- c67e6c6 DRC in single ports fixed. by mrg · 3 years, 8 months ago
- cfead8e Update with new single port macros by mrg · 3 years, 8 months ago
- e988856 Update SP SRAMs to have spare_wen0 by mrg · 3 years, 9 months ago
- 4a0200e Remove left/right separate pins by mrg · 3 years, 9 months ago
- 8bde8f8 Remove extra character by mrg · 3 years, 9 months ago
- 0d14b0b Use single clock, top-level gate place and route by mrg · 3 years, 9 months ago
- 0dd2159 Resolve clock port and net issue by making clock_mux by mrg · 3 years, 9 months ago
- 8188070 Change reset to resetn by mrg · 3 years, 9 months ago
- 8de4e28 Incrase PL_DIAMOND_SEARCH_HEIGHT by mrg · 3 years, 9 months ago
- 2cd561f Remove errors in configs by mrg · 3 years, 9 months ago
- b8597a7 Move sram_clk to user_project_wrapper by mrg · 3 years, 9 months ago
- 53295f0 Add custom SDC script by mrg · 3 years, 9 months ago
- 48dbc1e Update macros by mrg · 3 years, 9 months ago
- 2f1a8ef Debug user_project_wrapper verilog by mrg · 3 years, 9 months ago
- 44a125a Don't route clocks until debugged by mrg · 3 years, 9 months ago
- 231495b Don't check supply connectivity. Resolve multiple pin regex warning. by mrg · 3 years, 9 months ago
- 0418bc2 Update macro placement. Remove a dual port mem. by mrg · 3 years, 9 months ago
- 08b141b Initial floorplan by mrg · 3 years, 9 months ago
- 9e8c375 Add pins to sides of block. by mrg · 3 years, 9 months ago
- 34e4779 Make macro almost chip height by mrg · 3 years, 9 months ago
- 763d546 Increase area so we can have enough IO pins by mrg · 3 years, 9 months ago
- 1b30acd Delete clks.sdc by Amogh Lonkar · 3 years, 9 months ago
- 5bb2036 Macro for verilog based control module by AmoghLonkar · 3 years, 9 months ago
- 58d416f Clock selection at top level by AmoghLonkar · 3 years, 9 months ago
- cf608e2 Use control logic macro by AmoghLonkar · 3 years, 9 months ago
- bb967ab Disabled Klayout XOR step by AmoghLonkar · 3 years, 10 months ago
- 7c55d39 remove extra folders by Jesse Cirimelli-Low · 3 years, 10 months ago
- 20d0669 remove extra files from repo; gbl routing to 0.2 by Jesse Cirimelli-Low · 3 years, 10 months ago
- d55f176 Removed optimization envs because no standard cells by AmoghLonkar · 3 years, 10 months ago
- f27be30 Initial macro arrangement by AmoghLonkar · 3 years, 10 months ago
- d7ce953 Included single port files and fixed gds error by AmoghLonkar · 3 years, 10 months ago
- a51bbbe Disabled optimizations, much faster by AmoghLonkar · 3 years, 10 months ago
- 49efff8 Update config file by AmoghLonkar · 3 years, 10 months ago
- 63f0643 Removed macro placement for control unit by AmoghLonkar · 3 years, 10 months ago
- 41062a7 Updated config file to use pdn script and removed macro files for control logic by AmoghLonkar · 3 years, 10 months ago
- 520c9fb Placed macros far apart to avoid overlap by AmoghLonkar · 3 years, 10 months ago
- 00023dc Updated SRAM macro name by AmoghLonkar · 3 years, 10 months ago
- 220784c Added intial macro placement by AmoghLonkar · 3 years, 10 months ago
- 7d7491d Added wrapper gds and lef to env by AmoghLonkar · 3 years, 10 months ago
- accab47 Updating config file by AmoghLonkar · 3 years, 10 months ago
- f8d3dbf Update config.tcl by AmoghLonkar · 3 years, 10 months ago
- ced003a Adding script for Power Distribution Network. Taken from Professor's repo by AmoghLonkar · 3 years, 10 months ago
- 3308457 Added clock net and pdn script from professor's repo by AmoghLonkar · 3 years, 10 months ago
- 8090539 Changed paths to verilog dir by AmoghLonkar · 3 years, 10 months ago
- 1ad4c69 Initial config file for hardening macro by AmoghLonkar · 3 years, 10 months ago
- 609ec98 [DATA] Update views by manarabdelaty · 3 years, 11 months ago
- e542bdf Update caravel-lite references by manarabdelaty · 3 years, 11 months ago
- 32b6e9f Update submodule reference by manarabdelaty · 3 years, 11 months ago
- b41301c Added top level makefile by manarabdelaty · 3 years, 11 months ago
- 1766544 [CI] Install full caravel for build tasks like ship/setid by manarabdelaty · 4 years ago
- 548e5a7 [DATA] Adjust user_proj_example/config.tcl by Ahmed Ghazy · 4 years ago
- d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 4 years ago
