commit	9e8c375e4425fed8d07a7f02e6ac7f70afdb1ca2	[log] [tgz]
author	mrg <mrg@ucsc.edu>	Mon Jun 14 08:22:13 2021 -0700
committer	mrg <mrg@ucsc.edu>	Mon Jun 14 08:22:13 2021 -0700
tree	6a0ea1c6147102c2b0212a4db2cc045dc07037f1
parent	3dbe3c4c7a231a8115567bf4679be5ed00a31468 [diff]

Add pins to sides of block.

openlane/openram_testchip/pin_order.cfg[Added - diff]
verilog/rtl/openram_defines.v[Added - diff]
verilog/rtl/openram_testchip.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

4 files changed

tree: 6a0ea1c6147102c2b0212a4db2cc045dc07037f1

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.