)]}'
{
  "commit": "9e8c375e4425fed8d07a7f02e6ac7f70afdb1ca2",
  "tree": "6a0ea1c6147102c2b0212a4db2cc045dc07037f1",
  "parents": [
    "3dbe3c4c7a231a8115567bf4679be5ed00a31468"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Mon Jun 14 08:22:13 2021 -0700"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Mon Jun 14 08:22:13 2021 -0700"
  },
  "message": "Add pins to sides of block.\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "bbd4cba0821403170488efb5f8377ef623282c8f",
      "new_mode": 33188,
      "new_path": "openlane/openram_testchip/pin_order.cfg"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ff695e86784affbb8c905912ff7d8d18ffd457df",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_defines.v"
    },
    {
      "type": "modify",
      "old_id": "d3638741561d69f22cd8fda769ad56289e9b5b20",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "f8aa54e4aee4cbca5aeaf352316fac668708e10f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "986b5430437fea083505b5fce2f69f27050c594c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "86c92ded70a1bb1b557b9a4d5f52149bae1861e3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
