Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
e98885619012cd016322416e415e4ca7fa24ec60
commit
e98885619012cd016322416e415e4ca7fa24ec60
[
log
]
[
tgz
]
author
mrg <mrg@ucsc.edu>
Fri Jun 18 08:01:45 2021 -0700
committer
mrg <mrg@ucsc.edu>
Fri Jun 18 08:01:45 2021 -0700
tree
f1dbd0d2fd628a211c70aa94b549406720e2d245
parent
1946164ce18aa97f7c9803702be09dcd4933c11b
[
diff
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Update SP SRAMs to have spare_wen0
gds/sram_1rw0r0w_32_1024_sky130.gds
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diff
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gds/sram_1rw0r0w_32_256_sky130.gds
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diff
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gds/sram_1rw0r0w_32_512_sky130.gds
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diff
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gds/sram_1rw0r0w_64_512_sky130.gds
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diff
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lef/sram_1rw0r0w_32_1024_sky130.lef
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diff
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lef/sram_1rw0r0w_32_256_sky130.lef
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diff
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lef/sram_1rw0r0w_32_512_sky130.lef
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diff
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lef/sram_1rw0r0w_64_512_sky130.lef
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diff
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openlane/user_project_wrapper/config.tcl
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diff
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verilog/rtl/openram_defines.v
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diff
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verilog/rtl/sram_1rw0r0w_32_1024_sky130.v
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diff
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verilog/rtl/sram_1rw0r0w_32_256_sky130.v
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diff
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verilog/rtl/sram_1rw0r0w_32_512_sky130.v
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diff
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verilog/rtl/sram_1rw0r0w_64_512_sky130.v
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verilog/rtl/user_project_wrapper.v
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diff
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15 files changed
tree: f1dbd0d2fd628a211c70aa94b549406720e2d245
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
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Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.
