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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/2f1a8ef2cebf784aa74ff39015e9fa4bd0d4f25b
commit
2f1a8ef2cebf784aa74ff39015e9fa4bd0d4f25b
[log] [tgz]
author
mrg <mrg@ucsc.edu>
Mon Jun 14 13:26:17 2021 -0700
committer
mrg <mrg@ucsc.edu>
Mon Jun 14 13:26:17 2021 -0700
tree
d5d20b73980d35bb5fecf4fd45bb0d46cd4598b4
parent
44a125ad32b1dd67b3da2debc5e42d7d6953ad28 [diff]
Debug user_project_wrapper verilog
3 files changed
tree: d5d20b73980d35bb5fecf4fd45bb0d46cd4598b4
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. single_port/
  11. spi/
  12. verilog/
  13. caravel
  14. .gitignore
  15. .gitmodules
  16. info.yaml
  17. LICENSE
  18. Makefile
  19. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.