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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
818807053051611ccc25c9a241c2cbab008d8503
commit
818807053051611ccc25c9a241c2cbab008d8503
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log
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author
mrg <mrg@ucsc.edu>
Wed Jun 16 20:34:50 2021 -0700
committer
mrg <mrg@ucsc.edu>
Wed Jun 16 20:34:50 2021 -0700
tree
a8ec372a07d8d86c9a1ccc047e2ec69fbd74c1b4
parent
af01516d9ad272c99ee91001710fa1411d1eeee9
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Change reset to resetn
openlane/openram_testchip/config.tcl
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openlane/openram_testchip/openram_testchip.sdc
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openlane/user_project_wrapper/config.tcl
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openlane/user_project_wrapper/user_project_wrapper.sdc
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verilog/rtl/openram_testchip.v
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verilog/rtl/user_proj_example.v
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verilog/rtl/user_project_wrapper.v
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7 files changed
tree: a8ec372a07d8d86c9a1ccc047e2ec69fbd74c1b4
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.
