| commit | 5bb203653907a595841c6940c420899e063e7541 | [log] [tgz] |
|---|---|---|
| author | AmoghLonkar <alonkar@ucsc.edu> | Fri Jun 11 11:38:13 2021 -0700 |
| committer | AmoghLonkar <alonkar@ucsc.edu> | Fri Jun 11 11:38:13 2021 -0700 |
| tree | 485d3e771d35945c516544e2cca12f8e9e20ec21 | |
| parent | c0fe5560492c461c40569eece5d154ecca54ed6a [diff] |
Macro for verilog based control module
| :exclamation: Important Note |
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Refer to README for this sample project documentation.