tree 485d3e771d35945c516544e2cca12f8e9e20ec21
parent c0fe5560492c461c40569eece5d154ecca54ed6a
author AmoghLonkar <alonkar@ucsc.edu> 1623436693 -0700
committer AmoghLonkar <alonkar@ucsc.edu> 1623436693 -0700

Macro for verilog based control module