Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-009
/
4a0200ec8174b24306e086ef7d39431f675d397b
commit
4a0200ec8174b24306e086ef7d39431f675d397b
[
log
]
author
mrg <mrg@ucsc.edu>
Thu Jun 17 16:45:35 2021 -0700
committer
mrg <mrg@ucsc.edu>
Thu Jun 17 16:45:35 2021 -0700
tree
ad45bf4c1f9fee1de562e59801872466f8afc403
parent
076f16c3c999e23d9ecde47e72427c3a95b153a9
[
diff
]
Remove left/right separate pins
openlane/user_project_wrapper/config.tcl
[
diff
]
verilog/rtl/openram_testchip.v
[
diff
]
verilog/rtl/user_project_wrapper.v
[
diff
]
3 files changed
tree: ad45bf4c1f9fee1de562e59801872466f8afc403
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
single_port/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
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Please fill in your project documentation in this README.md file
Refer to
README
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