foundryslot-001TinyTapeout: Test to put 500 100x100um designs onto one chip. More info at https://tinytapeout.com.slot-002Zero to ASIC...: Zero to ASIC course group submission MPW7.slot-003Microwatt MPW7: Microwatt is a 64 bit OpenPOWER core written in VHDL.slot-004YONGA-CAN Controller: YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.slot-005RocketAlpha: This project demonstrates a customized Rocket Chip SoC, generated from Chipyard.slot-006Riscduino-DCore(D3): Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.slot-007Riscduino-QCore(Q2): Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.slot-008Riscduino-SCore(S4): Arduino pin compatible Single RISCV 32 Bit core Project.slot-009Nanofabrication...: Test Structures for NIST's Nanofabrication Project.slot-010SRAMTestVehicleG3: Iteration on SRAM test vehicle that failed to be selected for MPW5 and MPW6.slot-011Analog Frontend...: This is a simple analog fronted for particle detection.slot-012ISA 16-bit Microprocessor: This is simple microprocessor.slot-013ReRAM crossbar: ReRAM 16x16 array characterisation, including forming, incremental set and reset, and parallel analog read for vector-matrix multiplication.slot-014Trainable NN: Neural network with on-chip training.slot-01510b ADC and...: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network.slot-016Bitcoin Mining Asic: This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.slot-017YONGA-MCU: Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C.slot-018SoomRV: SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor.slot-019Marmot RISC-V...: Increased features (plus 8KB D-Cache and 3ch PWM）and improved clocking (25MHz > 50MHz) by mastering tools since MPW-6 MARMOT RISC-V, three months ago.slot-020Mixed_signal_circ...: We have a 2x2 1T1R ReRam structure and a C4 Filter as well as some other supporting analog circuits for mixed-signal computing.slot-021FPGA_Programming_...: User project wrapper includes the PMU version 3, SOFA 2x2 FPGA generated using OpenFPGA, and AES/SHA cores.slot-022WARP-V: WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I.slot-023Leaf (mpw7): Leaf is a small 32-bit RISC core for simple applications.slot-024In memory computing SRAM: SRAM in memory computing : The project includes SRAM In Memory Computing Accelerator.slot-025RNG based on a...: A random number generator that uses the chaotic signals from a figaro based ring oscillator to generate bits.slot-026ReRAM-Controller-MPW7_v2: This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.slot-027Enhanced Chaotic...: Two general frameworks called NLCS and FPCS are developed for building robust chaotic system based on existing seed maps.slot-028In memory computing RRAM: The project includes RRAM In Memory Computing Accelerator, by researchers mentioned below under the supervision of Prof: Manan Suri (NVM & Neuromorphic Hardware Research Group IIT-Delhi, https://web.slot-029slot-030TopmetalSe-DPS: The TopmetalSe is a pixelated charge sensor in the Skywater 130nm process, designed for the Selena Neutrino experiment as an imager for rare nuclear processes in amorphous Selenium.slot-031Chaos Automaton: An array of 'Chaos Cells' that pass data onto one another in a loop, allowing for modifications to the data based on inputs, while the entire snake of data can be read at once.slot-032slot-033Waveform Generator: A generic waveform generator divided into stimulus and driver units that can be arbitrarily interconnected.slot-034Rift2Core: Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.slot-035Rift2Go_2300: This is a real Rift2Core CPU now, I remove L2-cache, and implement the L1-ICache L1-Dcache with Flip-flop.slot-036slot-037Systolic Array...: Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs.slot-038crypto_aes128: AES128 project test.slot-039Graphics Controller: The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.slot-040PRGA-test: An initial attempt to create a Test chip. 