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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-032 / HEAD
  1. 87679b6 final gds oasis by Jeff DiCorpo · 1 year, 5 months ago main
  2. ac660c8 Updated readme. by Charlie · 1 year, 11 months ago
  3. 607c8c7 Rebuild with fixes to core access to memory. by Charlie · 1 year, 11 months ago
  4. 4281fdf Added additional core memory tests to verify read from flash and writes to gpio. by Charlie · 1 year, 11 months ago
  5. 95c709c Fixed cores not being able to access the wishbone bus. by Charlie · 1 year, 11 months ago
  6. 933bd6b Fixed performing load instructions not triggering a read from the local memory controller. by Charlie · 1 year, 11 months ago
  7. 5704b64 Added test for the cores ability to access memory. by Charlie · 1 year, 11 months ago
  8. 9fa5cd6 Rebuild with changes to caravel host which where not included in previous rebuild. Also removed GL simulations from GitHub action as they take too long and where causing it to time out. by Charlie · 1 year, 11 months ago
  9. 8790257 Rebuild with fixes to flash controller and wishbone bus. by Charlie · 1 year, 11 months ago
  10. 6190297 Fixed flash controller using the wrong address when storing data in the sram cache. Also fixed some problems with the flash test. by Charlie · 1 year, 11 months ago
  11. 63c22b1 Fixed an additional clock cycle being generated by the flash controller. by Charlie · 1 year, 11 months ago
  12. bddc1c1 Fixed access to the wishbone bus causing it to lock infinitely if an address is used that isn't the SoC wishbone bus. by Charlie · 1 year, 11 months ago
  13. 0850b7c Merge branch 'Development' by Charlie · 1 year, 11 months ago
  14. 1f59cbf Rebuild with updated spi, flash device, and other small fixes. by Charlie · 1 year, 11 months ago
  15. e14d7b8 Added a simple flash interface controller. by Charlie · 1 year, 11 months ago
  16. 9bbab5f Added test for user flash interface. by Charlie · 1 year, 11 months ago
  17. 9714d8c Added buffers to data registers. by Charlie · 1 year, 11 months ago
  18. 65d4228 Updated the SPI test to include a test of the inverted clock mode. Also fixed a number of problems with the SPI implementation and added a status register for determining if data is still being sent. by Charlie · 1 year, 11 months ago
  19. 9811238 Added SPI test. by Charlie · 1 year, 11 months ago
  20. 1d03f86 Updated GitHub workflow so that it will run all rtl tests, and also added the coreArch gl test. by Charlie · 1 year, 11 months ago
  21. f424330 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  22. 4d8e1f2 Full rebuild with additions to core, and other fixes. by Charlie · 1 year, 11 months ago
  23. 7ed4bee Fixed incorrect command when running GL core architecture tests. Also added compiled test program so that the test can be run through the OpenLane system. by Charlie · 1 year, 11 months ago
  24. 224e6ad Fixed valid time ranges in PWM test. Also added message saying valid range if the timing test fails. by Charlie · 1 year, 11 months ago
  25. fab5f03 Fixed off by one error on the default PWM top compare value. by Charlie · 1 year, 11 months ago
  26. 0cd43a2 Added test for PWM peripheral. by Charlie · 1 year, 11 months ago
  27. 238b999 Fixed that the previous change used the full counter value rather than the scaled counter value for comparing to the top value. by Charlie · 1 year, 11 months ago
  28. b283c6f Added separate counter top register to PWM devices. This stores the full mask allowing more control over the clock frequency. Also fixed a number of PWM issues including that data could not be read from registers, and that if the top value is set to a value under the current counter value the counter would not reset. by Charlie · 1 year, 11 months ago
  29. c561c88 Fixed a number of small issues. by Charlie · 1 year, 11 months ago
  30. 5292e79 Added buffers to irq lines from GPIO and PWM peripherals. by Charlie · 1 year, 11 months ago
  31. e768ce4 Fixed that the PWM device was using a wildly wrong reset value. by Charlie · 1 year, 11 months ago
  32. 530e657 Added buffer to UART signals to interrupt and status register. This should help with some timing issues. Also fixed a bug where the wrong signal was being used for the Rx data available interrupt. by Charlie · 1 year, 11 months ago
  33. 1fbc0bb Added peripheral interrupts by Charlie · 1 year, 11 months ago
  34. f0597c4 Fixed branch and jump instructions not generating instruction address misalignment exceptions when jumping to a non word aligned address. by Charlie · 1 year, 11 months ago
  35. 546583c Added RISCV spec. by Charlie · 1 year, 11 months ago
  36. a4827b3 Added trap handling to core. by Charlie · 1 year, 11 months ago
  37. e78d211 Fixed arithmetic right shifts not sign extending correctly. by Charlie · 1 year, 11 months ago
  38. 17641e2 Fixed store instructions not using the correct byte mask. by Charlie · 1 year, 11 months ago
  39. c9949d1 Fixed that non word aligned loads would not have the data shifted. Also fixed signed loads. by Charlie · 1 year, 11 months ago
  40. cfdb424 Fixed load word instructions being marked as invalid. by Charlie · 1 year, 11 months ago
  41. a56209c Fixed that address misalignment error bit could be set when not performing a load or store instruction. This means that some other instructions would trigger the core to lock, when performing valid instructions. by Charlie · 1 year, 11 months ago
  42. c678a2e Fixed ALU immediate instructions producing the wrong result if the aluAlt bit is set, even when this signal is not used in the instruction. by Charlie · 1 year, 11 months ago
  43. 7d855db Added core architecture simulation. Currently this will only work locally with some other applications installed. Already used this to fix AUIPC instruction not actually adding the program counter, by Charlie · 1 year, 11 months ago
  44. bf7d214 Added assignments to unused input pins, this helps GL simulations work now that input pins are actually connected. Also made some ease of use changes, such as adding a script to copy simulation results, and automatically copy guide file when regenerating guide view. by Charlie · 1 year, 11 months ago
  45. 600ce3a Re added ore PC GL simulation to GitHub workflow. Between this and the GPIO test, it should ensure nothing major is missing from the SoC, and these simulations should be just about fast enough to run. by Charlie · 1 year, 11 months ago
  46. 1a18a97 Added additional modules to variable dump after GL simulations. This means that its actually possible to see what's happening on the wishbone bus in the event of a simulation failing. by Charlie · 1 year, 11 months ago
  47. e67733d Added CSR registers to core. These include the basic counters and status registers. by Charlie · 1 year, 11 months ago
  48. 753ef0c Added JTAG core management controller. This is untested and don't use a standard method of using JTAG for managing a core. However, if it works, a custom interface could be written to allow programming the core over JTAG. by Charlie · 1 year, 11 months ago
  49. 9e72728 Fixed gpio not getting input connections (a bit more) due to verilog being dumb and not correctly parsing a mux inside a mux when performing syntheses, even though it works correctly in rtl simulation. by Charlie · 1 year, 11 months ago
  50. 626c8dc Fixed GL simulations not working properly due to missing pullup on mprj_io[3]. This is needed to make sure the management core doesn't end up in an invalid reset state. Also fixed nextTest method which wasn't correctly setting the test passed pin low if a test failed. This uncovered a some mistake made in the GPIO, memory, and UART tests, which are now also fixed. These included input pins not being connected to anything within the peripherals macro. by Charlie · 1 year, 11 months ago
  51. 1f2caf5 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  52. bcdb9c9 Updated art macro so that it can pass prechecks. by Charlie · 1 year, 11 months ago
  53. 6758205 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  54. 9f21750 Updated Art macro to possibly pass prechecks. by Charlie · 1 year, 11 months ago
  55. 6885aec Added memory test. This check that all regions of memory can be written to and read from, and that reading from unused parts of memory gives the correct value. by Charlie · 1 year, 11 months ago
  56. bda2da0 Rebuilt with recent fixes. Also re-added GL simulation to GitHub workflow. by Charlie · 1 year, 11 months ago
  57. 7b09468 Fixed VGA pixel data being misaligned with synchronisation signals. by Charlie · 1 year, 11 months ago
  58. 6ab7edd Fixed VGA using the wrong pixel stretch size, and using the wrong pixel data from memory. by Charlie · 1 year, 11 months ago
  59. 6fb002f Fixed some issues with VGA pixel counters not changing correctly. by Charlie · 1 year, 11 months ago
  60. e88c884 Fixed timing valid pin being inverted when output error in video test. by Charlie · 1 year, 11 months ago
  61. b2e455b Added video device simulation test, and new VGA state register which contains synchronisation signals. Also fixed some issues with register addresses, and the VGA signal generation. The video test doesn't currently validate that the correct pixels are displayed, but it does test the synchronisation times. by Charlie · 1 year, 11 months ago
  62. 2746c44 Made fixes to UART device and caravel host to enable UART-rtl test to pass. Also updated corePC test to use the newer GPIO registers. by Charlie · 1 year, 11 months ago
  63. 823b8ab Merge branch 'Development' by Charlie · 1 year, 11 months ago
  64. d52c5c2 Updated GitHub workflow to uncompress the Art gds file so it can be used in building the user project. by Charlie · 1 year, 11 months ago
  65. fdffa98 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  66. 7e13152 Removed art from art module so that it doesn't cause DRC errors (this will be changed back when a fix for this is found). Also added set, clear, and toggle registers to gpio for easier control. This also makes it easier for both cores to write to gpio without clearing what the other core has set. by Charlie · 1 year, 11 months ago
  67. e4118ea Renamed Counter.v to use the upper case first letter. This allows the file to be used when building on case sensitive file systems. Strangely this wasn't a problem when using Ubuntu through WSL. by Charlie · 1 year, 11 months ago
  68. 273a77b Fixed directory that GitHub workflows checks for finding precheck results. by Charlie · 1 year, 11 months ago
  69. dd6cb52 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  70. 9cc2031 Reverted to older OpenLane version, as it seems this is a requirement for MPW submission. by Charlie · 1 year, 11 months ago
  71. d7d2d89 Merge branch 'Development' by Charlie · 1 year, 11 months ago
  72. 794a27c Rebuilt with recent changes. by Charlie · 1 year, 11 months ago
  73. 257d283 Removed commented out tests completely from GitHub workflow file, as the file now has an error. by Charlie · 1 year, 11 months ago
  74. a504e94 Changed how VGA reads pixel data from sram so that it should work correctly. by Charlie · 1 year, 11 months ago
  75. 52e7ba1 Updated Github workflow to use the correct mpw precheck version. Also disabled tests that haven't been written yet. by Charlie · 1 year, 11 months ago
  76. 4562681 Re-added licence and CI badges to readme. by Charlie · 1 year, 11 months ago
  77. 5286602 Made a number of fixes and changes which now allows the cores to pass the corePC simulation test. This has required the core size to increased by Charlie · 1 year, 11 months ago
  78. 4443fea Added read back of test memory to core program counter test. by Charlie · 1 year, 11 months ago
  79. c138fb0 Added core program counter test. Also fixed the core not putting any of the core in the macro. This was caused by the unimplemented JTAG device not sending a signal to the core management, preventing it from ever allowing the core to run, resulting it being optimised away. by Charlie · 1 year, 11 months ago
  80. 951f5a3 Updated GitHub workflow to harden and test the correct modules. by Charlie · 1 year, 11 months ago
  81. 2ccd997 Merge pull request #3 from Wevel/Development by Wevel · 1 year, 11 months ago
  82. ff79e92 Got user_project_wrapper to build successfully. There are still problems to be resolved, but this is now a by Charlie · 1 year, 11 months ago
  83. 99bde90 Fixed spelling error in source file name. by Charlie · 1 year, 11 months ago
  84. 0ba103f Updated rendering of guide file to show layers better, this now also shows macro positions using a custom macro placement json file. Also added generation of macro position configuration using the macro placement file. by Charlie · 1 year, 11 months ago
  85. 049d4be Fixed UART test not checking for the correct status bit. Also added some extra checks to make sure data leaves the FIFO buffers correctly. by Charlie · 1 year, 11 months ago
  86. 4dfa791 Added UART test . by Charlie · 1 year, 11 months ago
  87. 2b18208 Fixed uart device outputting data when not enabled. Also fixed uart using the wrong cycles per bit value. by Charlie · 1 year, 11 months ago
  88. bedb595 Fixed N input mux not generating an output signal. by Charlie · 1 year, 11 months ago
  89. 2988523 Fixed wishbone slave stall signal staying on for an extra clock cycle. by Charlie · 1 year, 11 months ago
  90. e312600 Updated GPIO test to set the success pin high before the test starts, so that if it fails on the first test its more clear. by Charlie · 1 year, 11 months ago
  91. 7d7207a Updated testing setup to remove example tests, and provide a proper GPIO test which passes when using verify rtl. by Charlie · 1 year, 11 months ago
  92. e851b8a Fixed UART sending a single bit of data on reset. by Charlie · 1 year, 11 months ago
  93. aeb29be Added gpio input buffer to remove unknown data bits. by Charlie · 1 year, 11 months ago
  94. 8b2f283 Fixed wishbone slaves not providing read data on the correct clock cycle. by Charlie · 1 year, 11 months ago
  95. 025b919 Fixed user macros not being connected to PDN. Rotated SRAM macros are still not connected, so the full build still fails. by Charlie · 1 year, 11 months ago
  96. b8c7bb2 Made some small changes to try to get PDN to connect to macros. Also fixed some missing logic in the core macro. However, most of the macro still does not get built. by Charlie · 2 years ago
  97. c6f707b Added info on tests that need to be implemented. by Charlie · 2 years ago
  98. 8afd017 Fixed core 1 SRAM macros not having the correct orientation. by Charlie · 2 years ago
  99. 8100c3e Added script to render image of routing guide files. This can be useful to make sure macros are placed correctly, but only when there are lots of wires near them. by Charlie · 2 years ago
  100. d6dcdf1 Updated collated logs after previous build. by Charlie · 2 years ago