Fixed performing load instructions not triggering a read from the local memory controller.
1 file changed
RISC-V SoC designed for the Efabless Open MPW Program. This project
- Dual RV32I cores
- Per core SRAM
- JTAG interface
- External flash controller
- Shared video SRAM
- Configurable VGA output
- 3x UART ports + 1 internal to caravel
- 1x SPI ports
- 4x PWM counters with 4x separate outputs (2 are internal read only)
- CaravelHost: Success
- ExperiarCore: Success
- Flash: Success
- Peripherals: Success
- Video: Success
- WishboneInterconnect: Success
- user_project_wrapper: Success
verify-video-rtl: Success (Not validating correct pixel data)
verify-flash-gl: Not run
Need to do
- Make final version of art
- Decide on probe values
- Check for any remaining errors
- Misaligned architecture instructions
- Look into simulation with CVC
- Write macro level simulations to get more coverage due to shorter simulations
- Add JTAG test
- Add interrupt test
- Add uart pin swapping
- Page based flash controller
- Tile map rendering
- Fetch next instruction a clock cycle earlier so instructions only take 2 cycles
- Allow JTAG to read from wishbone bus
Reference work and inspiration
- Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
- Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
- Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
- Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.