Added video device simulation test, and new VGA state register which contains synchronisation signals. Also fixed some issues with register addresses, and the VGA signal generation. The video test doesn't currently validate that the correct pixels are displayed, but it does test the synchronisation times.
11 files changed
tree: cccb379f022c3c6503d757eb6579cdddf9588b58
- .github/
- def/
- docs/
- gds/
- lef/
- mag/
- maglef/
- openlane/
- sdc/
- sdf/
- signoff/
- spef/
- spi/
- verilog/
- .gitignore
- LICENSE
- Makefile
- README.md
README.md
ExperiarSoC
RISC-V SoC designed for the Efabless Open MPW Program. This project
Features
- Dual RV32I cores
- Per core SRAM
- JTAG interface
- External flash controller
- Shared video SRAM
- Configurable VGA output
- 3x UART ports + 1 internal to caravel
- 1x SPI ports
- 4x PWM counters with 4x separate outputs (2 are internal read only)
Memory Map
Macro Layout
Build Status
- CaravelHost: Success
- ExperiarCore: Success
- Flash: Success
- Peripherals: Success
- Video: Success
- WishboneInterconnect: Success
- user_project_wrapper: Success
Several macros have max slew violations.
Tests
RTL
verify-peripheralsGPIO-rtl: Success
verify-peripheralsUART-rtl: Success
verify-peripheralsSPI-rtl: Not implemented
verify-peripheralsPWM-rtl: Not implemented
verify-memory-rtl: Not implemented
verify-video-rtl: Not run
verify-corePC-rtl: Success
verify-coreMem-rtl: Not implemented
verify-coreArch-rtl: Not implemented
GL
verify-peripheralsGPIO-gl: Failed
verify-peripheralsUART-gl: Failed
verify-peripheralsSPI-gl: Not implemented
verify-peripheralsPWM-gl: Not implemented
verify-memory-gl: Not implemented
verify-video-gl: Not implemented
verify-corePC-gl: Failed
verify-coreMem-gl: Not implemented
verify-coreArch-gl: Not implemented
Need to do
- Write remaining tests (and fix everything until they pass)
- Fix timing violations
- Fix precheck errors
Could do
- Add uart pin swapping
- Flash controller
- JTAG core management controller
- CSRs
- More tests
- Tile map rendering
- Change peripheral bus design to have a read ready signal
- Fetch next instruction a clock cycle earlier so instructions only take 2 cycles
Reference work and inspiration
- Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
- Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
- Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
- Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
