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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-032 / 17641e27390956c21ae1c415c2d534e6a728bb40
commit17641e27390956c21ae1c415c2d534e6a728bb40[log] [tgz]
authorCharlie <charlie.david.smith@hotmail.co.uk>Mon May 30 00:11:59 2022 +0100
committerCharlie <charlie.david.smith@hotmail.co.uk>Mon May 30 00:11:59 2022 +0100
tree0e991f6b099c44487246f61f4fedd85bb8b86751
parentc9949d15dc3b31e5a32e18b114ae3206407a4d92 [diff]
Fixed store instructions not using the correct byte mask.
1 file changed
tree: 0e991f6b099c44487246f61f4fedd85bb8b86751
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

License UPRJ_CI

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program. This project

Block diagram of Experiar SoC

Features

  • Dual RV32I cores
  • Per core SRAM
  • JTAG interface
  • External flash controller
  • Shared video SRAM
  • Configurable VGA output
  • 3x UART ports + 1 internal to caravel
  • 1x SPI ports
  • 4x PWM counters with 4x separate outputs (2 are internal read only)

Memory Map

Memory map for Experiar SoC

Macro Layout

Build Status

  • CaravelHost: Success
  • ExperiarCore: Success
  • Flash: Success
  • Peripherals: Success
  • Video: Success
  • WishboneInterconnect: Success
  • user_project_wrapper: Success

Several macros have max slew violations.

Tests

RTL

verify-peripheralsGPIO-rtl: Success

verify-peripheralsUART-rtl: Success

verify-peripheralsSPI-rtl: Not implemented

verify-peripheralsPWM-rtl: Not implemented

verify-memory-rtl: Success

verify-video-rtl: Success (Not validating correct pixel data)

verify-corePC-rtl: Success

verify-coreMemory-rtl: Not implemented

verify-coreArch-rtl: Not implemented

GL

verify-peripheralsGPIO-gl: Success

verify-peripheralsUART-gl: Success

verify-peripheralsSPI-gl: Not implemented

verify-peripheralsPWM-gl: Not implemented

verify-memory-gl: Success

verify-video-gl: Success

verify-corePC-gl: Success

verify-coreMemory-gl: Not implemented

verify-coreArch-gl: Not implemented

Need to do

  • Write SPI test
  • Write PWM test
  • Write core arch test
  • Fix timing violations
  • Make final version of art
  • Disable routing on met5

Could do

  • Look into simulation with CVC
  • Write macro level simulations to get more coverage due to shorter simulations
  • Add JTAG test
  • Add uart pin swapping
  • Flash controller
  • Interrupts
  • Tile map rendering
  • Fetch next instruction a clock cycle earlier so instructions only take 2 cycles
  • Allow JTAG to read from wishbone bus

Reference work and inspiration

  • Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
  • Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
  • Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
  • Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.