Added core architecture simulation. Currently this will only work locally with some other applications installed. Already used this to fix AUIPC instruction not actually adding the program counter,
17 files changed
tree: d831ff61fd3569f006b9bd387fea6d427675cdfe
- .github/
- def/
- docs/
- gds/
- lef/
- mag/
- maglef/
- openlane/
- sdc/
- sdf/
- signoff/
- spef/
- spi/
- verilog/
- .gitignore
- LICENSE
- Makefile
- README.md
README.md
ExperiarSoC
RISC-V SoC designed for the Efabless Open MPW Program. This project
Features
- Dual RV32I cores
- Per core SRAM
- JTAG interface
- External flash controller
- Shared video SRAM
- Configurable VGA output
- 3x UART ports + 1 internal to caravel
- 1x SPI ports
- 4x PWM counters with 4x separate outputs (2 are internal read only)
Memory Map
Macro Layout
Build Status
- CaravelHost: Success
- ExperiarCore: Success
- Flash: Success
- Peripherals: Success
- Video: Success
- WishboneInterconnect: Success
- user_project_wrapper: Success
Several macros have max slew violations.
Tests
RTL
verify-peripheralsGPIO-rtl: Success
verify-peripheralsUART-rtl: Success
verify-peripheralsSPI-rtl: Not implemented
verify-peripheralsPWM-rtl: Not implemented
verify-memory-rtl: Success
verify-video-rtl: Success (Not validating correct pixel data)
verify-corePC-rtl: Success
verify-coreMemory-rtl: Not implemented
verify-coreArch-rtl: Not implemented
GL
verify-peripheralsGPIO-gl: Success
verify-peripheralsUART-gl: Success
verify-peripheralsSPI-gl: Not implemented
verify-peripheralsPWM-gl: Not implemented
verify-memory-gl: Success
verify-video-gl: Success
verify-corePC-gl: Success
verify-coreMemory-gl: Not implemented
verify-coreArch-gl: Not implemented
Need to do
- Write SPI test
- Write PWM test
- Write core arch test
- Fix timing violations
- Make final version of art
- Disable routing on met5
Could do
- Look into simulation with CVC
- Write macro level simulations to get more coverage due to shorter simulations
- Add JTAG test
- Add uart pin swapping
- Flash controller
- Interrupts
- Tile map rendering
- Fetch next instruction a clock cycle earlier so instructions only take 2 cycles
- Allow JTAG to read from wishbone bus
Reference work and inspiration
- Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
- Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
- Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
- Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.
