Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-032 / 2b18208b708cd51459ee46c3c1d1531eed5ddbed
commit2b18208b708cd51459ee46c3c1d1531eed5ddbed[log] [tgz]
authorCharlie <charlie.david.smith@hotmail.co.uk>Sat May 21 22:32:57 2022 +0100
committerCharlie <charlie.david.smith@hotmail.co.uk>Sat May 21 22:32:57 2022 +0100
tree89f5f29b91cee87dd0396bd1d74a28db38957c83
parentbedb595d4dfe22d088efac99de78eb4ddc23322d [diff]
Fixed uart device outputting data when not enabled. Also fixed uart using the wrong cycles per bit value.
3 files changed
tree: 89f5f29b91cee87dd0396bd1d74a28db38957c83
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

ExperiarSoC

RISC-V SoC designed for the Efabless Open MPW Program. This project

Block diagram of Experiar SoC

Features

  • Dual RV32I cores
  • Per core SRAM
  • JTAG interface
  • External flash controller
  • Shared video SRAM
  • Configurable VGA output
  • 3x UART ports + 1 internal to caravel
  • 1x SPI ports
  • 4x PWM counters with 4x separate outputs (2 are internal read only)

Memory Map

Memory map for Experiar SoC

Macro Layout

Experiar SoC Macro Layout

Build Status

  • CaravelHost: Success
  • ExperiarCore: Success (Seem to be missing much of the core from the gds)
  • Flash: Success
  • Peripherals: Success
  • Video: Success
  • WishboneInterconnect: Success
  • user_project_wrapper: Rotated SRAM macoros not connected to power

Tests

RTL

verify-peripheralsGPIO-rtl: Success

verify-peripheralsUART-rtl: Not implemented

verify-peripheralsSPI-rtl: Not implemented

verify-peripheralsPWM-rtl: Not implemented

verify-memory-rtl: Not implemented

verify-video-rtl: Not implemented

verify-core-rtl: Not implemented

GL

verify-peripheralsGPIO-gl: Failed

verify-peripheralsUART-gl: Not implemented

verify-peripheralsSPI-gl: Not implemented

verify-peripheralsPWM-gl: Not implemented

verify-memory-gl: Not implemented

verify-video-gl: Not implemented

verify-core-gl: Not implemented

ToDo

  • Get it to build
  • Flash controller
  • JTAG core management controller
  • CSRs
  • Write more tests
  • Fix all of the errors

Reference work and inspiration

  • Zero to ASIC Course: Complete course on ASIC design. Also has useful references and terminology definitions.
  • Openlane Documentation: Reference for a lot of configuration. The Variables and Hardening Macros pages have been particularity useful.
  • Caravel Documentation: Reference for caravel and configuration. This seems slightly out of date, but an alternate version can be found in the github repository.
  • Riscduino: Used for inspiration and as a reference for using openlane. There are a number of similar aspects to this project, but all have been reimplemented rather than copied.