)]}'
{
  "commit": "2b18208b708cd51459ee46c3c1d1531eed5ddbed",
  "tree": "89f5f29b91cee87dd0396bd1d74a28db38957c83",
  "parents": [
    "bedb595d4dfe22d088efac99de78eb4ddc23322d"
  ],
  "author": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 22:32:57 2022 +0100"
  },
  "committer": {
    "name": "Charlie",
    "email": "charlie.david.smith@hotmail.co.uk",
    "time": "Sat May 21 22:32:57 2022 +0100"
  },
  "message": "Fixed uart device outputting data when not enabled. Also fixed uart using the wrong cycles per bit value.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c6b6e2557838e91bc38564be356ef3efa74b8c60",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/UART/UARTDevice.v",
      "new_id": "e52e86f6d4229c71262e7e62a0d29041561f19fd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/UART/UARTDevice.v"
    },
    {
      "type": "modify",
      "old_id": "6e983ff5a460eeee1a71b97cd48bb1dc209d0487",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/UART/UART_rx.v",
      "new_id": "bf8e8cea4488bedb0be61906e10a23d5ed0f0560",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/UART/UART_rx.v"
    },
    {
      "type": "modify",
      "old_id": "6c78d5b8fcffb3efe601b2bacf6beff9c3d48b9e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/Peripherals/UART/UART_tx.v",
      "new_id": "3fc73a55609c082517b21ec04a6010d27b2007fc",
      "new_mode": 33188,
      "new_path": "verilog/rtl/Peripherals/UART/UART_tx.v"
    }
  ]
}