| commit | b8c7bb25bfc0bb290de43a968359fd72e524018f | [log] [tgz] |
|---|---|---|
| author | Charlie <charlie.david.smith@hotmail.co.uk> | Sat May 21 01:21:54 2022 +0100 |
| committer | Charlie <charlie.david.smith@hotmail.co.uk> | Sat May 21 01:21:54 2022 +0100 |
| tree | 666cc67b9f67d23e6f517defc315862f53bba5ba | |
| parent | c6f707b8370c84ecdbb9fe6588da0838651287b3 [diff] |
Made some small changes to try to get PDN to connect to macros. Also fixed some missing logic in the core macro. However, most of the macro still does not get built.
RISC-V SoC designed for the Efabless Open MPW Program. This project
Runs a number of tests (currently just a very basic gpio test) from the management core to ensure the peripherals work correctly.
Tests the managment core has access to each sram region, and that data can be correctly writen and read.
Tests that the managment core can initialise the VGA device, and that the signal coresponding to this is generated. This will not produce a valid VGA signal as the simulation time would be too long.
Runs a number of tests on each core to ensure they function correctly, and can access all peripherals on the SoC.
