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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / f2a114e9a167d756dace2a8c68f2c061b64a9582 / . / sky130 / magic / sky130.tech
blob: f34aad5f6eda3c042213cb8c20591a830200b3fc [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards5d450d52022-01-22 15:31:32 -0500[diff] [blame]26 requires magic-8.3.260
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]66# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v5 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]85# sky130_fd_pr__photodiode photo Photodiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]86#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]87# (*) Note that ppres may extract into some generic type called
88# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
89# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]90#
91# (**) nFET and pFET in standard cells are the same as devices
92# outside of the standard cell except for the DRC rule for
93# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
94#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]95#-------------------------------------------------------------
96# The following devices are not extracted but are represented
97# only by script-generated subcells in the PDK.
98#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]145 dwell isosubstrate,isosub
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]146 dwell photodiode,photo
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]147
148# Wells
149 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well pwell,pw
151 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]152 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]153 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]154 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]155
156# Transistors
157 active nmos,ntransistor,nfet
158 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]159 -active npd,npdfet,sramnfet
160 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]161 active pmos,ptransistor,pfet
162 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]163 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]164 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]165 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]166 active mvnmos,mvntransistor,mvnfet
167 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]168 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]169 -active mvnmosesd,mvntransistoresd,mvnfetesd
170 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]171 active varactor,varact,var
172 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]173
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]174 active pmoslvt,pfetlvt
175 active pmosmvt,pfetmvt
176 active pmoshvt,pfethvt
177 active nmoslvt,nfetlvt
178 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]179 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]180 -active sramnvar,corenvar,corenvaractor
181 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182
183# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]184 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]185 active ndiff,ndiffusion,ndif
186 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]187 active mvndiff,mvndiffusion,mvndif
188 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]189 active ndiffc,ndcontact,ndc
190 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]191 active mvndiffc,mvndcontact,mvndc
192 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]193 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
194 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
195 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
196 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
197 active psubdiffcont,psubstratepcontact,psc,ptapc
198 active nsubdiffcont,nsubstratencontact,nsc,ntapc
199 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
200 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]201 -active obsactive
202 -active mvobsactive
203
204# Poly
205 active poly,p,polysilicon
206 active polycont,pc,pcontact,polycut,polyc
207 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]208 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]209
210# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]211 active npolyres,npres,mrp1
212 active ppolyres,ppres,xhrpoly
213 active xpolyres,xpres,xres,uhrpoly
214 active ndiffres,rnd,rdn,rndiff
215 active pdiffres,rpd,rdp,rpdiff
216 active mvndiffres,mvrnd,mvrdn,mvrndiff
217 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
218 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]219
220# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]221 active pdiode,pdi
222 active ndiode,ndi
223 active nndiode,nndi
224 active pdiodec,pdic
225 active ndiodec,ndic
226 active nndiodec,nndic
227 active mvpdiode,mvpdi
228 active mvndiode,mvndi
229 active mvpdiodec,mvpdic
230 active mvndiodec,mvndic
231 active pdiodelvt,pdilvt
232 active pdiodehvt,pdihvt
233 active ndiodelvt,ndilvt
234 active pdiodelvtc,pdilvtc
235 active pdiodehvtc,pdihvtc
236 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]237
238# Local Interconnect
239 locali locali,li1,li
240 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]241 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]243 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]244 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]245 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]246
247# Metal 1
248 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]249 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]250 metal1 via1,m2contact,m2cut,m2c,via,v,v1
251 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]252 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]253 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]254
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]255#ifdef RERAM
256 metal2 reram,rr
257#endif
258
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259# Metal 2
260 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]261 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]262 metal2 via2,m3contact,m3cut,m3c,v2
263 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]264 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]265
266# Metal 3
267 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]269 -metal3 obsm3
270#ifdef METAL5
271 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]272 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]273
274#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 cap1 mimcap,mim,capm
276 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]277#endif
278
279# Metal 4
280 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]282 -metal4 obsm4
283 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]284 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]285
286#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 cap2 mimcap2,mim2,capm2
288 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]289#endif
290
291# Metal 5
292 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]293 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]294 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]295 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]296#endif (METAL5)
297
298#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]299 metal5 mrdlcontact,mrdlc,pi1
300 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]301 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]302 metali pi2
303 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304#endif (REDISTRIBUTION)
305
306# Miscellaneous
307 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]308 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]309 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]310 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]311# fixed resistor width identifiers
312 -comment res0p35
313 -comment res0p69
314 -comment res1p41
315 -comment res2p85
316 -comment res5p73
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]317# fixed bipolar area identifiers
318 -comment pnp0p68
319 -comment pnp3p40
320 -comment npn1p00
321 -comment npn2p00
322 -comment npn11p0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]323
324end
325
326#-----------------------------------------------------
327# Magic contact types
328#-----------------------------------------------------
329
330contact
331 pc poly locali
332 ndc ndiff locali
333 pdc pdiff locali
334 nsc nsd locali
335 psc psd locali
336 ndic ndiode locali
337 ndilvtc ndiodelvt locali
338 nndic nndiode locali
339 pdic pdiode locali
340 pdilvtc pdiodelvt locali
341 pdihvtc pdiodehvt locali
342 xpc xpc locali
343
344 mvndc mvndiff locali
345 mvpdc mvpdiff locali
346 mvnsc mvnsd locali
347 mvpsc mvpsd locali
348 mvndic mvndiode locali
349 mvpdic mvpdiode locali
350
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]351 mcon locali metal1
352 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]353
354 via1 metal1 metal2
355 via2 metal2 metal3
356#ifdef METAL5
357 via3 metal3 metal4
358 via4 metal4 metal5
359#endif (METAL5)
360 stackable
361
362#ifdef METAL5
363#ifdef MIM
364 # MiM cap contacts are not stackable!
365 mimcc mimcap metal4
366 mim2cc mimcap2 metal5
367#endif (MIM)
368
369 padl m1 m2 m3 m4 m5 glass
370#else
371 padl m1 m2 m3 glass
372#endif (!METAL5)
373
374#ifdef REDISTRIBUTION
375 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]376 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]377#endif (REDISTRIBUTION)
378end
379
380#-----------------------------------------------------
381# Layer aliases
382#-----------------------------------------------------
383
384aliases
385
386 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]387 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]389 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]390 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]391 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]392 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]393 allfetsspecial scnfet,scpfet,scpfethvt
394 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]395 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]396
397 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
398 allnactive allnactivenonfet,allnfets
399 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]400 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]401
402 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
403 allpactive allpactivenonfet,allpfets
404 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]405 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]406
407 allactivenonfet allnactivenonfet,allpactivenonfet
408 allactive allactivenonfet,allfets
409
410 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
411
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]412 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]413 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]414 alldifflv allndifflv,allpdifflv
415 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
416 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
417 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
418
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]419 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]420 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]421 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]422 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]423 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]424 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
425 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
426 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
427 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
428
429 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]430 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]431
432 allpolyres mrp1,xhrpoly,uhrpoly,rmp
433 allpolynonfet *poly,allpolyres,xpc
434 allpolynonres *poly,allfets,xpc
435
436 allpoly allpolynonfet,allfets
437 allpolynoncap *poly,xpc,allfets,allpolyres
438
439 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
440 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
441 allndiffcontmv mvndc,mvnsc,mvndic
442 allpdiffcontmv mvpdc,mvpsc,mvpdic
443 allndiffcont allndiffcontlv,allndiffcontmv
444 allpdiffcont allpdiffcontlv,allpdiffcontmv
445 alldiffcontlv allndiffcontlv,allpdiffcontlv
446 alldiffcontmv allndiffcontmv,allpdiffcontmv
447 alldiffcont alldiffcontlv,alldiffcontmv
448
449 allcont alldiffcont,pc
450
451 allres allpolyres,allactiveres
452
453 allli *locali,coreli,rli
454 allm1 *m1,rm1
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]455#ifdef RERAM
456 allm2 *m2,rm2,reram
457#else (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]458 allm2 *m2,rm2
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]459#endif (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]460 allm3 *m3,rm3
461#ifdef METAL5
462 allm4 *m4,rm4
463 allm5 *m5,rm5
464#endif (METAL5)
465
466 allpad padl
467
468 psub pwell
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]469
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]470 obstypes obswell,mvobsactive,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]471 idtypes res0p35,res0p69,res1p41,res2p85,res5p73,pnp0p68,pnp3p40,npn1p00,npn2p00,npn11p0
472 blocktypes fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473
474end
475
476#-----------------------------------------------------
477# Layer drawing styles
478#-----------------------------------------------------
479
480styles
481 styletype mos
482 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]483 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]484 nwell nwell
485 pwell pwell
486 rpwell pwell ptransistor_stripes
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]487 photo nwell nwell_field_implant
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]488 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]489 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]490 pdiff pdiffusion
491 nsd ndiff_in_nwell
492 psd pdiff_in_pwell
493 nfet ntransistor ntransistor_stripes
494 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]495 npass ntransistor ntransistor_stripes
496 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 pfet ptransistor ptransistor_stripes
498 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]499 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]500 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]501 var polysilicon ndiff_in_nwell
502 ndc ndiffusion metal1 contact_X'es
503 pdc pdiffusion metal1 contact_X'es
504 nsc ndiff_in_nwell metal1 contact_X'es
505 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]506 corenvar polysilicon ndiff_in_nwell
507 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]509 pnp nwell ntransistor_stripes
510 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]511
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]512 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]513 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]514 pfethvt ptransistor ptransistor_stripes implant2
515 nfetlvt ntransistor ntransistor_stripes implant1
516 nsonos ntransistor implant3
517 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]518 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]519
520 mvndiff ndiffusion hvndiff_mask
521 mvpdiff pdiffusion hvpdiff_mask
522 mvnsd ndiff_in_nwell hvndiff_mask
523 mvpsd pdiff_in_pwell hvpdiff_mask
524 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]525 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]526 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
527 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]528 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]529 mvvar polysilicon ndiff_in_nwell hvndiff_mask
530 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
531 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
532 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
533 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
534
535 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]536 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]537 pc polysilicon metal1 contact_X'es
538 npolyres polysilicon silicide_block nselect2
539 ppolyres polysilicon silicide_block pselect2
540 xpc polysilicon pselect2 metal1 contact_X'es
541 rmp polysilicon poly_resist_stripes
542
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]543 res0p35 implant1
544 res0p69 implant1
545 res1p41 implant1
546 res2p85 implant1
547 res5p73 implant1
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]548 pnp0p68 implant1
549 pnp3p40 implant1
550 npn1p00 implant1
551 npn2p00 implant1
552 npn11p0 implant1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]553
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]554 pdiode pdiffusion pselect2
555 ndiode ndiffusion nselect2
556 pdiodec pdiffusion pselect2 metal1 contact_X'es
557 ndiodec ndiffusion nselect2 metal1 contact_X'es
558
559 nndiode ndiffusion nselect2 implant3
560 ndiodelvt ndiffusion nselect2 implant1
561 pdiodelvt pdiffusion pselect2 implant1
562 pdiodehvt pdiffusion pselect2 implant2
563 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
564 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
565 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
566
567 mvpdiode pdiffusion pselect2 hvpdiff_mask
568 mvndiode ndiffusion nselect2 hvndiff_mask
569 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
570 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
571 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
572
573 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]574 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]575 coreli metal1
576 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]577 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]578 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]579 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]580
581 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]582 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]583 rm1 metal2 poly_resist_stripes
584 obsm1 metal2
585 m2c metal2 metal3 via2arrow
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]586
587#ifdef RERAM
588 reram metal2 metal3 via2 contact_X'es
589#endif (RERAM)
590
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]591 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]592 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]593 rm2 metal3 poly_resist_stripes
594 obsm2 metal3
595 m3c metal3 metal4 via3alt
596 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]597 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]598 rm3 metal4 poly_resist_stripes
599 obsm3 metal4
600#ifdef METAL5
601#ifdef MIM
602 mimcap metal3 mems
603 mimcc metal3 contact_X'es mems
604 mimcap2 metal4 mems
605 mim2cc metal4 contact_X'es mems
606#endif (MIM)
607 via3 metal4 metal5 via4
608 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]609 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]610 rm4 metal5 poly_resist_stripes
611 obsm4 metal5
612 via4 metal5 metal6 via5
613 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]614 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]615 rm5 metal6 poly_resist_stripes
616 obsm5 metal6
617#endif (METAL5)
618#ifdef REDISTRIBUTION
619 mrdlc metal6 metal7 via6
620 metalrdl metal7
621 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]622 ubm metal8
623 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]624#endif (REDISTRIBUTION)
625
626 glass overglass
627 mrp1 poly_resist poly_resist_stripes
628 xhrpoly poly_resist silicide_block
629 uhrpoly poly_resist
630 ndiffres ndiffusion ndop_stripes
631 pdiffres pdiffusion pdop_stripes
632 mvndiffres ndiffusion hvndiff_mask ndop_stripes
633 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
634 comment comment
635 error_p error_waffle
636 error_s error_waffle
637 error_ps error_waffle
638 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]639 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]640
641 obswell cwell
642 obsactive implant4
643
644#ifndef METAL5
645 padl metal4 via4 overglass
646#else
647 padl metal6 via6 overglass
648#endif
649
650 magnet substrate_field_implant
651 rotate via3alt
652 fence via5
653end
654
655#-----------------------------------------------------
656# Special paint/erase rules
657#-----------------------------------------------------
658
659compose
660 compose nfet poly ndiff
661 compose pfet poly pdiff
662 compose var poly nsd
663
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]664 decompose npass poly ndiff
665 decompose npd poly ndiff
666 decompose scnfet poly ndiff
667 decompose nfetlvt poly ndiff
668 decompose nsonos poly ndiff
669
670 decompose ppu poly pdiff
671 decompose scpfet poly pdiff
672 decompose scpfethvt poly pdiff
673 decompose pfethvt poly pdiff
674 decompose pfetlvt poly pdiff
675 decompose pfetmvt poly pdiff
676 decompose corenvar poly nsd
677 decompose corepvar poly psd
678 decompose varhvt poly nsd
679
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]680 compose mvnfet poly mvndiff
681 compose mvpfet poly mvpdiff
682 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]683
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]684 decompose nnfet poly mvndiff
685 decompose mvnfetesd poly mvndiff
686 decompose mvnnfet poly mvndiff
687 decompose mvpfetesd poly mvpdiff
688
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]689 paint obsmcon locali via1
690 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]691
692 paint ndc nwell pdc
693 paint nfet nwell pfet
694 paint scnfet nwell scpfet
695 paint ndiff nwell pdiff
696 paint psd nwell nsd
697 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]698 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]699
700 paint pdc pwell ndc
701 paint pfet pwell nfet
702 paint scpfet pwell scnfet
703 paint pdiff pwell ndiff
704 paint nsd pwell psd
705 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]706 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]707
708 paint pdc coreli pdc
709 paint ndc coreli ndc
710 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]711 paint nsc coreli nsc
712 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]713 paint viali coreli viali
Tim Edwards4cbe2582022-01-20 14:45:23 -0500[diff] [blame]714 paint mvpdc coreli mvpdc
715 paint mvndc coreli mvndc
716 paint mvnsc coreli mvnsc
717 paint mvpsc coreli mvpsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]718
719 paint coreli pdc pdc
720 paint coreli ndc ndc
721 paint coreli pc pc
722 paint coreli nsc nsc
723 paint coreli psc psc
724 paint coreli viali viali
Tim Edwards5d450d52022-01-22 15:31:32 -0500[diff] [blame]725 paint coreli mvpdc mvpdc
726 paint coreli mvndc mvndc
727 paint coreli mvnsc mvnsc
728 paint coreli mvpsc mvpsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]729
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]730#ifdef RERAM
731 paint reram metal2 reram
732#endif (RERAM)
733
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]734#ifdef METAL5
735 paint m4 obsm4 m4
736 paint m5 obsm5 m5
737#endif (METAL5)
738end
739
740#-----------------------------------------------------
741# Electrical connectivity
742#-----------------------------------------------------
743
744connect
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]745 *nwell,*nsd,*mvnsd,dnwell,pnp,photo *nwell,*nsd,*mvnsd,dnwell,pnp,photo
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]746 pwell,*psd,*mvpsd,npn,isosub pwell,*psd,*mvpsd,npn,isosub
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]747 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]748 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]749#ifdef RERAM
750 *m2,m2fill,reram *m2,m2fill,reram
751#else (!RERAM)
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]752 *m2,m2fill *m2,m2fill
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]753#endif (!RERAM)
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]754 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]755#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]756 *m4,m4fill *m4,m4fill
757 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]758#ifdef MIM
759 *mimcap *mimcap
760 *mimcap2 *mimcap2
761#endif (MIM)
762#endif (METAL5)
763 allnactivenonfet allnactivenonfet
764 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]765 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]766#ifdef REDISTRIBUTION
767 # RDL connects to m5 (i.e., padl) through glass cut
768 *mrdl *mrdl
769 glass metrdl
770#endif (REDISTRIBUTION)
771end
772
773#-----------------------------------------------------
774# CIF/GDS output layer definitions
775#-----------------------------------------------------
776# NOTE: All values in this section MUST be multiples of 25
777# or else magic will scale below the allowed layout grid size
778
779cifoutput
780
781#----------------------------------------------------------------
782style gdsii
783# NOTE: This section is used for actual GDS output
784#----------------------------------------------------------------
785 scalefactor 10 nanometers
786 options calma-permissive-labels
787 gridlimit 5
788
789#----------------------------------------------------------------
790# Create a temp layer from the cell bounding box for use in
791# generating ID layers. Note that "boundary", unlike "bbox",
792# requires the FIXED_BBOX property (abutment box) in the cell.
793#----------------------------------------------------------------
794 templayer CELLBOUND
795 boundary
796
797#----------------------------------------------------------------
798# BOUND
799#----------------------------------------------------------------
800 layer BOUND CELLBOUND
801 calma 235 4
802
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]803#----------------------------------------------------------------
804# DNWELL
805#----------------------------------------------------------------
806
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]807 layer DNWELL dnwell,npn,photo
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]808 calma 64 18
809
810 layer PWRES rpw
811 and dnwell
812 calma 64 13
813
814#----------------------------------------------------------------
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]815# SUBCUT
816#----------------------------------------------------------------
817
818 layer SUBCUT isosub
819 calma 81 53
820
821#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]822# NWELL
823#----------------------------------------------------------------
824
825 layer NWELL allnwell
826 bloat-all rpw dnwell
827 and-not rpw,pwell
828 calma 64 20
829
830 layer WELLTXT
831 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]832 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]833
834 layer WELLPIN
835 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]836 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]837
838#----------------------------------------------------------------
839# SUB (text/port only)
840#----------------------------------------------------------------
841
842 layer SUBTXT
843 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]844 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]845
846 layer SUBPIN
847 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]848 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]849
850#----------------------------------------------------------------
851# DIFF
852#----------------------------------------------------------------
853
854 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]855 calma 65 20
856
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]857 layer DIFFTXT
858 labels allnactivenontap,allpactivenontap noport
859 calma 65 6
860
861 layer DIFFPIN
862 labels allnactivenontap,allpactivenontap port
863 calma 65 16
864
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]865#----------------------------------------------------------------
866# TAP
867#----------------------------------------------------------------
868
869 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]870 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]871 calma 65 44
872
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]873 layer TAPTXT
874 labels allnactivetap,allpactivetap noport
875 calma 65 5
876
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]877#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]878# FOM
879#----------------------------------------------------------------
880
881 layer FOMFILL fomfill
882 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]883 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]884
885#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]886# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]887#----------------------------------------------------------------
888
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]889 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]890 grow 15
891 or xhrpoly,uhrpoly,xpc
892 grow 110
893 bloat-or allpactivetap * 125 allnactivenontap 0
894 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]895
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]896 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]897 grow 125
898 bloat-or allnactivetap * 125 allpactivenontap 0
899 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]900
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]901 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]902 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]903 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]904
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]905 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]906 grow 185
907 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]908 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]909 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]910 calma 94 20
911
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]912 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]913 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]914 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]915
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]916 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]917 grow 185
918 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]919 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]920 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]921 calma 93 44
922
923#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]924# LVID
925#----------------------------------------------------------------
926
927 layer LVID nnfet
928 grow 100
929 calma 81 60
930
931#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]932# LVTN
933#----------------------------------------------------------------
934
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]935 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]936 grow 180
937 bridge 380 380
938 grow 185
939 shrink 185
940 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]941 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]942 calma 125 44
943
944#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]945# HVTR
946#----------------------------------------------------------------
947
948 layer HVTR pfetmvt
949 grow 180
950 bridge 380 380
951 grow 185
952 shrink 185
953 close 265000
954 calma 18 20
955
956#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]957# HVTP
958#----------------------------------------------------------------
959
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]960 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]961 grow 180
962 bridge 380 380
963 grow 185
964 shrink 185
965 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]966 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]967 calma 78 44
968
969#----------------------------------------------------------------
970# SONOS
971#----------------------------------------------------------------
972
973 layer SONOS nsonos
974 grow 100
975 grow-min 410
976 bridge 500 410
977 grow 250
978 shrink 250
979 calma 80 20
980
981#----------------------------------------------------------------
Tim Edwards7791df22022-01-18 16:23:33 -0500[diff] [blame]982# The coreli layer indicates a cell needing COREID. Also,
983# devices npd, npass, and ppu indicate a COREID cell. NOTE:
984# SONOS does not use COREID, counter to SkyWater rules.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]985#----------------------------------------------------------------
986
987 layer COREID
Tim Edwards7791df22022-01-18 16:23:33 -0500[diff] [blame]988 bloat-all coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]989 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]990 calma 81 2
991
992#----------------------------------------------------------------
993# STDCELL applies to all cells containing scnfet or scpfet.
994#----------------------------------------------------------------
995
996 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]997 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]998 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]999 calma 81 4
1000
1001#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]1002# ESDID is a marker layer for ESD devices in the padframe I/O.
1003#----------------------------------------------------------------
1004
1005 layer ESDID
1006 bloat-all mvnfetesd *mvndiff,*poly
1007 bloat-all mvpfetesd *mvpdiff,*poly
1008 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1009 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]1010 calma 81 19
1011
1012#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1013# NPNID and PNPID apply to bipolar transistors
1014#----------------------------------------------------------------
1015
1016 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]1017 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1018 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1019 calma 82 20
1020
1021 templayer pnparea pnp
1022 grow 400
1023
1024 layer PNPID
1025 bloat-all pnparea *psd
1026 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1027 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1028 calma 82 44
1029
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]1030 layer PHOTO photo
1031 calma 81 81
1032
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1033#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1034# RPM
1035#----------------------------------------------------------------
1036
1037 layer RPM
1038 bloat-all xhrpoly xpc
1039 grow 200
1040 grow-min 1270
1041 grow 420
1042 shrink 420
1043 calma 86 20
1044
1045#----------------------------------------------------------------
1046# URPM (2kOhms/sq. poly implant)
1047#----------------------------------------------------------------
1048
1049 layer URPM
1050 bloat-all uhrpoly xpc
1051 grow 200
1052 grow-min 1270
1053 grow 420
1054 shrink 420
1055 calma 79 20
1056
1057#----------------------------------------------------------------
1058# LDNTM (Tip implant for SONOS FETs)
1059#----------------------------------------------------------------
1060
1061 layer LDNTM
1062 bloat-all nsonos *ndiff
1063 grow 185
1064 grow 345
1065 shrink 345
1066 calma 11 44
1067
1068#----------------------------------------------------------------
1069# HVNTM (Tip implant for MV ndiff devices)
1070#----------------------------------------------------------------
1071
1072 templayer hvntm_block *mvpsd
1073 grow 185
1074
1075 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1076 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1077 bloat-all mvvaractor *mvnsd
1078 and-not hvntm_block
1079 grow 185
1080 grow 345
1081 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1082 and-not hvntm_block
Tim Edwardsce38f722021-07-22 11:43:58 -0400[diff] [blame]1083 mask-hints HVNTM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1084 calma 125 20
1085
1086#----------------------------------------------------------------
1087# POLY
1088#----------------------------------------------------------------
1089
1090 layer POLY allpoly
1091 calma 66 20
1092
1093 layer POLYTXT
1094 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1095 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1096
1097 layer POLYPIN
1098 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1099 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1100
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1101 layer POLYFILL polyfill
1102 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1103 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1104
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1105#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1106# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1107#----------------------------------------------------------------
1108
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1109 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1110 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1111 bloat-all alldiffmv nwell
1112 grow 345
1113 shrink 345
1114
1115 templayer large_ptap_mv thkox_area
1116 shrink 420
1117 grow 420
1118
1119 templayer small_ptap_mv thkox_area
1120 and-not large_ptap_mv
1121 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1122 grow-min 840
1123
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1124 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1125 bridge 700 600
1126 grow 345
1127 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1128 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1129 calma 75 20
1130
1131#----------------------------------------------------------------
1132# CONT (LICON)
1133#----------------------------------------------------------------
1134
1135 layer CONT allcont
1136 squares-grid 0 170 170
1137 calma 66 44
1138
1139 # Contact for pres is different than other LICON contacts
1140 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1141 templayer xpc_horiz xpc
1142 shrink 1007
1143 grow 1007
1144
1145 layer CONT xpc
1146 and-not xpc_horiz
1147 # Force long edge vertical for contacts narrower than 2um
1148 # Minimum space is 350 but 520 satisfies no. of contacts rule
1149 slots 80 190 520 80 2000 350
1150 calma 66 44
1151
1152 layer CONT xpc
1153 and xpc_horiz
1154 # Force long edge vertical for contacts wider than 2um
1155 # Minimum space is 350 but 520 satisfies no. of contacts rule
1156 slots 80 2000 350 80 190 520
1157 calma 66 44
1158
1159#----------------------------------------------------------------
1160# NPC (Nitride poly cut)
1161# surrounds CONT (LICON) on poly only (i.e., pc)
1162#----------------------------------------------------------------
1163
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1164 # Avoids a common case of NPC bridges too close to other LICON shapes.
1165 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1166 grow 90
1167
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1168 layer NPC pc
1169 squares-grid 0 170 170
1170 grow 100
1171 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1172 and-not diffcutarea
1173 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1174 grow 130
1175 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1176 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1177 calma 95 20
1178
1179 # NPC is also generated on xhrpoly and uhrpoly resistors
1180
1181 layer NPC xpc,xhrpoly,uhrpoly
1182 # xpc surrounds precision_resistor by 0.095um
1183 grow 95
1184 grow 130
1185 shrink 130
1186 calma 95 20
1187
1188#----------------------------------------------------------------
1189# Device markers
1190#----------------------------------------------------------------
1191
1192 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1193 calma 65 13
1194
1195 layer POLYRES mrp1
1196 calma 66 13
1197
1198 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1199 layer POLYSHORT rmp
1200 calma 66 15
1201
1202 # POLYRES extends to edge of contact cut
1203 layer POLYRES xhrpoly,uhrpoly
1204 grow 60
1205 and xpc
1206 or xhrpoly,uhrpoly
1207 calma 66 13
1208
1209 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1210 # To be done: Expand to include anode, cathode, and guard ring
1211 calma 81 23
1212
1213#----------------------------------------------------------------
1214# LI
1215#----------------------------------------------------------------
1216 layer LI allli
1217 calma 67 20
1218
1219 layer LITXT
1220 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1221 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1222
1223 layer LIPIN
1224 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1225 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1226
1227 layer LIRES rli
1228 labels rli
1229 calma 67 13
1230
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1231 layer LIFILL lifill
1232 labels lifill
1233 calma 56 28
1234
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1235#----------------------------------------------------------------
1236# MCON
1237#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1238 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1239 squares-grid 0 170 190
1240 calma 67 44
1241
1242#----------------------------------------------------------------
1243# MET1
1244#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1245 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1246 calma 68 20
1247
1248 layer MET1TXT
1249 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1250 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1251
1252 layer MET1PIN
1253 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1254 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1255
1256 layer MET1RES rm1
1257 labels rm1
1258 calma 68 13
1259
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1260 layer MET1FILL m1fill
1261 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1262 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1263
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1264#----------------------------------------------------------------
1265# VIA1
1266#----------------------------------------------------------------
1267 layer VIA1 via1
1268 squares-grid 55 150 170
1269 calma 68 44
1270
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]1271#ifdef RERAM
1272#undef RERAM
1273 layer VIA1 reram
1274 squares-grid 55 150 170
1275 calma 68 44
1276
1277 layer RERAM reram
1278 squares-grid 55 230 230
1279 calma 201 20
1280#define RERAM
1281#endif (RERAM)
1282
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1283#----------------------------------------------------------------
1284# MET2
1285#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1286 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1287 calma 69 20
1288
1289 layer MET2TXT
1290 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1291 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1292
1293 layer MET2PIN
1294 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1295 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1296
1297 layer MET2RES rm2
1298 labels rm2
1299 calma 69 13
1300
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1301 layer MET2FILL m2fill
1302 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1303 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1304
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1305#----------------------------------------------------------------
1306# VIA2
1307#----------------------------------------------------------------
1308 layer VIA2 via2
1309 squares-grid 40 200 200
1310 calma 69 44
1311
1312#----------------------------------------------------------------
1313# MET3
1314#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1315 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1316 calma 70 20
1317
1318 layer MET3TXT
1319 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1320 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1321
1322 layer MET3PIN
1323 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1324 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1325
1326 layer MET3RES rm3
1327 labels rm3
1328 calma 70 13
1329
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1330 layer MET3FILL m3fill
1331 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1332 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1333
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1334#ifdef METAL5
1335#----------------------------------------------------------------
1336# VIA3
1337#----------------------------------------------------------------
1338 layer VIA3 via3
1339#ifdef MIM
1340 or mimcc
1341#endif (MIM)
1342 squares-grid 60 200 200
1343 calma 70 44
1344
1345#----------------------------------------------------------------
1346# MET4
1347#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1348 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1349 calma 71 20
1350
1351 layer MET4TXT
1352 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1353 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1354
1355 layer MET4PIN
1356 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1357 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1358
1359 layer MET4RES rm4
1360 labels rm4
1361 calma 71 13
1362
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1363 layer MET4FILL m4fill
1364 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1365 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1366
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1367#----------------------------------------------------------------
1368# VIA4
1369#----------------------------------------------------------------
1370 layer VIA4 via4
1371#ifdef MIM
1372 or mim2cc
1373#endif (MIM)
1374 squares-grid 190 800 800
1375 calma 71 44
1376
1377#----------------------------------------------------------------
1378# MET5
1379#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1380 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1381 calma 72 20
1382
1383 layer MET5TXT
1384 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1385 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1386
1387 layer MET5PIN
1388 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1389 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1390
1391 layer MET5RES rm5
1392 labels rm5
1393 calma 72 13
1394
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1395 layer MET5FILL m5fill
1396 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1397 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1398
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1399#endif (METAL5)
1400
1401#ifdef REDISTRIBUTION
1402#----------------------------------------------------------------
1403# RDL
1404#----------------------------------------------------------------
1405 layer RDL *metrdl
1406 calma 74 20
1407
1408 layer RDLTXT
1409 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1410 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1411
1412 layer RDLPIN
1413 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1414 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1415
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1416 layer PI1 *metrdl
1417 and padl,glass
1418 # Test only---needs GDS layer number
1419
1420 layer UBM *metrdl
1421 shrink 50000
1422 grow 40000
1423 # Test only---needs GDS layer number
1424
1425 layer PI2 *metrdl
1426 shrink 50000
1427 grow 25000
1428 # Test only---needs GDS layer number
1429
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1430#endif REDISTRIBUTION
1431
1432#----------------------------------------------------------------
1433# GLASS
1434#----------------------------------------------------------------
1435 layer GLASS glass
1436 calma 76 20
1437
1438#ifdef MIM
1439#----------------------------------------------------------------
1440# CAPM
1441#----------------------------------------------------------------
1442 layer CAPM *mimcap
1443 labels mimcap
1444 calma 89 44
1445
1446 layer CAPM2 *mimcap2
1447 labels mimcap2
1448 calma 97 44
1449#endif (MIM)
1450
1451#----------------------------------------------------------------
1452# Chip top level marker for DRC latchup rules to check 15um
1453# distance to taps (otherwise 6um is used)
1454#----------------------------------------------------------------
1455
1456 layer LOWTAPDENSITY
1457 bbox top
1458 # Clear 200um for pads + 50um for required high tap density
1459 # in critical area.
1460 shrink 250000
1461 calma 81 14
1462
1463#----------------------------------------------------------------
1464# FILLBLOCK
1465#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1466 layer FILLOBSFOM obsactive
1467 calma 22 24
1468
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1469 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1470 calma 62 24
1471
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1472 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1473 calma 105 52
1474
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1475 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1476 calma 107 24
1477
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1478 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1479 calma 112 4
1480
1481 render DNWELL cwell -0.1 0.1
1482 render NWELL nwell 0.0 0.2062
1483 render DIFF ndiffusion 0.2062 0.12
1484 render TAP pdiffusion 0.2062 0.12
1485 render POLY polysilicon 0.3262 0.18
1486 render CONT via 0.5062 0.43
1487 render LI metal1 0.9361 0.10
1488 render MCON via 1.0361 0.34
1489 render MET1 metal2 1.3761 0.36
1490 render VIA1 via 1.7361 0.27
1491 render MET2 metal3 2.0061 0.36
1492 render VIA2 via 2.3661 0.42
1493 render MET3 metal4 2.7861 0.845
1494#ifdef METAL5
1495 render VIA3 via 3.6311 0.39
1496 render MET4 metal5 4.0211 0.845
1497 render VIA4 via 4.8661 0.505
1498 render MET5 metal6 5.3711 1.26
1499 render CAPM metal8 2.4661 0.2
1500 render CAPM2 metal9 3.7311 0.2
1501#ifdef REDISTRIBUTION
1502 render RDL metal7 11.8834 4.0
1503#endif (!REDISTRIBUTION)
1504#endif (!METAL5)
1505
1506#----------------------------------------------------------------
1507style drc
1508#----------------------------------------------------------------
1509# NOTE: This style is used for DRC only, not for GDS output
1510#----------------------------------------------------------------
1511 scalefactor 10 nanometers
1512 options calma-permissive-labels
1513
1514 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1515 templayer dnwell_shrink dnwell
1516 shrink 1030
1517
1518 templayer nwell_missing dnwell
1519 grow 400
1520 and-not dnwell_shrink
1521 and-not nwell
1522
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1523 templayer pwell_in_dnwell dnwell
1524 and-not nwell
1525
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1526 # SONOS nFET devices must be in deep nwell
1527 templayer dnwell_missing nsonos
1528 and-not dnwell
1529
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1530 # SONOS nFET devices must be in cell with abutment box
1531 templayer abutment_box
1532 boundary
1533
1534 templayer bbox_missing nsonos
1535 and-not abutment_box
1536
1537 # Make sure nwell covers varactor poly
1538 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1539 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1540 grow 150
1541 and-not nwell
1542
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1543 # Define MiM cap bottom plate for spacing rule
1544 templayer mim_bottom
1545 bloat-all *mimcap *metal3
1546
1547 # Define MiM2 cap bottom plate for spacing rule
1548 templayer mim2_bottom
1549 bloat-all *mimcap2 *metal4
1550
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]1551 # Define areas where mim2cc is inside the boundary of mimcc
1552 # by more than the contact surround
1553 templayer mim2_contact_overlap
1554 bloat-all *mimcap2 mimcc
1555 shrink 60
1556 and-not *mimcap2
1557
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1558 # Note that metal fill is performed by the foundry and so is not
1559 # an option for a cifoutput style.
1560
1561 # Check latchup rule (15um minimum from tap LICON center to any
1562 # non-tap diffusion. Note that to count as a tap, the diffusion
1563 # must be contacted to LI
1564
1565 templayer ptap_reach psc,mvpsc
1566 and-not dnwell
1567 # grow total is 15um. grow in 0.84um increments to ensure that
1568 # no nwell ring is crossed
1569 grow 840
1570 and-not nwell,dnwell
1571 grow 840
1572 and-not nwell,dnwell
1573 grow 840
1574 and-not nwell,dnwell
1575 grow 840
1576 and-not nwell,dnwell
1577 grow 840
1578 and-not nwell,dnwell
1579 grow 840
1580 and-not nwell,dnwell
1581 grow 840
1582 and-not nwell,dnwell
1583 grow 840
1584 and-not nwell,dnwell
1585 grow 840
1586 and-not nwell,dnwell
1587 grow 840
1588 and-not nwell,dnwell
1589 grow 840
1590 and-not nwell,dnwell
1591 grow 840
1592 and-not nwell,dnwell
1593 grow 840
1594 and-not nwell,dnwell
1595 grow 840
1596 and-not nwell,dnwell
1597 grow 840
1598 and-not nwell,dnwell
1599 grow 840
1600 and-not nwell,dnwell
1601 grow 840
1602 and-not nwell,dnwell
1603 grow 635
1604 and-not nwell,dnwell
1605
1606 templayer ptap_missing *ndiff,*mvndiff
1607 and-not dnwell
1608 and-not ptap_reach
1609
1610 templayer ntap_reach nsc,mvnsc
1611 # grow total is 15um. grow in 1.27um increments to ensure that
1612 # no nwell ring is crossed. There is no difference between
1613 # ntaps in and out of deep nwell.
1614 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1615 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1616 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1617 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1618 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1619 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1620 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1621 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1622 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1623 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1624 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1625 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1626 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1627 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1628 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1629 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1630 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1631 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1632 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1633 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1634 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1635 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1636 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1637 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1638
1639 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1640 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1641 and-not ntap_reach
1642
1643 templayer dptap_reach psc,mvpsc
1644 and dnwell
1645 grow 840
1646 and-not nwell
1647 and dnwell
1648 grow 840
1649 and-not nwell
1650 and dnwell
1651 grow 840
1652 and-not nwell
1653 and dnwell
1654 grow 840
1655 and-not nwell
1656 and dnwell
1657 grow 840
1658 and-not nwell
1659 and dnwell
1660 grow 840
1661 and-not nwell
1662 and dnwell
1663 grow 840
1664 and-not nwell
1665 and dnwell
1666 grow 840
1667 and-not nwell
1668 and dnwell
1669 grow 840
1670 and-not nwell
1671 and dnwell
1672 grow 840
1673 and-not nwell
1674 and dnwell
1675 grow 840
1676 and-not nwell
1677 and dnwell
1678 grow 840
1679 and-not nwell
1680 and dnwell
1681 grow 840
1682 and-not nwell
1683 and dnwell
1684 grow 840
1685 and-not nwell
1686 and dnwell
1687 grow 840
1688 and-not nwell
1689 and dnwell
1690 grow 840
1691 and-not nwell
1692 and dnwell
1693 grow 840
1694 and-not nwell
1695 and dnwell
1696 grow 635
1697 and-not nwell
1698 and dnwell
1699
1700 templayer dptap_missing *ndiff,*mvndiff
1701 and dnwell
1702 and-not dptap_reach
1703
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1704 templayer pdiff_crosses_dnwell dnwell
1705 grow 20
1706 and-not dnwell
1707 and allpdifflv,allpdiffmv
1708
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1709 # MV nwell must be 2um from any other nwell
1710 templayer mvnwell
1711 bloat-all alldiffmv nwell
1712 grow-min 840
1713 bridge 700 600
1714
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1715 # Simple spacing checks to lvnwell must use CIF-DRC rule
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1716 # Note that HVI may *abut* lvnwell; this can only be handled
1717 # with mask-hints layers.
1718
1719 templayer drawn_hvi
1720 mask-hints HVI
1721
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1722 templayer allmvdiffnowell *mvndiff,*mvpsd
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1723 and-not drawn_hvi
1724
1725 templayer nwell_or_hvi nwell,drawn_hvi
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1726
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1727 templayer lvnwell nwell
1728 and-not mvnwell
1729
Tim Edwardsd2e57fc2022-01-10 10:31:23 -0500[diff] [blame]1730 # Check for low-voltage diffusion in high-voltage well
1731 templayer lvdiff_in_mvnwell *pdiff,*pdiode,pdiffres,*nsd
1732 or pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
1733 and mvnwell
1734
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1735 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1736 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1737
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1738 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1739 and-not nwell_with_tap
1740
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1741 templayer tap_with_licon
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1742 bloat-all allpactivetap psd,mvpsd
1743 bloat-all allnactivetap nsd,mvnsd
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1744
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1745 templayer tap_missing_licon allnactivetap,allpactivetap
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1746 and-not tap_with_licon
1747
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1748 # Make sure varactor nwell contains no P diffusion
1749 templayer pdiff_in_varactor_well
1750 bloat-all varactor,mvvaractor nwell
1751 and allpactive
1752
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1753 # HVNTM spacing requires recreating HVNTM
1754 templayer hvntm_block *mvpsd
1755 grow 185
1756
1757 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1758 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1759 bloat-all mvvaractor *mvnsd
1760 and-not hvntm_block
1761 grow 185
1762 grow 345
1763 shrink 345
1764 and-not hvntm_block
1765
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1766 # RPM spacing checks require recreating RPM
1767 templayer rpm_generate
1768 bloat-all xhrpoly,uhrpoly xpc
1769 grow 200
1770 grow-min 1270
1771 grow 420
1772 shrink 420
1773
1774 # Check distance RPM to NSDM
1775 templayer rpm_nsd_check rpm_generate
1776 grow 325
1777 and allndifflv,allndiffmv
1778
1779 # Check distance RPM to (unrelated) POLY
1780 templayer rpm_poly_check rpm_generate
1781 grow 200
1782 and-not xhrpoly,uhrpoly,xpc
1783 and allpoly
1784
1785 # Check distance RPM to HVNTM
1786 templayer rpm_hvntm_check rpm_generate
1787 grow 385
1788 and allndiffmvnontap
1789
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1790 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1791 close 140000
1792
1793 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1794 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1795
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1796 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1797 close 140000
1798
1799 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1800 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1801
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1802 templayer m1_huge allm1
1803 shrink 1500
1804 grow 1500
1805
1806 templayer m1_large_halo m1_huge
1807 grow 280
1808 and-not m1_huge
1809 and allm1
1810
1811 templayer m2_huge allm2
1812 shrink 1500
1813 grow 1500
1814
1815 templayer m2_large_halo m2_huge
1816 grow 280
1817 and-not m2_huge
1818 and allm2
1819
1820 templayer m3_huge allm3
1821 shrink 1500
1822 grow 1500
1823
1824 templayer m3_large_halo m3_huge
1825 grow 400
1826 and-not m3_huge
1827 and allm3
1828
1829 templayer m4_huge allm4
1830 shrink 1500
1831 grow 1500
1832
1833 templayer m4_large_halo m4_huge
1834 grow 400
1835 and-not m4_huge
1836 and allm4
1837
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1838#ifdef EXPERIMENTAL
1839#----------------------------------------------------------------
1840style paint
1841#----------------------------------------------------------------
1842# NOTE: This style is used for database manipulations only via
1843# the "cif paint" command.
1844#----------------------------------------------------------------
1845
1846 scalefactor 10 nanometers
1847
1848 templayer m1grow *m1
1849 grow 290
1850
1851 # layer listrap: Use the following set of commands to strap local
1852 # interconnect wires with metal1 (inside the cursor box) to satisfy
1853 # the maximum aspect ratio rule for local interconnect:
1854 #
1855 # tech unlock *
1856 # cif ostyle paint
1857 # cif paint m1strap comment
1858 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1859 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1860 # erase comment
1861
1862 templayer m1strap *li
1863 and-not m1grow
1864 grow 30
1865
1866 templayer listrap comment
1867 slots 30 170 170 60
1868
1869#endif (EXPERIMENTAL)
1870
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1871#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1872style density
1873#----------------------------------------------------------------
1874# Style used by scripts to check for fill density
1875#----------------------------------------------------------------
1876 scalefactor 10 nanometers
1877 options calma-permissive-labels
1878 gridlimit 5
1879
1880 templayer fom_all alldiff,fomfill
1881
1882 templayer poly_all allpoly,polyfill
1883
1884 templayer li_all allli,lifill
1885
1886 templayer m1_all allm1,m1fill
1887
1888 templayer m2_all allm2,m2fill
1889
1890 templayer m3_all allm3,m3fill
1891
1892 templayer m4_all allm4,m4fill
1893
1894 templayer m5_all allm5,m5fill
1895
1896#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1897style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1898#----------------------------------------------------------------
1899# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1900# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1901#----------------------------------------------------------------
1902 scalefactor 10 nanometers
1903 options calma-permissive-labels
1904 gridlimit 5
1905
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1906#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1907# Generate and retain a layer representing the bounding box.
1908#
1909# For variant ():
1910# The bounding box is the full extent of geometry on the top level
1911# cell.
1912#
1913# For variant (tiled):
1914# Use with a script that breaks layout into flattened tiles and runs
1915# fill individually on each. The tiles should be larger than the
1916# step size, and each should draw a layer "comment" the size of the
1917# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1918#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1919
1920 variants ()
1921 templayer topbox
1922 bbox top
1923
1924 variants (tiled)
1925 templayer topbox comment
1926 # Each tile imposes the full keepout distance rule of
1927 # 3um on all sides.
1928 shrink 1500
1929
1930 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1931
1932#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1933# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1934# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1935# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1936# Enclosure by nwell = Diff/Tap 8 = 0.18um
1937#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1938
1939 templayer mvnwell
1940 bloat-all alldiffmv nwell
1941
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1942 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1943 and-not mvnwell
1944
1945 templayer well_shrink mvnwell
1946 shrink 250
1947 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1948 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1949 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1950 grow 340
1951 and-not well_shrink
1952
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1953#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1954# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1955#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1956 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1957 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1958 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1959 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1960
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1961 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1962 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1963 grow 1000
1964
1965#---------------------------------------------------
1966# FOM and POLY fill
1967#---------------------------------------------------
1968 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1969 # slots 0 4080 1320 0 4080 1320 1360 0
1970 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1971 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1972 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1973 shrink 2035
1974 grow 2035
1975
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1976#---------------------------------------------------
1977
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1978 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1979 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1980 or obstruct_poly
1981 templayer polyfill_pass1 topbox
1982 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1983 and-not obstruct_poly_pass1
1984 and topbox
1985 shrink 355
1986 grow 355
1987
1988#---------------------------------------------------
1989
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1990 templayer obstruct_fom_pass2 fomfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1991 grow 1290
1992 or polyfill_pass1
1993 grow 300
1994 or obstruct_fom
1995 templayer fomfill_pass2 topbox
1996 slots 0 2500 1320 0 2500 1320 1360 0
1997 and-not obstruct_fom_pass2
1998 and topbox
1999 shrink 1245
2000 grow 1245
2001
2002#---------------------------------------------------
2003
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2004 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2005 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2006 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2007 grow 300
2008 or obstruct_poly
2009 templayer polyfill_coarse topbox
2010 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2011 and-not obstruct_poly_coarse
2012 and topbox
2013 shrink 355
2014 grow 355
2015
2016#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2017 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2018 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2019 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2020 grow 300
2021 or obstruct_poly
2022 templayer polyfill_medium topbox
2023 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2024 and-not obstruct_poly_medium
2025 and topbox
2026 shrink 265
2027 grow 265
2028
2029#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2030 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2031 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2032 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2033 grow 300
2034 or obstruct_poly
2035 templayer polyfill_fine topbox
2036 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2037 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2038 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2039 shrink 235
2040 grow 235
2041
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2042#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2043
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2044 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2045 grow 1290
2046 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
2047 grow 300
2048 or obstruct_fom
2049 templayer fomfill_coarse topbox
2050 slots 0 1500 1320 0 1500 1320 1360 0
2051 and-not obstruct_fom_coarse
2052 and topbox
2053 shrink 745
2054 grow 745
2055
2056#---------------------------------------------------
2057
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2058 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2059 grow 1290
2060 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
2061 grow 300
2062 or obstruct_fom
2063 templayer fomfill_fine topbox
2064 slots 0 500 400 0 500 400 160 0
2065 and-not obstruct_fom_fine
2066 and topbox
2067 shrink 245
2068 grow 245
2069
2070#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2071 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2072 or fomfill_pass2
2073 or fomfill_coarse
2074 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2075 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2076
2077 layer POLYFILL polyfill_pass1
2078 or polyfill_coarse
2079 or polyfill_medium
2080 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2081 calma 28 28
2082
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2083#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2084# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2085# Note requirement that LI fill may not overlap (non-fill)
2086# diff or poly.
2087#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2088
2089 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2090 grow 2800
2091 or alldiff,allpoly
2092 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2093 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]2094 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]2095 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2096 and-not obstruct_li_coarse
2097 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2098 shrink 1495
2099 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2100
2101 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2102 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2103 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2104 grow 300
2105 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2106 grow 200
2107 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2108 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2109 and-not obstruct_li_medium
2110 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2111 shrink 745
2112 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2113
2114 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2115 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2116 grow 300
2117 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2118 grow 200
2119 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2120 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2121 and-not obstruct_li_fine
2122 and topbox
2123 shrink 285
2124 grow 285
2125
2126 layer LIFILL lifill_coarse
2127 or lifill_medium
2128 or lifill_fine
2129 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2130
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2131#---------------------------------------------------
2132# MET1 fill
2133#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2134
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2135 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2136 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2137 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2138 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2139 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2140 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2141 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2142 shrink 995
2143 grow 995
2144
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2145 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2146 grow 2800
2147 or met1fill_coarse
2148 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2149 templayer met1fill_medium topbox
2150 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2151 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2152 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2153 shrink 495
2154 grow 495
2155
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2156 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2157 grow 300
2158 or met1fill_coarse,met1fill_medium
2159 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2160 templayer met1fill_fine topbox
2161 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2162 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2163 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2164 shrink 285
2165 grow 285
2166
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2167 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2168 grow 100
2169 or met1fill_coarse,met1fill_medium,met1fill_fine
2170 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2171 templayer met1fill_veryfine topbox
2172 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2173 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2174 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2175 shrink 145
2176 grow 145
2177
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2178 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2179 or met1fill_medium
2180 or met1fill_fine
2181 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2182 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2183
2184#---------------------------------------------------
2185# MET2 fill
2186#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2187 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2188 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2189 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2190 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2191 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2192 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2193 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2194 shrink 995
2195 grow 995
2196
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2197 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2198 grow 2800
2199 or met2fill_coarse
2200 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2201 templayer met2fill_medium topbox
2202 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2203 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2204 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2205 shrink 495
2206 grow 495
2207
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2208 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2209 grow 300
2210 or met2fill_coarse,met2fill_medium
2211 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2212 templayer met2fill_fine topbox
2213 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2214 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2215 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2216 shrink 285
2217 grow 285
2218
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2219 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2220 grow 100
2221 or met2fill_coarse,met2fill_medium,met2fill_fine
2222 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2223 templayer met2fill_veryfine topbox
2224 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2225 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2226 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2227 shrink 145
2228 grow 145
2229
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2230 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2231 or met2fill_medium
2232 or met2fill_fine
2233 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2234 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2235
2236#---------------------------------------------------
2237# MET3 fill
2238#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2239 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2240 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2241 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2242 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2243 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2244 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2245 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2246 shrink 995
2247 grow 995
2248
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2249 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2250 grow 2700
2251 or met3fill_coarse
2252 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2253 templayer met3fill_medium topbox
2254 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2255 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2256 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2257 shrink 495
2258 grow 495
2259
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2260 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2261 grow 200
2262 or met3fill_coarse,met3fill_medium
2263 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2264 templayer met3fill_fine topbox
2265 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2266 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2267 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2268 shrink 285
2269 grow 285
2270
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2271 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2272 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2273 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2274 or met3fill_coarse,met3fill_medium,met3fill_fine
2275 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2276 templayer met3fill_veryfine topbox
2277 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2278 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2279 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2280 shrink 195
2281 grow 195
2282
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2283 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2284 or met3fill_medium
2285 or met3fill_fine
2286 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2287 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2288
2289#ifdef METAL5
2290#---------------------------------------------------
2291# MET4 fill
2292#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2293 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2294 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2295 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2296 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2297 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2298 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2299 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2300 shrink 995
2301 grow 995
2302
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2303 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2304 grow 2700
2305 or met4fill_coarse
2306 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2307 templayer met4fill_medium topbox
2308 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2309 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2310 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2311 shrink 495
2312 grow 495
2313
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2314 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2315 grow 200
2316 or met4fill_coarse,met4fill_medium
2317 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2318 templayer met4fill_fine topbox
2319 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2320 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2321 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2322 shrink 285
2323 grow 285
2324
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2325 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2326 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2327 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2328 or met4fill_coarse,met4fill_medium,met4fill_fine
2329 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2330 templayer met4fill_veryfine topbox
2331 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2332 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2333 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2334 shrink 195
2335 grow 195
2336
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2337 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2338 or met4fill_medium
2339 or met4fill_fine
2340 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2341 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2342
2343#---------------------------------------------------
2344# MET5 fill
2345#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2346 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2347 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2348 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2349 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2350 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2351 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2352 shrink 2495
2353 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2354
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2355 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2356 grow 1400
2357 or met5fill_coarse
2358 grow 1600
2359 templayer met5fill_medium topbox
2360 slots 0 3000 1600 0 3000 1600 1000 100
2361 and-not obstruct_m5_medium
2362 and topbox
2363 shrink 1495
2364 grow 1495
2365
2366 layer MET5FILL met5fill_coarse
2367 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2368 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2369#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2370
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2371end
2372
2373#-----------------------------------------------------------------------
2374cifinput
2375#-----------------------------------------------------------------------
2376# NOTE: All values in this section MUST be multiples of 25
2377# or else magic will scale below the allowed layout grid size
2378#-----------------------------------------------------------------------
2379
Tim Edwardsd7d8a102021-07-21 10:56:23 -0400[diff] [blame]2380style sky130 variants (vendor),()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2381 scalefactor 10 nanometers
2382 gridlimit 5
2383
2384 options ignore-unknown-layer-labels no-reconnect-labels
2385
2386#ifndef MIM
2387 ignore CAPM
2388 ignore CAPM2
2389#endif (!MIM)
2390#ifndef METAL5
2391 ignore MET4,VIA3
2392 ignore MET5,VIA4
2393#endif
2394 ignore NPC
2395 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2396 ignore CAPID
2397 ignore LDNTM
2398 ignore HVNTM
2399 ignore POLYMOD
2400 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2401 ignore FILLOBSPOLY
Tim Edwards19435622021-12-31 14:11:01 -0500[diff] [blame]2402 ignore MET5BLOCK
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2403 ignore OUTLINE
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]2404 ignore POLYCUT
2405 ignore POLYGATE
2406 ignore DIFFCUT
2407 ignore HVNWELLID
2408 ignore PADDIFFID
2409 ignore PADMETALID
Tim Edwardsccf51c22021-12-31 14:18:06 -0500[diff] [blame]2410 ignore PADCENTERID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2411
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2412 layer pnp NWELL,WELLTXT,WELLPIN
2413 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2414 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2415 variants (vendor)
2416 labels WELLTXT port
2417 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2418 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2419 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2420 labels WELLPIN port
2421
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2422 layer nwell NWELL,WELLTXT,WELLPIN
2423 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2424 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2425 variants (vendor)
2426 labels WELLTXT port
2427 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2428 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2429 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2430 labels WELLPIN port
2431
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2432 templayer nwellarea NWELL
2433 copyup nwelcheck
2434
2435 # Copy nwell areas up for diffusion checks
2436 templayer xnwelcheck nwelcheck
2437 copyup nwelcheck
2438
2439 templayer hvarea HVI
2440 copyup hvcheck
2441
2442 # Copy high-voltage (HVI) areas up for diffusion checks
2443 templayer xhvcheck hvcheck
2444 copyup hvcheck
2445
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2446 # Always draw pwell under p-tap and n-diff. This is not always
2447 # necessary but works better with deep nwell for correct extraction.
2448 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2449 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2450 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2451 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2452 grow 420
2453 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2454 variants (vendor)
2455 labels SUBTXT port
2456 variants ()
2457 labels SUBTXT text
2458 variants *
2459 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2460
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2461 layer dnwell DNWELL
2462 labels DNWELL
2463
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]2464 layer isosub SUBCUT
2465 labels SUBCUT
2466
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2467 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2468 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2469 and NPNID
2470
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]2471 layer photo DNWELL
2472 and PHOTO
2473
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2474 layer rpw PWRES
2475 and DNWELL
2476 labels PWRES
2477
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2478 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2479 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2480 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2481 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2482 and-not DIODE
2483 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2484 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2485 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2486 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2487 copyup ndifcheck
2488 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2489 variants (vendor)
2490 labels DIFFTXT port
2491 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2492 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2493 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2494 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2495
2496 layer ndiff ndiffarea
2497
2498 # Copy ndiff areas up for contact checks
2499 templayer xndifcheck ndifcheck
2500 copyup ndifcheck
2501
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2502 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2503 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2504 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2505 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2506 and-not DIODE
2507 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2508 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2509 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2510 copyup ndifcheck
2511 labels DIFF
2512 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2513 variants (vendor)
2514 labels DIFFTXT port
2515 variants ()
2516 labels DIFFTXT text
2517 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2518 labels DIFFPIN port
2519
2520 layer mvndiff mvndiffarea
2521
2522 # Copy ndiff areas up for contact checks
2523 templayer mvxndifcheck mvndifcheck
2524 copyup mvndifcheck
2525
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2526 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2527 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2528 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2529 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2530 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2531 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2532 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2533 and-not LVTN
2534 labels DIFF
2535
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2536 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2537 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2538 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2539 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2540 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2541 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2542 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2543 and LVTN
2544 labels DIFF
2545
2546 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2547 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2548 and-not HVI,hvcheck
2549 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2550 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2551
2552 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2553 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2554 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2555 labels DIFF
2556
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2557 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2558 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2559 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2560 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2561 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2562 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2563 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2564 copyup pdifcheck
2565 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2566 variants (vendor)
2567 labels DIFFTXT port
2568 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2569 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2570 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2571 labels DIFFPIN port
2572
2573 layer pdiff pdiffarea
2574
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2575 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2576 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2577 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2578 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2579 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2580 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2581 and-not LVTN
2582 labels DIFF
2583
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2584 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2585 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2586 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2587 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2588 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2589 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2590 and LVTN
2591 labels DIFF
2592
2593 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2594 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2595 and HVI,hvcheck
2596 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2597 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2598
2599 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2600 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2601 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2602 labels DIFF
2603
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2604 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2605 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2606 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2607 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2608 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2609 and-not DIODE
2610 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2611 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2612 copyup mvpdifcheck
2613 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2614 variants (vendor)
2615 labels DIFFTXT port
2616 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2617 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2618 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2619 labels DIFFPIN port
2620
2621 layer mvpdiff mvpdiffarea
2622
2623 # Copy pdiff areas up for contact checks
2624 templayer xpdifcheck pdifcheck
2625 copyup pdifcheck
2626
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2627 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2628 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2629 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2630 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2631 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2632 and-not LVTN
2633 and-not HVTP
2634 and DIODE
2635 labels DIFF
2636
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2637 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2638 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2639 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2640 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2641 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2642 and LVTN
2643 and-not HVTP
2644 and DIODE
2645 labels DIFF
2646
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2647 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2648 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2649 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2650 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2651 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2652 and-not LVTN
2653 and HVTP
2654 and DIODE
2655 labels DIFF
2656
2657 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2658 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2659 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2660 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2661
2662 # Define pfet areas as known pdiff, regardless of the presence of a well.
2663
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2664 templayer pfetarea DIFF,barediff
2665 and POLY
2666 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2667 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2668 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2669
2670 layer pfet pfetarea
2671 and-not LVTN
2672 and-not HVTP
2673 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2674 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2675 labels DIFF
2676
2677 layer scpfet pfetarea
2678 and-not LVTN
2679 and-not HVTP
2680 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2681 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2682 labels DIFF
2683
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2684 layer scpfethvt pfetarea
2685 and-not LVTN
2686 and HVTP
2687 and STDCELL
2688 labels DIFF
2689
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2690 layer ppu pfetarea
2691 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2692 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2693 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2694 # Shrink-grow operation eliminates the smaller parasitie device
2695 # shrink 70
2696 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2697 labels DIFF
2698
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2699 layer pfetlvt pfetarea
2700 and LVTN
2701 labels DIFF
2702
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2703 layer pfetmvt pfetarea
2704 and HVTR
2705 labels DIFF
2706
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2707 layer pfethvt pfetarea
2708 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2709 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2710 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2711 labels DIFF
2712
2713 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2714 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2715 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2716 grow 180
2717
2718 # Copy mvpdiff areas up for contact checks
2719 templayer mvxpdifcheck mvpdifcheck
2720 copyup mvpdifcheck
2721
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2722 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2723 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2724 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2725 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2726 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2727 and DIODE
2728 labels DIFF
2729
2730 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2731 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2732 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2733 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2734
2735 # Define pfet areas as known pdiff,
2736 # regardless of the presence of a
2737 # well.
2738
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2739 templayer mvpfetarea DIFF,barediff
2740 and POLY
2741 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2742 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2743 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2744
2745 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2746 and-not ESDID
2747 labels DIFF
2748
2749 layer mvpfetesd mvpfetarea
2750 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2751 labels DIFF
2752
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2753 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2754 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2755 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2756 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2757 and-not DIODE
2758 and-not DIFFRES
2759 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2760 variants (vendor)
2761 labels DIFFTXT port
2762 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2763 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2764 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2765 labels DIFFPIN port
2766
2767 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2768 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2769 and NWELL,nwelcheck
2770 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2771 labels DIFF
2772
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2773 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2774 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2775 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2776 and-not PSDM
2777 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2778 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2779 and-not LVTN
2780 and-not SONOS
2781 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2782 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2783 labels DIFF
2784
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2785 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2786 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2787 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2788 and-not PSDM
2789 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2790 and-not NWELL,nwelcheck
2791 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2792 and-not LVTN
2793 and-not SONOS
2794 and STDCELL
2795 labels DIFF
2796
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2797 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2798 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2799 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2800 and-not PSDM
2801 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2802 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2803 and COREID
2804 labels DIFF
2805
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2806 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2807 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2808 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2809 and-not PSDM
2810 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2811 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2812 and COREID
2813 # Shrink-grow operation eliminates the smaller npass device
2814 shrink 70
2815 grow 70
2816 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2817
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2818 # Devices abutting tap under gate are officially npd, not npass
2819 layer npd TAP
2820 grow 100
2821 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2822 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2823 and-not PSDM
2824 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2825 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2826 and COREID
2827 labels DIFF
2828
2829 layer nfetlvt DIFF,barediff
2830 and POLY
2831 or baretrans
2832 and-not PSDM
2833 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2834 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2835 and LVTN
2836 and-not SONOS
2837 labels DIFF
2838
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2839 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2840 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2841 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2842 and-not PSDM
2843 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2844 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2845 and LVTN
2846 and SONOS
2847 labels DIFF
2848
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2849 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2850 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2851 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2852 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2853 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2854 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2855 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2856 copyup nsubcheck
2857
2858 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2859 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2860
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2861 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2862 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2863 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2864 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2865 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2866 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2867
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2868 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2869 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2870 and POLY
2871 and COREID
2872 labels TAP
2873
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2874 templayer nsdexpand nsdarea
2875 grow 500
2876
2877 # Copy nsub areas up for contact checks
2878 templayer xnsubcheck nsubcheck
2879 copyup nsubcheck
2880
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2881 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2882 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2883 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2884 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2885 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2886 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2887 and-not pfetexpand
2888 copyup psubcheck
2889
2890 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2891 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2892
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2893 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2894 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2895 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2896 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2897 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2898 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2899
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2900 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2901 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2902 and POLY
2903 and COREID
2904 labels TAP
2905
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2906 templayer psdexpand psdarea
2907 grow 500
2908
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2909 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2910 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2911 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2912 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2913 and mvpfetexpand
2914 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2915 variants (vendor)
2916 labels DIFFTXT port
2917 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2918 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2919 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2920 labels DIFFPIN port
2921
2922 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2923 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2924 and NWELL,nwelcheck
2925 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2926 and-not mvrdpioedge
2927 labels DIFF
2928
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2929 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2930 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2931 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2932 and-not PSDM
2933 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2934 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2935 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2936 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2937
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2938 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2939 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2940 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2941 and-not PSDM
2942 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2943 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2944 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2945 and-not mvnfetarea
2946
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2947 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2948 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2949 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2950 and-not PSDM
2951 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2952 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2953 and ESDID
2954 and-not mvnnfetarea
2955 labels DIFF
2956
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2957 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2958 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2959 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2960 and-not PSDM
2961 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2962 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2963 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2964 and-not mvnnfetarea
2965 labels DIFF
2966
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2967 layer nnfet mvnnfetarea
2968 and LVID
2969 labels DIFF
2970
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2971 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2972 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2973 labels DIFF
2974
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2975 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2976 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2977 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2978 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2979 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2980 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2981 copyup mvnsubcheck
2982
2983 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2984 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2985
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2986 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2987 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2988 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2989 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2990 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2991
2992 templayer mvnsdexpand mvnsdarea
2993 grow 500
2994
2995 # Copy nsub areas up for contact checks
2996 templayer mvxnsubcheck mvnsubcheck
2997 copyup mvnsubcheck
2998
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2999 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3000 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3001 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3002 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3003 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3004 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3005 and-not mvpfetexpand
3006 copyup mvpsubcheck
3007
3008 layer mvpsd mvpsdarea
3009 labels DIFF
3010
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3011 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3012 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3013 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3014 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3015 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3016
3017 templayer mvpsdexpand mvpsdarea
3018 grow 500
3019
3020 # Copy psub areas up for contact checks
3021 templayer xpsubcheck psubcheck
3022 copyup psubcheck
3023
3024 templayer mvxpsubcheck mvpsubcheck
3025 copyup mvpsubcheck
3026
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3027 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3028 and-not PSDM
3029 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3030 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3031 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3032 and-not pfetexpand
3033 and psdexpand
3034
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3035 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3036 and-not PSDM
3037 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3038 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3039 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3040 and nsdexpand
3041
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3042 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3043 and-not PSDM
3044 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3045 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3046 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3047 and-not mvpfetexpand
3048 and mvpsdexpand
3049
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3050 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3051 and-not PSDM
3052 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3053 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3054 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3055 and mvnsdexpand
3056
3057 templayer hresarea POLY
3058 and RPM
3059 grow 3000
3060
3061 templayer uresarea POLY
3062 and URPM
3063 grow 3000
3064
3065 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3066 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3067 grow 3000
3068
3069 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3070 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3071 grow 3000
3072
3073 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
3074
3075 layer pfet POLY
3076 and DIFF
3077 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3078 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3079 and-not STDCELL
3080
3081 layer scpfet POLY
3082 and DIFF
3083 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3084 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3085 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3086 and STDCELL
3087
3088 layer scpfethvt POLY
3089 and DIFF
3090 and diffresarea
3091 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3092 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3093 and STDCELL
3094
3095 templayer xpolyterm RPM,URPM
3096 and POLY
3097 and-not POLYRES
3098 # add back the 0.06um contact surround in the direction of the resistor
3099 grow 60
3100 and POLY
3101
3102 layer xpc xpolyterm
3103
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3104 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3105 and-not POLYRES
3106 and-not POLYSHORT
3107 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3108 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3109 and-not RPM
3110 and-not URPM
3111 copyup polycheck
3112
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3113 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3114 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3115 variants (vendor)
3116 labels POLYTXT port
3117 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3118 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3119 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3120 labels POLYPIN port
3121
3122 # Copy (non-resistor) poly areas up for contact checks
3123 templayer xpolycheck polycheck
3124 copyup polycheck
3125
3126 layer mrp1 POLY
3127 and POLYRES
3128 and-not RPM
3129 and-not URPM
3130 labels POLY
3131
3132 layer rmp POLY
3133 and POLYSHORT
3134 labels POLY
3135
3136 layer xhrpoly POLY
3137 and POLYRES
3138 and RPM
3139 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3140 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3141 and NPC
3142 and-not xpolyterm
3143 labels POLY
3144
3145 layer uhrpoly POLY
3146 and POLYRES
3147 and URPM
3148 and-not RPM
3149 and NPC
3150 and-not xpolyterm
3151 labels POLY
3152
3153 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3154 or barecont
3155 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3156 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3157 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3158 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3159 and-not NWELL,nwelcheck
3160 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3161
3162 layer ndc ndcbase
3163 grow 85
3164 shrink 85
3165 shrink 85
3166 grow 85
3167 or ndcbase
3168 labels CONT
3169
3170 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3171 or barecont
3172 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3173 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3174 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3175 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3176 and NWELL,nwelcheck
3177 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3178
3179 layer nsc nscbase
3180 grow 85
3181 shrink 85
3182 shrink 85
3183 grow 85
3184 or nscbase
3185 labels CONT
3186
3187 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3188 or barecont
3189 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3190 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3191 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3192 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3193 and NWELL,nwelcheck
3194 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3195
3196 layer pdc pdcbase
3197 grow 85
3198 shrink 85
3199 shrink 85
3200 grow 85
3201 or pdcbase
3202 labels CONT
3203
3204 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3205 or barecont
3206 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3207 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3208 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3209 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3210 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3211 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3212
3213 layer pdc pdcnowell
3214 grow 85
3215 shrink 85
3216 shrink 85
3217 grow 85
3218 or pdcnowell
3219 labels CONT
3220
3221 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3222 or barecont
3223 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3224 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3225 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3226 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3227 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3228 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3229 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3230
3231 layer psc pscbase
3232 grow 85
3233 shrink 85
3234 shrink 85
3235 grow 85
3236 or pscbase
3237 labels CONT
3238
3239 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3240 or barecont
3241 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3242 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3243 and POLY
3244 and-not DIFF
3245 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3246
3247 layer pc pcbase
3248 grow 85
3249 shrink 85
3250 shrink 85
3251 grow 85
3252 or pcbase
3253 labels CONT
3254
3255 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3256 or barecont
3257 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3258 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3259 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3260 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3261 and DIODE
3262 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3263 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3264 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3265 and-not LVTN
3266
3267 layer ndic ndicbase
3268 grow 85
3269 shrink 85
3270 shrink 85
3271 grow 85
3272 or ndicbase
3273 labels CONT
3274
3275 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3276 or barecont
3277 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3278 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3279 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3280 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3281 and DIODE
3282 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3283 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3284 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3285 and LVTN
3286
3287 layer ndilvtc ndilvtcbase
3288 grow 85
3289 shrink 85
3290 shrink 85
3291 grow 85
3292 or ndilvtcbase
3293 labels CONT
3294
3295 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3296 or barecont
3297 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3298 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3299 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3300 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3301 and DIODE
3302 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3303 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3304 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3305 and-not LVTN
3306 and-not HVTP
3307
3308 layer pdic pdicbase
3309 grow 85
3310 shrink 85
3311 shrink 85
3312 grow 85
3313 or pdicbase
3314 labels CONT
3315
3316 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3317 or barecont
3318 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3319 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3320 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3321 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3322 and DIODE
3323 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3324 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3325 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3326 and LVTN
3327 and-not HVTP
3328
3329 layer pdilvtc pdilvtcbase
3330 grow 85
3331 shrink 85
3332 shrink 85
3333 grow 85
3334 or pdilvtcbase
3335 labels CONT
3336
3337 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3338 or barecont
3339 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3340 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3341 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3342 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3343 and DIODE
3344 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3345 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3346 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3347 and-not LVTN
3348 and HVTP
3349
3350 layer pdihvtc pdihvtcbase
3351 grow 85
3352 shrink 85
3353 shrink 85
3354 grow 85
3355 or pdihvtcbase
3356 labels CONT
3357
3358 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3359 or barecont
3360 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3361 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3362 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3363 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3364 and-not NWELL,nwelcheck
3365 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3366
3367 layer mvndc mvndcbase
3368 grow 85
3369 shrink 85
3370 shrink 85
3371 grow 85
3372 or mvndcbase
3373 labels CONT
3374
3375 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3376 or barecont
3377 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3378 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3379 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3380 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3381 and NWELL,nwelcheck
3382 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3383
3384 layer mvnsc mvnscbase
3385 grow 85
3386 shrink 85
3387 shrink 85
3388 grow 85
3389 or mvnscbase
3390 labels CONT
3391
3392 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3393 or barecont
3394 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3395 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3396 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3397 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3398 and NWELL,nwelcheck
3399 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3400
3401 layer mvpdc mvpdcbase
3402 grow 85
3403 shrink 85
3404 shrink 85
3405 grow 85
3406 or mvpdcbase
3407 labels CONT
3408
3409 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3410 or barecont
3411 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3412 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3413 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3414 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3415 and mvpfetexpand
3416 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3417 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3418
3419 layer mvpdc mvpdcnowell
3420 grow 85
3421 shrink 85
3422 shrink 85
3423 grow 85
3424 or mvpdcnowell
3425 labels CONT
3426
3427 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3428 or barecont
3429 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3430 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3431 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3432 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3433 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3434 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3435 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3436
3437 layer mvpsc mvpscbase
3438 grow 85
3439 shrink 85
3440 shrink 85
3441 grow 85
3442 or mvpscbase
3443 labels CONT
3444
3445 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3446 or barecont
3447 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3448 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3449 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3450 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3451 and DIODE
3452 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3453 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3454 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3455 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3456
3457 layer mvndic mvndicbase
3458 grow 85
3459 shrink 85
3460 shrink 85
3461 grow 85
3462 or mvndicbase
3463 labels CONT
3464
3465 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3466 or barecont
3467 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3468 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3469 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3470 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3471 and DIODE
3472 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3473 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3474 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3475 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3476
3477 layer nndic nndicbase
3478 grow 85
3479 shrink 85
3480 shrink 85
3481 grow 85
3482 or nndicbase
3483 labels CONT
3484
3485 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3486 or barecont
3487 and LI
Tim Edwards0609b7f2022-01-20 12:32:09 -0500[diff] [blame]3488 or barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3489 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3490 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3491 and DIODE
3492 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3493 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3494 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3495
3496 layer mvpdic mvpdicbase
3497 grow 85
3498 shrink 85
3499 shrink 85
3500 grow 85
3501 or mvpdicbase
3502 labels CONT
3503
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3504 layer fomfill FOMFILL
3505 labels FOMFILL
3506
3507 layer polyfill POLYFILL
3508 labels POLYFILL
3509
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3510 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3511 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3512 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3513 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3514 variants (vendor)
3515 labels LITXT port
3516 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3517 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3518 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3519 labels LIPIN port
3520
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3521 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3522 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3523 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3524 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3525 variants (vendor)
3526 labels LITXT port
3527 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3528 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3529 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3530 labels LIPIN port
3531
3532 layer rli LI
3533 and LIRES,LISHORT
3534 labels LIRES,LISHORT
3535
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3536 layer lifill LIFILL
3537 labels LIFILL
3538
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3539 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3540 grow 95
3541 shrink 95
3542 shrink 85
3543 grow 85
3544 or MCON
3545 labels MCON
3546
3547 layer m1 MET1,MET1TXT,MET1PIN
3548 and-not MET1RES,MET1SHORT
3549 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3550 variants (vendor)
3551 labels MET1TXT port
3552 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3553 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3554 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3555 labels MET1PIN port
3556
3557 layer rm1 MET1
3558 and MET1RES,MET1SHORT
3559 labels MET1RES,MET1SHORT
3560
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3561 layer m1fill MET1FILL
3562 labels MET1FILL
3563
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3564#ifdef MIM
3565 layer mimcap MET3
3566 and CAPM
3567 labels CAPM
3568
3569 layer mimcc VIA3
3570 and CAPM
3571 grow 60
3572 grow 40
3573 shrink 40
3574 labels CAPM
3575
3576 layer mimcap2 MET4
3577 and CAPM2
3578 labels CAPM2
3579
3580 layer mim2cc VIA4
3581 and CAPM2
3582 grow 190
3583 grow 210
3584 shrink 210
3585 labels CAPM2
3586
3587#endif (MIM)
3588
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3589#ifdef RERAM
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3590#undef RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3591 layer reram RERAM
3592 and VIA1
3593 grow 55
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3594#define RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3595#endif (RERAM)
3596
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3597 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3598 and-not COREID
3599 grow 5
3600 or VIA1
3601 grow 50
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3602#ifdef RERAM
3603#undef RERAM
3604 and-not RERAM
3605#define RERAM
3606#endif (RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3607
3608 layer m2c m2cbase
3609 grow 30
3610 shrink 30
3611 shrink 130
3612 grow 130
3613 or m2cbase
3614
3615 layer m2 MET2,MET2TXT,MET2PIN
3616 and-not MET2RES,MET2SHORT
3617 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3618 variants (vendor)
3619 labels MET2TXT port
3620 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3621 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3622 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3623 labels MET2PIN port
3624
3625 layer rm2 MET2
3626 and MET2RES,MET2SHORT
3627 labels MET2RES,MET2SHORT
3628
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3629 layer m2fill MET2FILL
3630 labels MET2FILL
3631
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3632 templayer m3cbase VIA2
3633 grow 40
3634
3635 layer m3c m3cbase
3636 grow 60
3637 shrink 60
3638 shrink 140
3639 grow 140
3640 or m3cbase
3641
3642 layer m3 MET3,MET3TXT,MET3PIN
3643 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3644 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3645 variants (vendor)
3646 labels MET3TXT port
3647 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3648 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3649 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3650 labels MET3PIN port
3651
3652 layer rm3 MET3
3653 and MET3RES,MET3SHORT
3654 labels MET3RES,MET3SHORT
3655
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3656 layer m3fill MET3FILL
3657 labels MET3FILL
3658
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3659#ifdef (METAL5)
3660
3661 templayer via3base VIA3
3662#ifdef MIM
3663 and-not CAPM
3664#endif (MIM)
3665 grow 60
3666
3667 layer via3 via3base
3668 grow 40
3669 shrink 40
3670 shrink 160
3671 grow 160
3672 or via3base
3673
3674 layer m4 MET4,MET4TXT,MET4PIN
3675 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3676 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3677 variants (vendor)
3678 labels MET4TXT port
3679 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3680 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3681 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3682 labels MET4PIN port
3683
3684 layer rm4 MET4
3685 and MET4RES,MET4SHORT
3686 labels MET4RES,MET4SHORT
3687
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3688 layer m4fill MET4FILL
3689 labels MET4FILL
3690
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3691 layer m5 MET5,MET5TXT,MET5PIN
3692 and-not MET5RES,MET5SHORT
3693 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3694 variants (vendor)
3695 labels MET5TXT port
3696 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3697 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3698 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3699 labels MET5PIN port
3700
3701 layer rm5 MET5
3702 and MET5RES,MET5SHORT
3703 labels MET5RES,MET5SHORT
3704
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3705 layer m5fill MET5FILL
3706 labels MET5FILL
3707
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3708 templayer via4base VIA4
3709#ifdef MIM
3710 and-not CAPM2
3711#endif (MIM)
3712 grow 190
3713
3714 layer via4 via4base
3715 grow 210
3716 shrink 210
3717 shrink 590
3718 grow 590
3719 or via4base
3720#endif (METAL5)
3721
3722#ifdef REDISTRIBUTION
3723 layer metrdl RDL,RDLTXT,RDLPIN
3724 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3725 variants (vendor)
3726 labels RDLTXT port
3727 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3728 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3729 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3730 labels RDLPIN port
3731#endif
3732
3733 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3734 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3735 # the next layer up
3736
3737 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3738 and-not PSDM
3739 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3740 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3741 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3742
3743 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3744 and-not PSDM
3745 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3746 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3747 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3748 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3749
3750 # Handle contacts found by copyup
3751
3752 templayer ndiccopy CONT
3753 and LI
3754 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3755 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3756 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3757
3758 layer ndic ndiccopy
3759 grow 85
3760 shrink 85
3761 shrink 85
3762 grow 85
3763 or ndiccopy
3764 labels CONT
3765
3766 templayer mvndiccopy CONT
3767 and LI
3768 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3769 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3770 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3771
3772 layer mvndic mvndiccopy
3773 grow 85
3774 shrink 85
3775 shrink 85
3776 grow 85
3777 or mvndiccopy
3778 labels CONT
3779
3780 templayer pdiccopy CONT
3781 and LI
3782 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3783 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3784 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3785
3786 layer pdic pdiccopy
3787 grow 85
3788 shrink 85
3789 shrink 85
3790 grow 85
3791 or pdiccopy
3792 labels CONT
3793
3794 templayer mvpdiccopy CONT
3795 and LI
3796 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3797 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3798 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3799
3800 layer mvpdic mvpdiccopy
3801 grow 85
3802 shrink 85
3803 shrink 85
3804 grow 85
3805 or mvpdiccopy
3806 labels CONT
3807
3808 templayer ndccopy CONT
3809 and ndifcheck
3810
3811 layer ndc ndccopy
3812 grow 85
3813 shrink 85
3814 shrink 85
3815 grow 85
3816 or ndccopy
3817 labels CONT
3818
3819 templayer mvndccopy CONT
3820 and mvndifcheck
3821
3822 layer mvndc mvndccopy
3823 grow 85
3824 shrink 85
3825 shrink 85
3826 grow 85
3827 or mvndccopy
3828 labels CONT
3829
3830 templayer pdccopy CONT
3831 and pdifcheck
3832
3833 layer pdc pdccopy
3834 grow 85
3835 shrink 85
3836 shrink 85
3837 grow 85
3838 or pdccopy
3839 labels CONT
3840
3841 templayer mvpdccopy CONT
3842 and mvpdifcheck
3843
3844 layer mvpdc mvpdccopy
3845 grow 85
3846 shrink 85
3847 shrink 85
3848 grow 85
3849 or mvpdccopy
3850 labels CONT
3851
3852 templayer pccopy CONT
3853 and polycheck
3854
3855 layer pc pccopy
3856 grow 85
3857 shrink 85
3858 shrink 85
3859 grow 85
3860 or pccopy
3861 labels CONT
3862
3863 templayer nsccopy CONT
3864 and nsubcheck
3865
3866 layer nsc nsccopy
3867 grow 85
3868 shrink 85
3869 shrink 85
3870 grow 85
3871 or nsccopy
3872 labels CONT
3873
3874 templayer mvnsccopy CONT
3875 and mvnsubcheck
3876
3877 layer mvnsc mvnsccopy
3878 grow 85
3879 shrink 85
3880 shrink 85
3881 grow 85
3882 or mvnsccopy
3883 labels CONT
3884
3885 templayer psccopy CONT
3886 and psubcheck
3887
3888 layer psc psccopy
3889 grow 85
3890 shrink 85
3891 shrink 85
3892 grow 85
3893 or psccopy
3894 labels CONT
3895
3896 templayer mvpsccopy CONT
3897 and mvpsubcheck
3898
3899 layer mvpsc mvpsccopy
3900 grow 85
3901 shrink 85
3902 shrink 85
3903 grow 85
3904 or mvpsccopy
3905 labels CONT
3906
3907 # Find contacts not covered in
3908 # metal and pull them into the
3909 # next layer up
3910
Tim Edwards4cbe2582022-01-20 14:45:23 -0500[diff] [blame]3911 templayer barelicont CONT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3912 and LI
3913 and-not DIFF,TAP
3914 and-not POLY
3915 and-not DIODE
3916 and-not nsubcheck
3917 and-not psubcheck
3918 and-not mvnsubcheck
3919 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3920 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3921 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3922
3923 templayer barecont CONT
3924 and-not LI
3925 and-not nsubcheck
3926 and-not psubcheck
3927 and-not mvnsubcheck
3928 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3929 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3930 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3931
3932 layer glass GLASS,PADTXT,PADPIN
3933 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3934 variants (vendor)
3935 labels PADTXT port
3936 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3937 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3938 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3939 labels PADPIN port
3940
3941 templayer boundary BOUND,STDCELL,PADCELL
3942 boundary
3943
3944 layer comment LVSTEXT
3945 labels LVSTEXT text
3946
3947 layer comment TTEXT
3948 labels TTEXT text
3949
3950 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3951 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3952
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3953 layer obsactive FILLOBSFOM
3954
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3955# MOS Varactor
3956
3957 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3958 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3959 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3960 and NWELL,nwelcheck
3961 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3962 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3963 # NOTE: Else forms a varactor that is not in the vendor netlist.
3964 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3965 labels POLY
3966
3967 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3968 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3969 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3970 and NWELL,nwelcheck
3971 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3972 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3973 labels POLY
3974
3975 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3976 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3977 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3978 and NWELL,nwelcheck
3979 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3980 labels POLY
3981
3982 calma NWELL 64 20
3983 calma DIFF 65 20
3984 calma DNWELL 64 18
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]3985 calma SUBCUT 81 53
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3986 calma PWRES 64 13
3987 calma TAP 65 44
3988 # LVTN
3989 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3990 # HVTR
3991 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3992 # HVTP
3993 calma HVTP 78 44
3994 # SONOS (TUNM)
3995 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3996 # NSDM (NPLUS)
3997 calma NSDM 93 44
3998 # PSDM (PPLUS)
3999 calma PSDM 94 20
4000 # HVI (THKOX)
4001 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4002 # NPC
4003 calma NPC 95 20
4004 # P+ POLY MASK
4005 calma RPM 86 20
4006 calma URPM 79 20
4007 calma LDNTM 11 44
4008 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]4009 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4010 calma POLYRES 66 13
4011 # Diffusion resistor ID mark
4012 calma DIFFRES 65 13
4013 calma POLY 66 20
4014 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4015 # 3.3V native FET ID mark
4016 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4017 # Diode ID mark
4018 calma DIODE 81 23
4019 # Bipolar NPN mark
4020 calma NPNID 82 20
4021 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4022 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4023 # Capacitor ID
4024 calma CAPID 82 64
4025 # Core area ID mark
4026 calma COREID 81 2
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]4027 # Photodiode ID mark
4028 calma PHOTO 81 81
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4029 # Standard cell ID mark
4030 calma STDCELL 81 4
4031 # Padframe cell ID mark
4032 calma PADCELL 81 3
4033 # Seal ring ID mark
4034 calma SEALID 81 1
4035 # Low tap density ID mark
4036 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4037 # ESD area ID
4038 calma ESDID 81 19
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]4039 # Various unused layers
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]4040 calma OUTLINE 236 0
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]4041 calma POLYCUT 66 14
4042 calma POLYGATE 66 9
4043 calma DIFFCUT 65 14
4044 calma HVNWELLID 81 63
4045 calma MET5BLOCK 72 10
4046 calma PADDIFFID 81 6
4047 calma PADMETALID 81 8
Tim Edwardsccf51c22021-12-31 14:18:06 -0500[diff] [blame]4048 calma PADCENTERID 81 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4049
4050 # LICON
4051 calma CONT 66 44
4052 calma LI 67 20
4053 calma MCON 67 44
4054
4055 calma MET1 68 20
4056 calma VIA1 68 44
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4057#ifdef RERAM
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]4058#undef RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4059 calma RERAM 201 20
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]4060#define RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4061#endif (RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4062 calma MET2 69 20
4063 calma VIA2 69 44
4064 calma MET3 70 20
4065#ifdef METAL5
4066 calma VIA3 70 44
4067 calma MET4 71 20
4068 calma VIA4 71 44
4069 calma MET5 72 20
4070#endif
4071#ifdef REDISTRIBUTION
4072 calma RDL 74 20
4073#endif
4074 calma GLASS 76 20
4075
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4076 calma SUBTXT 64 59
4077 calma PADTXT 76 5
4078 calma DIFFTXT 65 6
4079 calma TAPTXT 65 5
4080 calma WELLTXT 64 5
4081 calma LITXT 67 5
4082 calma POLYTXT 66 5
4083 calma MET1TXT 68 5
4084 calma MET2TXT 69 5
4085 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4086#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4087 calma MET4TXT 71 5
4088 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4089#endif
4090#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4091 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4092#endif
4093
4094 calma LIRES 67 13
4095 calma MET1RES 68 13
4096 calma MET2RES 69 13
4097 calma MET3RES 70 13
4098#ifdef METAL5
4099 calma MET4RES 71 13
4100 calma MET5RES 72 13
4101#endif
4102
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4103 calma LIFILL 56 28
4104 calma MET1FILL 36 28
4105 calma MET2FILL 41 28
4106 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4107#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4108 calma MET4FILL 51 28
4109 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4110#endif
4111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4112 calma POLYSHORT 66 15
4113 calma LISHORT 67 15
4114 calma MET1SHORT 68 15
4115 calma MET2SHORT 69 15
4116 calma MET3SHORT 70 15
4117#ifdef METAL5
4118 calma MET4SHORT 71 15
4119 calma MET5SHORT 72 15
4120#endif
4121
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4122 calma SUBPIN 122 16
4123 calma PADPIN 76 16
4124 calma DIFFPIN 65 16
4125 calma POLYPIN 66 16
4126 calma WELLPIN 64 16
4127 calma LIPIN 67 16
4128 calma MET1PIN 68 16
4129 calma MET2PIN 69 16
4130 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4131#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4132 calma MET4PIN 71 16
4133 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4134#endif
4135#ifdef REDISTRIBUTION
4136 calma RDLPIN 74 16
4137#endif
4138
4139 calma BOUND 235 4
4140
4141 calma LVSTEXT 83 44
4142
4143#ifdef (MIM)
4144 calma CAPM 89 44
4145 calma CAPM2 97 44
4146#endif (MIM)
4147
4148 calma FILLOBSM1 62 24
4149 calma FILLOBSM2 105 52
4150 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]4151 calma FILLOBSM4 112 4
4152 calma FILLOBSFOM 22 24
4153 calma FILLOBSPOLY 33 24
4154
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4155 calma FOMFILL 23 28
4156 calma POLYFILL 28 28
4157 calma LIFILL 56 28
4158 calma MET1FILL 36 28
4159 calma MET2FILL 41 28
4160 calma MET3FILL 34 28
4161 calma MET4FILL 51 28
4162 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4163
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4164#-----------------------------------------------------------------------
4165
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4166style rdlimport
4167 # This style is for reading shapes generated with the RDL layers
4168
4169 scalefactor 10 nanometers
4170 gridlimit 5
4171
4172 options ignore-unknown-layer-labels no-reconnect-labels
4173
4174 layer mrdl RDL
4175 layer mrdlc RDLC
4176
4177 calma RDL 10 0
4178 calma RDLC 20 0
4179
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4180end
4181
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4182#-----------------------------------------------------
4183# Digital flow maze router cost parameters
4184#-----------------------------------------------------
4185
4186mzrouter
4187end
4188
4189#-----------------------------------------------------
4190# Vendor DRC rules
4191#-----------------------------------------------------
4192
4193drc
4194
4195 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4196 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4197 cifstyle drc
4198
4199 variants (fast),(full)
4200
4201#-----------------------------
4202# DNWELL
4203#-----------------------------
4204
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4205 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4206 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4207 spacing allnwell dnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4208 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4209
4210 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4211 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4212 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4213 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4214 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4215
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4216 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4217 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4218 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4219
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]4220 width photo 3000 "Photodiode width < %d (photo.2)"
4221 spacing photo photo 5000 touching_ok "Photodiode spacing < %d (photo.3)"
4222 spacing photo dnwell 5300 touching_illegal \
4223 "Photodiode spacing to deep nwell < %d (photo.4)"
4224
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4225#-----------------------------
4226# NWELL
4227#-----------------------------
4228
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4229 width allnwell 840 "N-well width < %d (nwell.1)"
4230 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4231
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4232 variants (full)
4233 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4234 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4235
4236 cifspacing mvnwell lvnwell 2000 touching_illegal \
4237 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4238 cifspacing mvnwell mvnwell 2000 touching_ok \
4239 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardsd2e57fc2022-01-10 10:31:23 -0500[diff] [blame]4240
4241 cifmaxwidth lvdiff_in_mvnwell 0 bend_illegal \
4242 "All HV nwell can contain only HV diffusion (diff/tap.21)"
4243
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4244 variants (fast),(full)
4245
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4246#-----------------------------
4247# DIFF
4248#-----------------------------
4249
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4250 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4251 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4252 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4253 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4254
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4255 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4256 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4257 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4258 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4259 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4260 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4261 spacing alldifflv,var,varhvt,corenvar,corepvar,fomfill \
4262 alldifflv,var,varhvt,corenvar,corepvar,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4263 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwardsada35632021-08-19 21:00:32 -0400[diff] [blame]4264 spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \
4265 "LV to MV Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4266 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4267 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4268 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4269 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4270 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4271 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4272 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4273 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4274 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4275 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4276 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4277 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4278 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4279 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4280 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4281 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4282 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4283 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4284 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4285 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4286 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4287 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4288 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4289 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4290 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4291 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4292 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4293 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4294
4295variants (full)
4296 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4297 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]4298 cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
4299 "HVI to HVI or LV nwell spacing < %d (hvi.5)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4300variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4301
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4302 spacing allnfets allpactivenonfet 270 touching_illegal \
4303 "nFET cannot abut P-diffusion (diff/tap.3)"
4304 spacing allpfets allnactivenonfet 270 touching_illegal \
4305 "pFET cannot abut N-diffusion (diff/tap.3)"
4306
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4307 # Butting junction rules
4308 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4309 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4310 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4311 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4312 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4313 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4314 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4315 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4316
4317 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4318 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4319 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4320 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4321 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4322 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4323 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4324 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4325
4326 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4327 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4328 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4329
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4330 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4331 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4332
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4333 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4334
4335 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4336 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4337
4338 # Latchup rules
4339 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4340 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4341 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4342 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4343 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4344 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4345
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4346 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4347
4348#-----------------------------
4349# POLY
4350#-----------------------------
4351
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4352 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4353 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4354
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4355 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4356 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4357 75 corner_ok allfets \
4358 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4359 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4360 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards434a0852021-11-17 16:36:15 -0500[diff] [blame]4361 overhang *ndiff,rndiff nfet,scnfet,npd,npass,nsonos 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4362 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4363 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4364 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4365 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4366 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4367 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4368 rect_only allfets "No bends in transistors (poly.11)"
4369 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4370 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4371 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4372 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4373 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4374
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4375 variants (fast)
4376
4377 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4378 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4379 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4380 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4381 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4382 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4383
4384 # Minimum width requirement means actual spacing from res to ndiff has to be
4385 # constructed from mask rules. These supercede the simpler checks.
4386
4387 variants (full)
4388
4389 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4390 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4391 cifmaxwidth rpm_poly_check 0 bend_illegal \
4392 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4393 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4394 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4395
Tim Edwards75dea452021-05-08 15:55:26 -0400[diff] [blame]4396 variants (fast),(full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4397
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4398 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4399
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4400#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4401# HVTP
4402#--------------------------------------------------------------------
4403
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4404 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4405 360 touching_illegal \
4406 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4407
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4408 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4409 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4410
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4411#--------------------------------------------------------------------
4412# LVTN
4413#--------------------------------------------------------------------
4414
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4415 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4416 allfetsnolvt 360 touching_illegal \
4417 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4418
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4419 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4420 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4421 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4422
4423 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4424 edge4way allfetsnolvt allactivenonfet 415 \
4425 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4426 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4427
4428#--------------------------------------------------------------------
4429# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4430#--------------------------------------------------------------------
4431
4432# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4433
4434#--------------------------------------------------------------------
4435# CONT (LICON, contact between poly/diff and LI)
4436#--------------------------------------------------------------------
4437
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4438 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4439 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4440 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4441 width psc/li 170 "P-tap contact width < %d (licon.1)"
4442 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4443 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4444 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4445
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4446 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4447 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4448 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4449
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4450 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4451 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4452 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4453 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4454 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4455 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4456
4457 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4458 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4459 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4460 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4461 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4462 "Diffusion contact spacing < %d (licon.2)"
4463 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4464
4465 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4466 "poly contact spacing to diffusion < %d (licon.14)"
4467 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4468 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4469
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4470 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4471 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4472 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4473 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4474 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4475 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards7261d722021-11-17 16:44:27 -0500[diff] [blame]4476 spacing ndc,pdc nsonos 75 touching_illegal \
4477 "Diffusion contact to SONOS gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4478 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4479 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4480 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4481 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4482 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4483 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4484
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4485 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4486 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4487 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4488 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4489 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4490 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4491 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4492 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4493 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4494
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4495 spacing psc/a allnactivenontap 60 touching_illegal \
4496 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4497 spacing nsc/a allpactivenontap 60 touching_illegal \
4498 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4499
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4500 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4501 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4502 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4503 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4504 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4505 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4506 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4507 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4508 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4509
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4510 surround nsc/a *nsd,corenvar 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4511 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4512 surround psc/a *psd,corepvar 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4513 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4514
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4515 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4516 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4517 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4518 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4519 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4520 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4521 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4522 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4523
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4524 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4525 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4526 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4527 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4528
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4529 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4530 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4531 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4532 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4533 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4534 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4535 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4536 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4537
4538 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4539 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4540 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4541 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4542
4543 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4544 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4545 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4546 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4547
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4548 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4549
4550#-------------------------------------------------------------
4551# LI - Local interconnect layer
4552#-------------------------------------------------------------
4553
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4554variants *
4555
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4556 width *li 170 "Local interconnect width < %d (li.1)"
4557 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4558
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4559 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4560 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4561
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4562 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4563 # no special layers for the contacts in core cells, so they must be included
4564 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4565 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4566 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4567
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4568 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4569 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4570
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4571 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4572 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4573
4574 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4575 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4576 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4577
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4578 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4579
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4580 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4581 angles coreli 45 \
4582 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4583
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4584#-------------------------------------------------------------
4585# MCON - Contact between local interconnect and metal1
4586#-------------------------------------------------------------
4587
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4588 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4589 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4590
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4591 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4592
4593#-------------------------------------------------------------
4594# METAL1 -
4595#-------------------------------------------------------------
4596
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4597 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4598 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4599 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4600
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4601 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4602 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4603 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4604 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4605
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4606 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4607
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4608variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4609 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4610 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4611 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4612 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4613
4614variants (full)
4615 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4616 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4617
4618 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4619 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4620variants *
4621
4622#--------------------------------------------------
4623# VIA1
4624#--------------------------------------------------
4625
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4626 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4627 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4628 surround v1/m1 *m1,rm1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4629 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4630 surround v1/m2 *m2,rm2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4631 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4632
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4633 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4634
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4635#ifdef RERAM
4636#--------------------------------------------------
4637# ReRAM
4638#--------------------------------------------------
4639
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]4640 width reram 260 "ReRAM width < %d (rr1.1)"
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4641 spacing reram reram 55 touching_illegal "ReRAM spacing < %d (rr1.2)"
4642 surround reram *m1,rm1 30 directional \
4643 "Metal1 overlap of ReRAM < %d in one direction (via.5a - via.4a)"
4644 surround reram *m2,rm2 30 directional \
4645 "Metal2 overlap of ReRAM < %d in one direction (met2.5 - met2.4)"
4646
Tim Edwards27ecf1c2022-01-05 13:54:30 -0500[diff] [blame]4647 no_overlap reram v1
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4648
4649#endif (RERAM)
4650
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4651#--------------------------------------------------
4652# METAL2 -
4653#--------------------------------------------------
4654
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4655 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4656 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4657 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4658
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4659 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4660
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4661variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4662 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4663 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4664 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4665 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4666
4667variants (full)
4668 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4669 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4670
4671 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4672 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4673variants *
4674
4675#--------------------------------------------------
4676# VIA2
4677#--------------------------------------------------
4678
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4679 width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4680
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4681 spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4682
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4683 surround v2/m2 *m2,rm2 45 directional \
4684 "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
4685 surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4686
4687 exact_overlap v2/m2
4688
4689#--------------------------------------------------
4690# METAL3 -
4691#--------------------------------------------------
4692
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4693 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4694 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4695 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4696
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4697 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4698
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4699variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4700 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4701 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4702 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4703 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4704variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4705 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4706 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4707variants *
4708
4709
4710#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4711#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4712#--------------------------------------------------
4713# VIA3 - Requires METAL5 Module
4714#--------------------------------------------------
4715
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4716 width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
4717 spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
4718 surround v3/m3 *m3,rm3 30 directional \
4719 "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
4720 surround v3/m4 *m4,rm4 5 absence_illegal \
4721 "Metal4 overlap of via3 < %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4722
4723 exact_overlap v3/m3
4724
4725#-----------------------------
4726# METAL4 - METAL4 Module
4727#-----------------------------
4728
4729variants *
4730
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4731 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4732 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4733 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4734
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4735 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4736
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4737variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4738 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4739 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4740 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4741 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4742variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4743 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4744 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4745variants *
4746
4747#--------------------------------------------------
4748# VIA4 - Requires METAL5 Module
4749#--------------------------------------------------
4750
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4751 width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
4752 spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
4753 surround v4/m5 *m5,rm5 120 absence_illegal \
4754 "Metal5 overlap of via4 < %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4755
4756 exact_overlap v4/m4
4757
4758#-----------------------------
4759# METAL5 - METAL5 Module
4760#-----------------------------
4761
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4762 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4763 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4764 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4765
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4766 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4767
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4768#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4769#endif (METAL5)
4770
4771#ifdef REDISTRIBUTION
4772
4773variants (full)
4774
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4775 width metrdl 10000 "RDL width < %d (rdl.1)"
4776 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4777 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4778 spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4779
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4780variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4781
4782#endif (REDISTRIBUTION)
4783
4784#--------------------------------------------------
4785# NMOS, PMOS
4786#--------------------------------------------------
4787
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4788 edge4way *poly allfetsstd 420 allfets 0 0 \
4789 "Transistor width < %d (diff/tap.2)"
4790 edge4way *poly allfetsspecial 360 allfets 0 0 \
4791 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4792 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4793 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4794 edge4way *poly ppu 140 allfets 0 0 \
4795 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4796
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4797 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4798 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4799
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4800 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4801 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4802 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4803 "poly spacing to diffusion tap < %d (poly.5)"
4804 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4805 "poly spacing to diffusion tap < %d (poly.5)"
4806 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4807 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4808
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4809 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4810 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4811 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4812 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4813 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4814 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4815 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4816 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4817
4818 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4819 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4820 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4821
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4822 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4823 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824
4825 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4826 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4827 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4828
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4829 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4830 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4831
4832 # Minimum length of MV FETs. Note that this is larger than the minimum
4833 # width (0.29um), so an edge rule is required
4834
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4835 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4836 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4837
4838 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4839 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4840
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4841 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4842 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4843
4844#--------------------------------------------------
4845# mrp1 (N+ poly resistor)
4846#--------------------------------------------------
4847
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4848 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4849
4850#--------------------------------------------------
4851# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4852# uhrpoly (P+ poly resistor, 2kOhm/sq)
4853#--------------------------------------------------
4854
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4855 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4856 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4857 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4858
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4859 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4860 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4861
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4862 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4863 "Poly resistor spacing to poly < %d (poly.9)"
4864
4865 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4866 "Poly resistor spacing to poly < %d (poly.9)"
4867
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4868 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4869 "Poly resistor spacing to poly < %d (poly.9)"
4870
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4871 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4872 "Poly resistor spacing to diffusion < %d (poly.9)"
4873
4874#------------------------------------
4875# nsonos
4876#------------------------------------
4877
4878variants (full)
4879 cifmaxwidth bbox_missing 0 bend_illegal \
4880 "SONOS transistor must be in cell with abutment box (tunm.8)"
4881variants (fast),(full)
4882
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4883#------------------------------------
4884# MOS Varactor device rules
4885#------------------------------------
4886
4887 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4888 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4889
4890 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4891 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4892
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4893 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4894 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4895
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4896variants (full)
4897 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4898 "N-well overlap of varactor poly < 0.15um (varac.5)"
4899
4900 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4901 "Varactor N-well must not contain P+ diffusion (varac.7)"
4902variants (fast),(full)
4903
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4904#ifdef MIM
4905#-----------------------------------------------------------
4906# MiM CAP (CAPM) -
4907#-----------------------------------------------------------
4908
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4909 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4910 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4911 spacing *mimcap via3/m3 80 touching_illegal \
4912 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4913 surround *mimcc *mimcap 80 absence_illegal \
4914 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4915 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4916
4917 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4918 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4919 spacing via2 *mimcap 100 touching_illegal \
4920 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4921 spacing *mimcap *metal3/m3 500 surround_ok \
4922 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4923
4924variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4925 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4926 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4927variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4928
4929 # MiM cap contact rules (VIA3)
4930
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4931 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4932 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4933 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4934 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4935 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4936
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4937 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4938 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4939 spacing *mimcap2 via4/m4 10 touching_illegal \
4940 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4941 surround *mim2cc *mimcap2 10 absence_illegal \
4942 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4943 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4944
4945 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4946 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4947 spacing via3 *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4948 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4949 spacing *mimcap2 *metal4/m4 500 surround_ok \
4950 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4951
4952variants (full)
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4953 cifmaxwidth mim2_contact_overlap 0 bend_illegal \
4954 "MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
4955
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4956 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4957 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4958variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4959
4960 # MiM cap contact rules (VIA4)
4961
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4962 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4963 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4964 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4965 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4966 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4967 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4968
4969#endif (MIM)
4970
4971#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4972# HVNTM
4973#----------------------------
4974variants (full)
4975 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4976 "HVNTM spacing < %d (hvntm.2)"
4977variants (fast),(full)
4978
4979#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4980# End DRC style
4981#----------------------------
4982
4983end
4984
4985#----------------------------
4986# LEF format definitions
4987#----------------------------
4988
4989lef
4990
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4991 masterslice pwell pwell PWELL substrate
4992 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4993
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4994 routing li li1 LI1 LI li
4995
4996 routing m1 met1 MET1 m1
4997 routing m2 met2 MET2 m2
4998 routing m3 met3 MET3 m3
4999#ifdef METAL5
5000 routing m4 met4 MET4 m4
5001 routing m5 met5 MET5 m5
5002#endif (METAL5)
5003#ifdef REDISTRIBUTION
5004 routing mrdl met6 MET6 m6 MRDL METRDL
5005#endif
5006
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5007 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5008 cut m2c via via1 VIA VIA1 cont2 via12
5009 cut m3c via2 VIA2 cont3 via23
5010#ifdef METAL5
5011 cut via3 via3 VIA3 cont4 via34
5012 cut via4 via4 VIA4 cont5 via45
5013#endif (METAL5)
5014
5015 obs obsli li1
5016 obs obsm1 met1
5017 obs obsm2 met2
5018 obs obsm3 met3
5019
5020#ifdef METAL5
5021 obs obsm4 met4
5022 obs obsm5 met5
5023#endif (METAL5)
5024#ifdef REDISTRIBUTION
5025 obs obsmrdl met6
5026#endif
5027
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5028 # NOTE: obsmcon only used with li1, not obsli.
5029 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5030
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]5031 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
5032 obs obsm1 via
5033 obs obsm2 via2
5034#ifdef METAL5
5035 obs obsm3 via3
5036 obs obsm4 via4
5037#endif (METAL5)
5038
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5039end
5040
5041#-----------------------------------------------------
5042# Device and Parasitic extraction
5043#-----------------------------------------------------
5044
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5045extract
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5046 style ngspice variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5047 cscale 1
5048 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5049 # dimensions must be in units of microns in the extract file.
5050 # Use extract style "ngspice(si)" to override this and produce
5051 # a file with SI units for length/area.
5052
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5053 variants (),(orig),(hrhc),(lrhc),(hrlc),(lrlc)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5054 lambda 1E6
5055 variants (si)
5056 lambda 1.0
5057 variants *
5058
5059 units microns
5060 step 7
5061 sidehalo 2
5062
5063 # NOTE: MiM cap layers have been purposely put out of order,
5064 # may want to reconsider.
5065
5066 planeorder dwell 0
5067 planeorder well 1
5068 planeorder active 2
5069 planeorder locali 3
5070 planeorder metal1 4
5071 planeorder metal2 5
5072 planeorder metal3 6
5073#ifdef METAL5
5074 planeorder metal4 7
5075 planeorder metal5 8
5076#ifdef REDISTRIBUTION
5077 planeorder metali 9
5078 planeorder block 10
5079 planeorder comment 11
5080 planeorder cap1 12
5081 planeorder cap2 13
5082#else (!REDISTRIBUTION)
5083 planeorder block 9
5084 planeorder comment 10
5085 planeorder cap1 11
5086 planeorder cap2 12
5087#endif (!REDISTRIBUTION)
5088#else (!METAL5)
5089#ifdef REDISTRIBUTION
5090 planeorder metali 7
5091 planeorder block 8
5092 planeorder comment 9
5093 planeorder cap1 10
5094 planeorder cap2 11
5095#else (!REDISTRIBUTION)
5096 planeorder block 7
5097 planeorder comment 8
5098 planeorder cap1 9
5099 planeorder cap2 10
5100#endif (!REDISTRIBUTION)
5101#endif (!METAL5)
5102
5103 height dnwell -0.1 0.1
5104 height nwell,pwell 0.0 0.2062
5105 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5106 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5107 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5108 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5109 height alldiffcont 0.3262 0.61
5110 height pc 0.5062 0.43
5111 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5112 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5113 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5114 height m1fill 1.3761 0.36
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5115#ifdef RERAM
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5116 height v1 1.7361 0.565
5117 height allm2 2.3011 0.36
5118 height m2fill 2.3011 0.36
5119 height v2 2.6611 0.42
5120 height allm3 3.0811 0.845
5121 height m3fill 3.0811 0.845
5122#ifdef MIM
5123 height mimcap 2.7611 0.2
5124 height mimcap2 4.0261 0.2
5125 height mimcc 2.9611 0.12
5126 height mim2cc 4.2261 0.09
5127#endif (MIM)
5128#ifdef METAL5
5129 height v3 3.9261 0.39
5130 height allm4 4.3161 0.845
5131 height m4fill 4.3161 0.845
5132 height v4 5.1611 0.505
5133 height allm5 5.6661 1.26
5134 height m5fill 5.6661 1.26
5135#ifdef REDISTRIBUTION
5136 height mrdlc 6.9261 0.63
5137 height mrdl 7.5561 3.0
5138#endif (!REDISTRIBUTION)
5139#endif (!METAL5)
5140#else (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5141 height v1 1.7361 0.27
5142 height allm2 2.0061 0.36
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5143 height m2fill 2.0061 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5144 height v2 2.3661 0.42
5145 height allm3 2.7861 0.845
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5146 height m3fill 2.7861 0.845
5147#ifdef MIM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5148 height mimcap 2.4661 0.2
5149 height mimcap2 3.7311 0.2
5150 height mimcc 2.6661 0.12
5151 height mim2cc 3.9311 0.09
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5152#endif (MIM)
5153#ifdef METAL5
5154 height v3 3.6311 0.39
5155 height allm4 4.0211 0.845
5156 height m4fill 4.0211 0.845
5157 height v4 4.8661 0.505
5158 height allm5 5.3711 1.26
5159 height m5fill 5.3711 1.26
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5160#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]5161 height mrdlc 6.6311 0.63
5162 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5163#endif (!REDISTRIBUTION)
5164#endif (!METAL5)
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5165#endif (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5166
5167 # Antenna check parameters
5168 # Note that checks w/diode diffusion are not modeled
5169 model partial
5170 antenna poly sidewall 50 none
5171 antenna allcont surface 3 none
5172 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5173 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5174 antenna m1,m2,m3 sidewall 400 2600 400
5175 antenna v1 surface 3 0 18
5176 antenna v2 surface 6 0 36
5177#ifdef METAL5
5178 antenna m4,m5 sidewall 400 2600 400
5179 antenna v3,v4 surface 6 0 36
5180#endif (METAL5)
5181
5182 tiedown alldiffnonfet
5183
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]5184 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5186# Resistances are in milliohms per square
5187# Optional 3rd argument is the corner adjustment fraction
5188# Device values come from trtc.cor (typical corner)
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5189
5190variants (),(orig),(si)
5191
Tim Edwards14beb9c2021-09-15 16:19:23 -0400[diff] [blame]5192 resist (pwell,isosub)/well 4400000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5193 resist (dnwell)/dwell 2200000
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5194 resist (nwell)/well 950000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5195 resist (rpw)/well 3050000 0.5
5196 resist (*ndiff,nsd)/active 120000
5197 resist (*pdiff,*psd)/active 197000
5198 resist (*mvndiff,mvnsd)/active 114000
5199 resist (*mvpdiff,*mvpsd)/active 191000
5200
5201 resist ndiffres/active 120000 0.5
5202 resist pdiffres/active 197000 0.5
5203 resist mvndiffres/active 114000 0.5
5204 resist mvpdiffres/active 191000 0.5
5205 resist mrp1/active 48200 0.5
5206 resist xhrpoly/active 319800 0.5
5207 resist uhrpoly/active 2000000 0.5
5208
5209 resist (allpolynonres)/active 48200
5210 resist rmp/active 48200
5211
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5212 resist (allli)/locali 12800
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5213 resist (allm1)/metal1 125
5214 resist (allm2)/metal2 125
5215 resist (allm3)/metal3 47
5216#ifdef METAL5
5217 resist (allm4)/metal4 47
5218 resist (allm5)/metal5 29
5219#endif (METAL5)
5220#ifdef REDISTRIBUTION
5221 resist mrdl/metali 5
5222#endif (REDISTRIBUTION)
5223
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5224 contact ndc,nsc 185000
5225 contact pdc,psc 585000
5226 contact mvndc,mvnsc 185000
5227 contact mvpdc,mvpsc 585000
5228 contact pc 152000
5229 contact mcon 9300
5230#ifdef RERAM
5231 contact m2c 9000
5232#else
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5233 contact m2c 4500
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5234#endif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5235 contact m3c 3410
5236#ifdef METAL5
5237#ifdef MIM
5238 contact mimcc 4500
5239 contact mim2cc 3410
5240#endif (MIM)
5241 contact via3 3410
5242 contact via4 380
5243#endif (METAL5)
5244#ifdef REDISTRIBUTION
5245 contact mrdlc 6
5246#endif (REDISTRIBUTION)
5247
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5248variants (hrhc),(hrlc)
5249
5250 # High-end corner resistances
5251 # No corner values available for: substrate, xhrpoly, uhrpoly, RDL
5252 resist (pwell,isosub)/well 4400000
5253 resist (dnwell)/dwell 2575000
5254 resist (nwell)/well 1350000
5255 resist (rpw)/well 3535000 0.5
5256 resist (*ndiff,nsd)/active 132000
5257 resist (*pdiff,*psd)/active 228000
5258 resist (*mvndiff,mvnsd)/active 126000
5259 resist (*mvpdiff,*mvpsd)/active 228000
5260
5261 resist ndiffres/active 132000 0.5
5262 resist pdiffres/active 228000 0.5
5263 resist mvndiffres/active 126000 0.5
5264 resist mvpdiffres/active 228000 0.5
5265 resist mrp1/active 55800 0.5
5266 resist xhrpoly/active 319800 0.5
5267 resist uhrpoly/active 2000000 0.5
5268
5269 resist (allpolynonres)/active 55800
5270 resist rmp/active 55800
5271
5272 resist (allli)/locali 17000
5273 resist (allm1)/metal1 145
5274 resist (allm2)/metal2 145
5275 resist (allm3)/metal3 56
5276#ifdef METAL5
5277 resist (allm4)/metal4 56
5278 resist (allm5)/metal5 36
5279#endif (METAL5)
5280#ifdef REDISTRIBUTION
5281 resist mrdl/metali 5
5282#endif (REDISTRIBUTION)
5283
5284 contact ndc,nsc 280000
5285 contact pdc,psc 840000
5286 contact mvndc,mvnsc 280000
5287 contact mvpdc,mvpsc 840000
5288 contact pc 252000
5289 contact mcon 23000
5290#ifdef RERAM
5291 contact m2c 30000
5292#else
5293 contact m2c 15000
5294#endif
5295 contact m3c 8000
5296#ifdef METAL5
5297#ifdef MIM
5298 contact mimcc 15000
5299 contact mim2cc 8000
5300#endif (MIM)
5301 contact via3 8000
5302 contact via4 891
5303#endif (METAL5)
5304#ifdef REDISTRIBUTION
5305 contact mrdlc 6
5306#endif (REDISTRIBUTION)
5307
5308variants (lrhc),(lrlc)
5309
5310 # Low-end corner resistances
5311 # No corner values available for: substrate, xhrpoly, uhrpoly, RDL
5312 resist (pwell,isosub)/well 4400000
5313 resist (dnwell)/dwell 1825000
5314 resist (nwell)/well 550000
5315 resist (rpw)/well 2565000 0.5
5316 resist (*ndiff,nsd)/active 108000
5317 resist (*pdiff,*psd)/active 166000
5318 resist (*mvndiff,mvnsd)/active 102000
5319 resist (*mvpdiff,*mvpsd)/active 160000
5320
5321 resist ndiffres/active 108000 0.5
5322 resist pdiffres/active 166000 0.5
5323 resist mvndiffres/active 102000 0.5
5324 resist mvpdiffres/active 160000 0.5
5325 resist mrp1/active 42200 0.5
5326 resist xhrpoly/active 319800 0.5
5327 resist uhrpoly/active 2000000 0.5
5328
5329 resist (allpolynonres)/active 42200
5330 resist rmp/active 42200
5331
5332 resist (allli)/locali 10500
5333 resist (allm1)/metal1 105
5334 resist (allm2)/metal2 105
5335 resist (allm3)/metal3 38
5336#ifdef METAL5
5337 resist (allm4)/metal4 38
5338 resist (allm5)/metal5 21
5339#endif (METAL5)
5340#ifdef REDISTRIBUTION
5341 resist mrdl/metali 5
5342#endif (REDISTRIBUTION)
5343
5344 contact ndc,nsc 95000
5345 contact pdc,psc 345000
5346 contact mvndc,mvnsc 95000
5347 contact mvpdc,mvpsc 345000
5348 contact pc 52000
5349 contact mcon 1600
5350#ifdef RERAM
5351 contact m2c 4000
5352#else
5353 contact m2c 2000
5354#endif
5355 contact m3c 500
5356#ifdef METAL5
5357#ifdef MIM
5358 contact mimcc 2000
5359 contact mim2cc 500
5360#endif (MIM)
5361 contact via3 500
5362 contact via4 12
5363#endif (METAL5)
5364#ifdef REDISTRIBUTION
5365 contact mrdlc 6
5366#endif (REDISTRIBUTION)
5367
5368variants *
5369
5370 # These types should not be considered as electrical nodes
5371 resist blocktypes None
5372 resist obstypes None
5373 resist idtypes None
5374 resist comment None
5375
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5376#-------------------------------------------------------------------------
5377# Parasitic capacitance values: Use document (...)
5378#-------------------------------------------------------------------------
5379# This uses the new "default" definitions that determine the intervening
5380# planes from the planeorder stack, take care of the reflexive sideoverlap
5381# definitions, and generally clean up the section and make it more readable.
5382#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5383# Also uses "units microns" statement. All values are taken from the
5384# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5385# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5386#-------------------------------------------------------------------------
5387# Remember that device capacitances to substrate are taken care of by the
5388# models. Thus, active and poly definitions ignore all "fet" types.
5389# fet types are excluded when computing parasitic capacitance to
5390# active from layers above them because poly is a shield; fet types are
5391# included for parasitics from layers above to poly. Resistor types
5392# should be removed from all parasitic capacitance calculations, or else
5393# they just create floating caps. Technically, the capacitance probably
5394# should be split between the two terminals. Unsure of the correct model.
5395#-------------------------------------------------------------------------
5396
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5397variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc)
5398# Nominal capacitances
5399
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5400#deep n-well
5401defaultareacap dnwell dwell 120
5402
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5403#p-well
5404defaultoverlap pwell well dnwell dwell 120
5405
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5406#n-well
5407# NOTE: This value not found in PEX files
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5408defaultareacap nwell well dnwell dwell 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5409
5410#n-active
5411# Rely on device models to capture *ndiff area cap
5412# Do not extract parasitics from resistors
5413# defaultareacap allnactivenonfet active 790
5414# defaultperimeter allnactivenonfet active 280
5415
5416#p-active
5417# Rely on device models to capture *pdiff area cap
5418# Do not extract parasitics from resistors
5419# defaultareacap allpactivenonfet active 810
5420# defaultperimeter allpactivenonfet active 300
5421
5422#poly
5423# Do not extract parasitics from resistors
5424# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5425# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5426# defaultperimeter allpolynonfet active 57
5427
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5428 defaultsidewall *poly active 22.6
5429 defaultareacap *poly active 106.13
5430 defaultperimeter *poly active 55.27
5431 defaultsideoverlap *poly active nwell,pwell well 55.27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5432
5433#locali
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5434 defaultsidewall allli locali 32.51
5435 defaultareacap allli locali 36.99
5436 defaultperimeter allli locali 40.70
5437 defaultoverlap allli locali nwell,pwell well 36.99
5438 defaultsideoverlap allli locali nwell,pwell well 40.70
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5439
5440#locali->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5441 defaultoverlap allli locali allactivenonfet active 36.99
5442 defaultsideoverlap allli locali allactivenonfet active 40.70
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5443
5444#locali->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5445 defaultoverlap allli locali allpolynonres active 94.16
5446 defaultsideoverlap allli locali allpolynonres active 51.85
5447 defaultsideoverlap *poly active allli locali 25.14
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5448
5449#metal1
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5450 defaultsidewall allm1 metal1 44.74
5451 defaultareacap allm1 metal1 25.78
5452 defaultperimeter allm1 metal1 40.57
5453 defaultoverlap allm1 metal1 nwell,pwell well 25.78
5454 defaultsideoverlap allm1 metal1 nwell,pwell well 40.57
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5455
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5456#metal1->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5457 defaultoverlap allm1 metal1 allactivenonfet active 25.78
5458 defaultsideoverlap allm1 metal1 allactivenonfet active 40.57
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5459
5460#metal1->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5461 defaultoverlap allm1 metal1 allpolynonres active 44.81
5462 defaultsideoverlap allm1 metal1 allpolynonres active 46.72
5463 defaultsideoverlap *poly active allm1 metal1 16.69
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5464
5465#metal1->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5466 defaultoverlap allm1 metal1 allli locali 114.20
5467 defaultsideoverlap allm1 metal1 allli locali 59.50
5468 defaultsideoverlap allli locali allm1 metal1 34.70
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5469
5470#metal2
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5471 defaultsidewall allm2 metal2 49.68
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5472
5473#ifdef RERAM
5474# For ReRAM, all parasitics account for the additional 0.295um between
5475# metal1 and metal2
5476
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5477 defaultareacap allm2 metal2 14.77
5478 defaultperimeter allm2 metal2 32.92
5479 defaultoverlap allm2 metal2 nwell,pwell well 14.77
5480 defaultsideoverlap allm2 metal2 nwell,pwell well 32.92
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5481
5482#metal2->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5483 defaultoverlap allm2 metal2 allactivenonfet active 14.77
5484 defaultsideoverlap allm2 metal2 allactivenonfet active 32.92
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5485
5486#metal2->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5487 defaultoverlap allm2 metal2 allpolynonres active 20.47
5488 defaultsideoverlap allm2 metal2 allpolynonres active 34.45
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5489 defaultsideoverlap *poly active allm2 metal2 9
5490
5491#metal2->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5492 defaultoverlap allm2 metal2 allli locali 28.80
5493 defaultsideoverlap allm2 metal2 allli locali 35.49
5494 defaultsideoverlap allli locali allm2 metal2 16.67
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5495
5496#metal2->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5497 defaultoverlap allm2 metal2 allm1 metal1 63.97
5498 defaultsideoverlap allm2 metal2 allm1 metal1 32.04
5499 defaultsideoverlap allm1 metal1 allm2 metal2 23.03
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5500
5501#else (!RERAM)
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5502 defaultareacap allm2 metal2 16.94
5503 defaultperimeter allm2 metal2 37.76
5504 defaultoverlap allm2 metal2 nwell,pwell well 16.94
5505 defaultsideoverlap allm2 metal2 nwell,pwell well 37.76
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5506
5507#metal2->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5508 defaultoverlap allm2 metal2 allactivenonfet active 16.94
5509 defaultsideoverlap allm2 metal2 allactivenonfet active 37.76
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5510
5511#metal2->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5512 defaultoverlap allm2 metal2 allpolynonres active 24.50
5513 defaultsideoverlap allm2 metal2 allpolynonres active 41.22
5514 defaultsideoverlap *poly active allm2 metal2 11.17
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5515
5516#metal2->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5517 defaultoverlap allm2 metal2 allli locali 37.56
5518 defaultsideoverlap allm2 metal2 allli locali 46.28
5519 defaultsideoverlap allli locali allm2 metal2 21.74
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5520
5521#metal2->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5522 defaultoverlap allm2 metal2 allm1 metal1 133.86
5523 defaultsideoverlap allm2 metal2 allm1 metal1 67.05
5524 defaultsideoverlap allm1 metal1 allm2 metal2 48.19
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5525
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5526#endif (!RERAM)
5527
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5528#metal3
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5529 defaultsidewall allm3 metal3 63.15
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5530
5531#ifdef RERAM
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5532 defaultareacap allm3 metal3 11.19
5533 defaultperimeter allm3 metal3 37.07
5534 defaultoverlap allm3 metal3 nwell,pwell well 11.19
5535 defaultsideoverlap allm3 metal3 nwell,pwell well 37.07
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5536
5537#metal3->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5538 defaultoverlap allm3 metal3 allactive active 11.19
5539 defaultsideoverlap allm3 metal3 allactive active 37.07
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5540
5541#metal3->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5542 defaultoverlap allm3 metal3 allpolynonres active 14.22
5543 defaultsideoverlap allm3 metal3 allpolynonres active 38.54
5544 defaultsideoverlap *poly active allm3 metal3 8.13
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5545
5546#metal3->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5547 defaultoverlap allm3 metal3 allli locali 17.79
5548 defaultsideoverlap allm3 metal3 allli locali 39.97
5549 defaultsideoverlap allli locali allm3 metal3 12.90
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5550
5551#metal3->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5552 defaultoverlap allm3 metal3 allm1 metal1 26.96
5553 defaultsideoverlap allm3 metal3 allm1 metal1 42.79
5554 defaultsideoverlap allm1 metal1 allm3 metal3 20.83
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5555
5556#else (!RERAM)
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5557 defaultareacap allm3 metal3 12.37
5558 defaultperimeter allm3 metal3 40.99
5559 defaultoverlap allm3 metal3 nwell,pwell well 12.37
5560 defaultsideoverlap allm3 metal3 nwell,pwell well 40.99
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5561
5562#metal3->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5563 defaultoverlap allm3 metal3 allactive active 12.37
5564 defaultsideoverlap allm3 metal3 allactive active 40.99
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5565
5566#metal3->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5567 defaultoverlap allm3 metal3 allpolynonres active 16.06
5568 defaultsideoverlap allm3 metal3 allpolynonres active 43.53
5569 defaultsideoverlap *poly active allm3 metal3 9.18
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5570
5571#metal3->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5572 defaultoverlap allm3 metal3 allli locali 20.79
5573 defaultsideoverlap allm3 metal3 allli locali 46.71
5574 defaultsideoverlap allli locali allm3 metal3 15.08
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5575
5576#metal3->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5577 defaultoverlap allm3 metal3 allm1 metal1 34.54
5578 defaultsideoverlap allm3 metal3 allm1 metal1 54.81
5579 defaultsideoverlap allm1 metal1 allm3 metal3 26.68
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5580
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5581#endif (!RERAM)
5582
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5583#metal3->metal2
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5584 defaultoverlap allm3 metal3 allm2 metal2 86.19
5585 defaultsideoverlap allm3 metal3 allm2 metal2 69.85
5586 defaultsideoverlap allm2 metal2 allm3 metal3 44.43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5587
5588#ifdef METAL5
5589#metal4
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5590 defaultsidewall allm4 metal4 67.33
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5591#ifdef RERAM
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5592 defaultareacap allm4 metal4 7.84
5593 defaultperimeter allm4 metal4 34.17
5594 defaultoverlap allm4 metal4 nwell,pwell well 7.84
5595 defaultsideoverlap allm4 metal4 nwell,pwell well 34.17
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5596
5597#metal4->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5598 defaultoverlap allm4 metal4 allactivenonfet active 7.84
5599 defaultsideoverlap allm4 metal4 allactivenonfet active 34.17
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5600
5601#metal4->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5602 defaultoverlap allm4 metal4 allpolynonres active 9.24
5603 defaultsideoverlap allm4 metal4 allpolynonres active 35.16
5604 defaultsideoverlap *poly active allm4 metal4 5.86
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5605
5606#metal4->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5607 defaultoverlap allm4 metal4 allli locali 10.62
5608 defaultsideoverlap allm4 metal4 allli locali 36.14
5609 defaultsideoverlap allli locali allm4 metal4 9.23
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5610
5611#metal4->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5612 defaultoverlap allm4 metal4 allm1 metal1 13.31
5613 defaultsideoverlap allm4 metal4 allm1 metal1 37.70
5614 defaultsideoverlap allm1 metal1 allm4 metal4 14.54
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5615
5616#else (!RERAM)
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5617 defaultareacap allm4 metal4 8.42
5618 defaultperimeter allm4 metal4 36.68
5619 defaultoverlap allm4 metal4 nwell,pwell well 8.42
5620 defaultsideoverlap allm4 metal4 nwell,pwell well 36.68
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5621
5622#metal4->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5623 defaultoverlap allm4 metal4 allactivenonfet active 8.42
5624 defaultsideoverlap allm4 metal4 allactivenonfet active 36.68
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5625
5626#metal4->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5627 defaultoverlap allm4 metal4 allpolynonres active 10.01
5628 defaultsideoverlap allm4 metal4 allpolynonres active 38.11
5629 defaultsideoverlap *poly active allm4 metal4 6.35
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5630
5631#metal4->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5632 defaultoverlap allm4 metal4 allli locali 11.67
5633 defaultsideoverlap allm4 metal4 allli locali 39.71
5634 defaultsideoverlap allli locali allm4 metal4 10.14
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5635
5636#metal4->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5637 defaultoverlap allm4 metal4 allm1 metal1 15.03
5638 defaultsideoverlap allm4 metal4 allm1 metal1 42.56
5639 defaultsideoverlap allm1 metal1 allm4 metal4 16.42
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5640
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5641#endif (!RERAM)
5642
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5643#metal4->metal2
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5644 defaultoverlap allm4 metal4 allm2 metal2 20.33
5645 defaultsideoverlap allm4 metal4 allm2 metal2 46.38
5646 defaultsideoverlap allm2 metal2 allm4 metal4 22.33
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5647
5648#metal4->metal3
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5649 defaultoverlap allm4 metal4 allm3 metal3 84.03
5650 defaultsideoverlap allm4 metal4 allm3 metal3 70.52
5651 defaultsideoverlap allm3 metal3 allm4 metal4 42.64
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5652
5653#metal5
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5654 defaultsidewall allm5 metal5 127.06
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5655#ifdef RERAM
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5656 defaultareacap allm5 metal5 5.99
Tim Edwardsf2a114e2022-02-25 18:12:33 -0500[diff] [blame^]5657 defaultperimeter allm5 metal5 5.99
5658 defaultoverlap allm5 metal5 nwell,pwell well 36.83
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5659 defaultsideoverlap allm5 metal5 nwell,pwell well 36.83
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5660
5661#metal5->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5662 defaultoverlap allm5 metal5 allactivenonfet active 5.99
5663 defaultsideoverlap allm5 metal5 allactivenonfet active 36.83
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5664
5665#metal5->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5666 defaultoverlap allm5 metal5 allpolynonres active 6.80
5667 defaultsideoverlap allm5 metal5 allpolynonres active 37.63
5668 defaultsideoverlap *poly active allm5 metal5 6.12
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5669
5670#metal5->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5671 defaultoverlap allm5 metal5 allli locali 7.52
5672 defaultsideoverlap allm5 metal5 allli locali 38.53
5673 defaultsideoverlap allli locali allm5 metal5 7.15
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5674
5675#metal5->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5676 defaultoverlap allm5 metal5 allm1 metal1 8.77
5677 defaultsideoverlap allm5 metal5 allm1 metal1 39.95
5678 defaultsideoverlap allm1 metal1 allm5 metal5 11.12
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5679
5680#else (!RERAM)
Tim Edwards429c83e2022-02-23 14:58:05 -0500[diff] [blame]5681 defaultareacap allm5 metal5 6.32
5682 defaultperimeter allm5 metal5 38.85
5683 defaultoverlap allm5 metal5 nwell,pwell well 6.32
5684 defaultsideoverlap allm5 metal5 nwell,pwell well 38.85
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5685
5686#metal5->diff
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5687 defaultoverlap allm5 metal5 allactivenonfet active 6.32
5688 defaultsideoverlap allm5 metal5 allactivenonfet active 38.85
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5689
5690#metal5->poly
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5691 defaultoverlap allm5 metal5 allpolynonres active 7.21
5692 defaultsideoverlap allm5 metal5 allpolynonres active 39.91
5693 defaultsideoverlap *poly active allm5 metal5 6.49
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5694
5695#metal5->locali
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5696 defaultoverlap allm5 metal5 allli locali 8.03
5697 defaultsideoverlap allm5 metal5 allli locali 41.15
5698 defaultsideoverlap allli locali allm5 metal5 7.64
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5699
5700#metal5->metal1
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5701 defaultoverlap allm5 metal5 allm1 metal1 9.48
5702 defaultsideoverlap allm5 metal5 allm1 metal1 43.19
5703 defaultsideoverlap allm1 metal1 allm5 metal5 12.02
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5704
Tim Edwardsfb7b41f2022-01-18 11:46:30 -0500[diff] [blame]5705#endif (!RERAM)
5706
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5707#metal5->metal2
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5708 defaultoverlap allm5 metal5 allm2 metal2 11.34
5709 defaultsideoverlap allm5 metal5 allm2 metal2 45.59
5710 defaultsideoverlap allm2 metal2 allm5 metal5 15.69
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5711
5712#metal5->metal3
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5713 defaultoverlap allm5 metal5 allm3 metal3 19.63
5714 defaultsideoverlap allm5 metal5 allm3 metal3 54.15
5715 defaultsideoverlap allm3 metal3 allm5 metal5 27.84
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5716
5717#metal5->metal4
Tim Edwardse52981f2022-02-21 17:52:51 -0500[diff] [blame]5718 defaultoverlap allm5 metal5 allm4 metal4 68.33
5719 defaultsideoverlap allm5 metal5 allm4 metal4 82.82
5720 defaultsideoverlap allm4 metal4 allm5 metal5 46.98
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5721#endif (METAL5)
5722
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5723variants *
5724
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5725#ifdef REDISTRIBUTION
5726#endif (REDISTRIBUTION)
5727
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5728# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5729
Tim Edwards220e0772022-02-09 10:16:39 -0500[diff] [blame]5730variants (),(si),(hrhc),(lrhc),(hrlc),(lrlc)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5731
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5732 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5733 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5734 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5735 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5736 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5737 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5738 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5739 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5740 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5741 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5742 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5743 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5744 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5745 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5746 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5747
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5748 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5749 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5750 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5751 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5752 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5753 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5754 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5755 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5756 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5757 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5758 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5759 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5760 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5761 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5762 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5763 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5764 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5765 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5766 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5767 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5768 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5769 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5770 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5771 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5772
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5773 # Bipolars
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5774 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
5775 error +npn1p00
5776 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
5777 error +npn2p00
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]5778 device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5779 device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
5780 pwell,space/w +pnp0p68
5781 device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
5782 pwell,space/w +pnp3p40
Tim Edwardsb9668302021-05-27 14:10:11 -0400[diff] [blame]5783 device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5784 device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
5785 dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5786 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5787
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5788 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5789 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5790 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5791 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5792
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5793 # Extended drain devices (must appear before the regular devices)
5794 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5795 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5796 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5797 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5798 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5799 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5800
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5801 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5802 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5803 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5804 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5805 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5806 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5807 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5808 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5809 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5810 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5811 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5812 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5813 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5814 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5815 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5816 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5817 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5818 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5819
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5820 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5821 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5822 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5823 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5824#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5825 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5826 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5827#endif (METAL5)
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]5828 device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \
5829 photo pwell,space/w error a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5830
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5831 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5832 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5833 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5834 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5835 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5836 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5837 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5838 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5839 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5840 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5841 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5842 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5843 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5844 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5845 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5846 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5847 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5848 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5849 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5850 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5851 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5852 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5853 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5854 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5855
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5856 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5857 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5858 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5859 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5860 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5861 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5862 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5863 *mvndiff pwell,space/w error l=l w=w
5864 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5865 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5866
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5867 device resistor sky130_fd_pr__res_generic_po rmp *poly
5868 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5869
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5870 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
5871 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
5872 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
5873 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5874
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5875 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
5876 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
5877 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
5878 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5879
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5880#ifdef RERAM
Tim Edwardsf1bee922021-11-24 23:05:34 -0500[diff] [blame]5881 device csubcircuit sky130_fd_pr__reram_reram_cell reram m1 a=area_ox
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5882#endif (RERAM)
5883
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5884#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5885 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5886 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5887#endif (MIM)
5888
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5889 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5890
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5891 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5892 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5893 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5894 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5895 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5896 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5897 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5898 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5899 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5900 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5901 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5902 pwell,space/w
5903
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5904 # Note that corenvar, corepvar are not considered devices, and extract as
5905 # parasitic capacitance instead (but cap values need to be added).
5906
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5907 # Extended drain devices (must appear before the regular devices)
5908 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5909 dnwell pwell,space/w error
5910 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5911 dnwell pwell,space/w error
5912 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5913 pwell,space/w nwell error
5914
5915 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5916 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5917 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5918 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5919 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5920 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5921
5922 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5923 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5924 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5925 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5926
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5927 device resistor sky130_fd_pr__res_generic_po rmp *poly
5928 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5929 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5930 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5931 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5932#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5933 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5934 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5935#endif (METAL5)
5936
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5937 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5938 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5939 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5940 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5941 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5942 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5943 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5944 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5945 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5946 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5947 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5948 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5949 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5950 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5951 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5952 device resistor mrdn_hv mvndiffres *mvndiff
5953 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5954 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5955
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5956 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5957 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5958 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5959 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5960
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5961 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5962 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5963 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5964 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5965
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5966 device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
5967 device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5968 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5969 device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
5970 device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5971 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5972 device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5973 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5974
5975#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5976 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5977 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5978#endif (MIM)
5979
5980end
5981
5982#-----------------------------------------------------
5983# Wiring tool definitions
5984#-----------------------------------------------------
5985
5986wiring
5987 # All wiring values are in nanometers
5988 scalefactor 10
5989
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5990 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5991 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5992 contact v2 280 m2 0 45 m3 25 0
5993#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5994 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5995 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5996#endif (METAL5)
5997
5998 contact pc 170 poly 50 80 li 0 80
5999 contact pdc 170 pdiff 40 60 li 0 80
6000 contact ndc 170 ndiff 40 60 li 0 80
6001 contact psc 170 psd 40 60 li 0 80
6002 contact nsc 170 nsd 40 60 li 0 80
6003
6004end
6005
6006#-----------------------------------------------------
6007# Plain old router. . .
6008#-----------------------------------------------------
6009
6010router
6011end
6012
6013#------------------------------------------------------------
6014# Plowing (restored in magic 8.2, need to fill this section)
6015#------------------------------------------------------------
6016
6017plowing
6018end
6019
6020#-----------------------------------------------------------------
6021# No special plot layers defined (use default PNM color choices)
6022#-----------------------------------------------------------------
6023
6024plot
6025 style pnm
6026 default
6027 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]6028 draw fillblock4 no_color_at_all
6029 draw fomfill no_color_at_all
6030 draw polyfill no_color_at_all
6031 draw m1fill no_color_at_all
6032 draw m2fill no_color_at_all
6033 draw m3fill no_color_at_all
6034 draw m4fill no_color_at_all
6035 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6036 draw nwell cwell
6037end
6038