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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / d7289eba5e17fa4c0bc5618f994820b8901a437c / . / sky130 / magic / sky130.tech
blob: 994e000dfaca7c00459ee61375a57bd956693938 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18# This file is designed to be used with magic versions
19# 8.3.24 or newer.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]20#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]21tech
22 format 35
23 TECHNAME
24end
25
26version
27 version REVISION
28 description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
29end
30
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]31#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]32# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]33# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]34# Status 8/14/20: Rev 2 (alpha):
35# Started updating with new device/model naming convention
36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]39# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]40#------------------------------------------------------------------------
41# device name magic ID layer description
42#------------------------------------------------------------------------
43# sky130_fd_pr__nfet_01v8 nfet standard nFET
44# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]45# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
46# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]48# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]49# sky130_fd_pr__pfet_01v8 pfet standard pFET
50# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]51# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]52# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
53# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
54# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
55# sky130_fd_pr__nfet_03v3_nvt --- native nFET
56# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
57# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
58# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]59# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
60# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
61# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
62# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]63# sky130_fd_pr__diode_pw2nd_nvt nndiode diode with nndiff
64# sky130_fd_pr__diode_pw2nd_lvt ndiodelvt low Vt n+ diff diode
65# sky130_fd_pr__diode_pd2nw_lvt pdiodelvt low Vt p+ diff diode
66# sky130_fd_pr__diode_pd2nw_hvt pdiodehvt high Vt p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
68# sky130_fd_pr__npn_11v0 mvpbase thick oxide gated NPN
69# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]70# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
71# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
72# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]73# mrdn_hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]74# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]75# mrdp_hv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]76# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
77# sky130_fd_pr__res_generic_po npres n+ poly resistor
78# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
79# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
80# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
81# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
82# sky130_fd_pr__cap_var mvvaractor thickox varactor
83# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
98# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET
99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
100# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET
101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
145
146# Wells
147 well nwell,nw
148 -well pwell,pw
149 -well rpw,rpwell
150 -well obswell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]151 -well pbase,npn
152 -well mvpbase,mvnpn
153 -well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]154
155# Transistors
156 active nmos,ntransistor,nfet
157 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]158 -active npd,npdfet,sramnfet
159 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]160 active pmos,ptransistor,pfet
161 -active scpmos,scptransistor,scpfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]163 -active nnmos,nntransistor
164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
166 -active mvnnmos,mvnntransistor,mvnnfet,nnfet
167 -active varactor,varact,var
168 -active mvvaractor,mvvaract,mvvar
169
170 -active pmoslvt,pfetlvt
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]171 -active pmosmvt,pfetmvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]172 -active pmoshvt,pfethvt
173 -active nmoslvt,nfetlvt
174 -active varactorhvt,varacthvt,varhvt
175 -active nsonos,sonos
176
177# Diffusions
178 active ndiff,ndiffusion,ndif
179 active pdiff,pdiffusion,pdif
180 -active mvndiff,mvndiffusion,mvndif
181 -active mvpdiff,mvpdiffusion,mvpdif
182 active ndiffc,ndcontact,ndc
183 active pdiffc,pdcontact,pdc
184 -active mvndiffc,mvndcontact,mvndc
185 -active mvpdiffc,mvpdcontact,mvpdc
186 active psubdiff,psubstratepdiff,ppdiff,ppd,psd
187 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
188 -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
189 -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
190 active psubdiffcont,psubstratepcontact,psc
191 active nsubdiffcont,nsubstratencontact,nsc
192 -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
193 -active mvnsubdiffcont,mvnsubstratencontact,mvnsc
194 -active obsactive
195 -active mvobsactive
196
197# Poly
198 active poly,p,polysilicon
199 active polycont,pc,pcontact,polycut,polyc
200 active xpolycontact,xpolyc,xpc
201
202# Resistors
203 -active npolyres,npres,mrp1
204 -active ppolyres,ppres,xhrpoly
205 -active xpolyres,xpres,xres,uhrpoly
206 -active ndiffres,rnd,rdn,rndiff
207 -active pdiffres,rpd,rdp,rpdiff
208 -active mvndiffres,mvrnd,mvrdn,mvrndiff
209 -active mvpdiffres,mvrpd,mvrdp,mvrpdiff
210 -active rmp
211
212# Diodes
213 -active pdiode,pdi
214 -active ndiode,ndi
215 -active nndiode,nndi
216 -active pdiodec,pdic
217 -active ndiodec,ndic
218 -active nndiodec,nndic
219 -active mvpdiode,mvpdi
220 -active mvndiode,mvndi
221 -active mvpdiodec,mvpdic
222 -active mvndiodec,mvndic
223 -active pdiodelvt,pdilvt
224 -active pdiodehvt,pdihvt
225 -active ndiodelvt,ndilvt
226 -active pdiodelvtc,pdilvtc
227 -active pdiodehvtc,pdihvtc
228 -active ndiodelvtc,ndilvtc
229
230# Local Interconnect
231 locali locali,li1,li
232 -locali corelocali,coreli1,coreli
233 -locali rlocali,rli1,rli
234 locali viali,vial,lic,licon,m1c,v0
235 -locali obsli1,obsli
236 -locali obsli1c,obslic,obslicon
237
238# Metal 1
239 metal1 metal1,m1,met1
240 -metal1 rmetal1,rm1,rmet1
241 metal1 via1,m2contact,m2cut,m2c,via,v,v1
242 -metal1 obsm1
243 -metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]244 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245
246# Metal 2
247 metal2 metal2,m2,met2
248 -metal2 rmetal2,rm2,rmet2
249 metal2 via2,m3contact,m3cut,m3c,v2
250 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 3
254 metal3 metal3,m3,met3
255 -metal3 rmetal3,rm3,rmet3
256 -metal3 obsm3
257#ifdef METAL5
258 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]259 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260
261#ifdef MIM
262 -cap1 mimcap,mim,capm
263 -cap1 mimcapcontact,mimcapc,mimcc,capmc
264#endif
265
266# Metal 4
267 metal4 metal4,m4,met4
268 -metal4 rmetal4,rm4,rmet4
269 -metal4 obsm4
270 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]271 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]272
273#ifdef MIM
274 -cap2 mimcap2,mim2,capm2
275 -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
276#endif
277
278# Metal 5
279 metal5 metal5,m5,met5
280 -metal5 rm5,rmetal5,rmet5
281 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]282 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif (METAL5)
284
285#ifdef REDISTRIBUTION
286 -metal5 mrdlcontact,mrdlc
287 -metali metalrdl,mrdl,metrdl
288 -metali obsmrdl
289#endif (REDISTRIBUTION)
290
291# Miscellaneous
292 -block glass
293 -block fillblock
294 -comment comment
295 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]296# fixed resistor width identifiers
297 -comment res0p35
298 -comment res0p69
299 -comment res1p41
300 -comment res2p85
301 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]302
303end
304
305#-----------------------------------------------------
306# Magic contact types
307#-----------------------------------------------------
308
309contact
310 pc poly locali
311 ndc ndiff locali
312 pdc pdiff locali
313 nsc nsd locali
314 psc psd locali
315 ndic ndiode locali
316 ndilvtc ndiodelvt locali
317 nndic nndiode locali
318 pdic pdiode locali
319 pdilvtc pdiodelvt locali
320 pdihvtc pdiodehvt locali
321 xpc xpc locali
322
323 mvndc mvndiff locali
324 mvpdc mvpdiff locali
325 mvnsc mvnsd locali
326 mvpsc mvpsd locali
327 mvndic mvndiode locali
328 mvpdic mvpdiode locali
329
330 lic locali metal1
331 obslic obsli obsm1
332
333 via1 metal1 metal2
334 via2 metal2 metal3
335#ifdef METAL5
336 via3 metal3 metal4
337 via4 metal4 metal5
338#endif (METAL5)
339 stackable
340
341#ifdef METAL5
342#ifdef MIM
343 # MiM cap contacts are not stackable!
344 mimcc mimcap metal4
345 mim2cc mimcap2 metal5
346#endif (MIM)
347
348 padl m1 m2 m3 m4 m5 glass
349#else
350 padl m1 m2 m3 glass
351#endif (!METAL5)
352
353#ifdef REDISTRIBUTION
354 mrdlc metal5 mrdl
355#endif (REDISTRIBUTION)
356end
357
358#-----------------------------------------------------
359# Layer aliases
360#-----------------------------------------------------
361
362aliases
363
364 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]365 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]366
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]367 allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]368 allpfets pfet,ppu,scpfet,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]369 allfets allnfets,allpfets,varactor,mvvaractor,varhvt
370
371 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
372 allnactive allnactivenonfet,allnfets
373 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
374 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar
375
376 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
377 allpactive allpactivenonfet,allpfets
378 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
379 allpactivetap *psd,*mvpsd
380
381 allactivenonfet allnactivenonfet,allpactivenonfet
382 allactive allactivenonfet,allfets
383
384 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
385
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]386 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]387 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388 alldifflv allndifflv,allpdifflv
389 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
390 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
391 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
392
393 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
394 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
395 alldiffmv allndiffmv,allpdiffmv
396 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
397 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
398 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
399 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
400 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
401 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
402
403 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
404 alldiff alldifflv,alldiffmv
405
406 allpolyres mrp1,xhrpoly,uhrpoly,rmp
407 allpolynonfet *poly,allpolyres,xpc
408 allpolynonres *poly,allfets,xpc
409
410 allpoly allpolynonfet,allfets
411 allpolynoncap *poly,xpc,allfets,allpolyres
412
413 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
414 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
415 allndiffcontmv mvndc,mvnsc,mvndic
416 allpdiffcontmv mvpdc,mvpsc,mvpdic
417 allndiffcont allndiffcontlv,allndiffcontmv
418 allpdiffcont allpdiffcontlv,allpdiffcontmv
419 alldiffcontlv allndiffcontlv,allpdiffcontlv
420 alldiffcontmv allndiffcontmv,allpdiffcontmv
421 alldiffcont alldiffcontlv,alldiffcontmv
422
423 allcont alldiffcont,pc
424
425 allres allpolyres,allactiveres
426
427 allli *locali,coreli,rli
428 allm1 *m1,rm1
429 allm2 *m2,rm2
430 allm3 *m3,rm3
431#ifdef METAL5
432 allm4 *m4,rm4
433 allm5 *m5,rm5
434#endif (METAL5)
435
436 allpad padl
437
438 psub pwell
439
440end
441
442#-----------------------------------------------------
443# Layer drawing styles
444#-----------------------------------------------------
445
446styles
447 styletype mos
448 dnwell cwell
449 nwell nwell
450 pwell pwell
451 rpwell pwell ptransistor_stripes
452 ndiff ndiffusion
453 pdiff pdiffusion
454 nsd ndiff_in_nwell
455 psd pdiff_in_pwell
456 nfet ntransistor ntransistor_stripes
457 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]458 npass ntransistor ntransistor_stripes
459 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]460 pfet ptransistor ptransistor_stripes
461 scpfet ptransistor ptransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]462 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]463 var polysilicon ndiff_in_nwell
464 ndc ndiffusion metal1 contact_X'es
465 pdc pdiffusion metal1 contact_X'es
466 nsc ndiff_in_nwell metal1 contact_X'es
467 psc pdiff_in_pwell metal1 contact_X'es
468
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]469 pnp nwell ntransistor_stripes
470 npn pwell ptransistor_stripes
471 mvnpn pwell hvpdiff_mask
472
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]474 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]475 pfethvt ptransistor ptransistor_stripes implant2
476 nfetlvt ntransistor ntransistor_stripes implant1
477 nsonos ntransistor implant3
478 varhvt polysilicon ndiff_in_nwell implant2
479
480 mvndiff ndiffusion hvndiff_mask
481 mvpdiff pdiffusion hvpdiff_mask
482 mvnsd ndiff_in_nwell hvndiff_mask
483 mvpsd pdiff_in_pwell hvpdiff_mask
484 mvnfet ntransistor ntransistor_stripes hvndiff_mask
485 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
486 mvpfet ptransistor ptransistor_stripes
487 mvvar polysilicon ndiff_in_nwell hvndiff_mask
488 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
489 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
490 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
491 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
492
493 poly polysilicon
494 pc polysilicon metal1 contact_X'es
495 npolyres polysilicon silicide_block nselect2
496 ppolyres polysilicon silicide_block pselect2
497 xpc polysilicon pselect2 metal1 contact_X'es
498 rmp polysilicon poly_resist_stripes
499
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]500 res0p35 implant1
501 res0p69 implant1
502 res1p41 implant1
503 res2p85 implant1
504 res5p73 implant1
505
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]506 pdiode pdiffusion pselect2
507 ndiode ndiffusion nselect2
508 pdiodec pdiffusion pselect2 metal1 contact_X'es
509 ndiodec ndiffusion nselect2 metal1 contact_X'es
510
511 nndiode ndiffusion nselect2 implant3
512 ndiodelvt ndiffusion nselect2 implant1
513 pdiodelvt pdiffusion pselect2 implant1
514 pdiodehvt pdiffusion pselect2 implant2
515 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
516 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
517 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
518
519 mvpdiode pdiffusion pselect2 hvpdiff_mask
520 mvndiode ndiffusion nselect2 hvndiff_mask
521 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
522 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
523 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
524
525 locali metal1
526 coreli metal1
527 rli metal1 poly_resist_stripes
528 lic metal1 metal2 via1arrow
529 obsli metal1
530 obslic metal1 metal2 via1arrow
531
532 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]533 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]534 rm1 metal2 poly_resist_stripes
535 obsm1 metal2
536 m2c metal2 metal3 via2arrow
537 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]538 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]539 rm2 metal3 poly_resist_stripes
540 obsm2 metal3
541 m3c metal3 metal4 via3alt
542 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]543 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]544 rm3 metal4 poly_resist_stripes
545 obsm3 metal4
546#ifdef METAL5
547#ifdef MIM
548 mimcap metal3 mems
549 mimcc metal3 contact_X'es mems
550 mimcap2 metal4 mems
551 mim2cc metal4 contact_X'es mems
552#endif (MIM)
553 via3 metal4 metal5 via4
554 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]555 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]556 rm4 metal5 poly_resist_stripes
557 obsm4 metal5
558 via4 metal5 metal6 via5
559 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]560 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]561 rm5 metal6 poly_resist_stripes
562 obsm5 metal6
563#endif (METAL5)
564#ifdef REDISTRIBUTION
565 mrdlc metal6 metal7 via6
566 metalrdl metal7
567 obsmrdl metal7
568#endif (REDISTRIBUTION)
569
570 glass overglass
571 mrp1 poly_resist poly_resist_stripes
572 xhrpoly poly_resist silicide_block
573 uhrpoly poly_resist
574 ndiffres ndiffusion ndop_stripes
575 pdiffres pdiffusion pdop_stripes
576 mvndiffres ndiffusion hvndiff_mask ndop_stripes
577 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
578 comment comment
579 error_p error_waffle
580 error_s error_waffle
581 error_ps error_waffle
582 fillblock cwell
583
584 obswell cwell
585 obsactive implant4
586
587#ifndef METAL5
588 padl metal4 via4 overglass
589#else
590 padl metal6 via6 overglass
591#endif
592
593 magnet substrate_field_implant
594 rotate via3alt
595 fence via5
596end
597
598#-----------------------------------------------------
599# Special paint/erase rules
600#-----------------------------------------------------
601
602compose
603 compose nfet poly ndiff
604 compose pfet poly pdiff
605 compose var poly nsd
606
607 compose mvnfet poly mvndiff
608 compose mvpfet poly mvpdiff
609 compose mvvar poly mvnsd
610
611 paint ndc nwell pdc
612 paint nfet nwell pfet
613 paint scnfet nwell scpfet
614 paint ndiff nwell pdiff
615 paint psd nwell nsd
616 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]617 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]618
619 paint pdc pwell ndc
620 paint pfet pwell nfet
621 paint scpfet pwell scnfet
622 paint pdiff pwell ndiff
623 paint nsd pwell psd
624 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]625 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]626
627 paint pdc coreli pdc
628 paint ndc coreli ndc
629 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]630 paint nsc coreli nsc
631 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]632 paint viali coreli viali
633
634 paint coreli pdc pdc
635 paint coreli ndc ndc
636 paint coreli pc pc
637 paint coreli nsc nsc
638 paint coreli psc psc
639 paint coreli viali viali
640
641#ifdef METAL5
642 paint m4 obsm4 m4
643 paint m5 obsm5 m5
644#endif (METAL5)
645end
646
647#-----------------------------------------------------
648# Electrical connectivity
649#-----------------------------------------------------
650
651connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]652 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
653 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]654 *li,coreli *li,coreli
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]655 *m1,m1fill *m1,m1fill
656 *m2,m2fill *m2,m2fill
657 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]658#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]659 *m4,m4fill *m4,m4fill
660 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]661#ifdef MIM
662 *mimcap *mimcap
663 *mimcap2 *mimcap2
664#endif (MIM)
665#endif (METAL5)
666 allnactivenonfet allnactivenonfet
667 allpactivenonfet allpactivenonfet
668 *poly,xpc,allfets *poly,xpc,allfets
669#ifdef REDISTRIBUTION
670 # RDL connects to m5 (i.e., padl) through glass cut
671 *mrdl *mrdl
672 glass metrdl
673#endif (REDISTRIBUTION)
674end
675
676#-----------------------------------------------------
677# CIF/GDS output layer definitions
678#-----------------------------------------------------
679# NOTE: All values in this section MUST be multiples of 25
680# or else magic will scale below the allowed layout grid size
681
682cifoutput
683
684#----------------------------------------------------------------
685style gdsii
686# NOTE: This section is used for actual GDS output
687#----------------------------------------------------------------
688 scalefactor 10 nanometers
689 options calma-permissive-labels
690 gridlimit 5
691
692#----------------------------------------------------------------
693# Create a temp layer from the cell bounding box for use in
694# generating ID layers. Note that "boundary", unlike "bbox",
695# requires the FIXED_BBOX property (abutment box) in the cell.
696#----------------------------------------------------------------
697 templayer CELLBOUND
698 boundary
699
700#----------------------------------------------------------------
701# BOUND
702#----------------------------------------------------------------
703 layer BOUND CELLBOUND
704 calma 235 4
705
706# Create a boundary outside of an abutment box, so that layers
707# can be made to stretch to the abutment box edges. First strink
708# so that any box that would be so small as to interact with
709# itself will be removed.
710
711 templayer CELLRING CELLBOUND
712 shrink 345
713 grow 545
714 and-not CELLBOUND
715
716#----------------------------------------------------------------
717# DNWELL
718#----------------------------------------------------------------
719
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]720 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]721 calma 64 18
722
723 layer PWRES rpw
724 and dnwell
725 calma 64 13
726
727#----------------------------------------------------------------
728# NWELL
729#----------------------------------------------------------------
730
731 layer NWELL allnwell
732 bloat-all rpw dnwell
733 and-not rpw,pwell
734 calma 64 20
735
736 layer WELLTXT
737 labels allnwell noport
738 calma 64 16
739
740 layer WELLPIN
741 labels allnwell port
742 calma 64 5
743
744#----------------------------------------------------------------
745# SUB (text/port only)
746#----------------------------------------------------------------
747
748 layer SUBTXT
749 labels pwell noport
750 calma 122 16
751
752 layer SUBPIN
753 labels pwell port
754 calma 64 59
755
756#----------------------------------------------------------------
757# DIFF
758#----------------------------------------------------------------
759
760 layer DIFF allnactivenontap,allpactivenontap,allactiveres
761 labels allnactivenontap,allpactivenontap
762 calma 65 20
763
764#----------------------------------------------------------------
765# TAP
766#----------------------------------------------------------------
767
768 layer TAP allnactivetap,allpactivetap
769 labels allnactivetap,allpactivetap
770 calma 65 44
771
772#----------------------------------------------------------------
773# PPLUS, NPLUS (PSDM, NSDM)
774#----------------------------------------------------------------
775
776 templayer basePPLUS pdiffres,mvpdiffres
777 grow 15
778 or xhrpoly,uhrpoly,xpc
779 grow 110
780 bloat-or allpactivetap * 125 allnactivenontap 0
781 bloat-or allpactivenontap * 125 allnactivetap 0
782 bridge 380 380
783
784 templayer extendPPLUS basePPLUS,CELLRING
785 grow 185
786 shrink 185
787 and-not CELLRING
788
789 layer PPLUS basePPLUS,extendPPLUS
790 close 265000
791 calma 94 20
792
793 templayer baseNPLUS ndiffres,mvndiffres
794 grow 125
795 bloat-or allnactivetap * 125 allpactivenontap 0
796 bloat-or allnactivenontap * 125 allpactivetap 0
797 bridge 380 380
798
799 templayer extendNPLUS baseNPLUS,CELLRING
800 grow 185
801 shrink 185
802 and-not CELLRING
803
804 layer NPLUS baseNPLUS,extendNPLUS
805 close 265000
806 calma 93 44
807
808#----------------------------------------------------------------
809# LVTN
810#----------------------------------------------------------------
811
812 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
813 grow 180
814 bridge 380 380
815 grow 185
816 shrink 185
817 close 265000
818 calma 125 44
819
820#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]821# HVTR
822#----------------------------------------------------------------
823
824 layer HVTR pfetmvt
825 grow 180
826 bridge 380 380
827 grow 185
828 shrink 185
829 close 265000
830 calma 18 20
831
832#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]833# HVTP
834#----------------------------------------------------------------
835
836 layer HVTP pfethvt,varhvt,*pdiodehvt
837 grow 180
838 bridge 380 380
839 grow 185
840 shrink 185
841 close 265000
842 calma 78 44
843
844#----------------------------------------------------------------
845# SONOS
846#----------------------------------------------------------------
847
848 layer SONOS nsonos
849 grow 100
850 grow-min 410
851 bridge 500 410
852 grow 250
853 shrink 250
854 calma 80 20
855
856#----------------------------------------------------------------
857# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]858# coreli layer indicates a cell needing COREID. Also, devices
859# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]860#----------------------------------------------------------------
861
862 layer COREID
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]863 bloat-all nsonos,coreli,ppu,npd,npass CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]864 calma 81 2
865
866#----------------------------------------------------------------
867# STDCELL applies to all cells containing scnfet or scpfet.
868#----------------------------------------------------------------
869
870 layer STDCELL scnfet
871 bloat-all scpfet,scnfet CELLBOUND
872 calma 81 4
873
874#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]875# NPNID and PNPID apply to bipolar transistors
876#----------------------------------------------------------------
877
878 layer NPNID
879 bloat-all npn,mvnpn dnwell
880 calma 82 20
881
882 templayer pnparea pnp
883 grow 400
884
885 layer PNPID
886 bloat-all pnparea *psd
887 or pnparea
888 calma 82 44
889
890#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]891# RPM
892#----------------------------------------------------------------
893
894 layer RPM
895 bloat-all xhrpoly xpc
896 grow 200
897 grow-min 1270
898 grow 420
899 shrink 420
900 calma 86 20
901
902#----------------------------------------------------------------
903# URPM (2kOhms/sq. poly implant)
904#----------------------------------------------------------------
905
906 layer URPM
907 bloat-all uhrpoly xpc
908 grow 200
909 grow-min 1270
910 grow 420
911 shrink 420
912 calma 79 20
913
914#----------------------------------------------------------------
915# LDNTM (Tip implant for SONOS FETs)
916#----------------------------------------------------------------
917
918 layer LDNTM
919 bloat-all nsonos *ndiff
920 grow 185
921 grow 345
922 shrink 345
923 calma 11 44
924
925#----------------------------------------------------------------
926# HVNTM (Tip implant for MV ndiff devices)
927#----------------------------------------------------------------
928
929 templayer hvntm_block *mvpsd
930 grow 185
931
932 layer HVNTM
933 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
934 bloat-all mvvaractor *mvnsd
935 and-not hvntm_block
936 grow 185
937 grow 345
938 shrink 345
939 calma 125 20
940
941#----------------------------------------------------------------
942# POLY
943#----------------------------------------------------------------
944
945 layer POLY allpoly
946 calma 66 20
947
948 layer POLYTXT
949 labels allpoly noport
950 calma 66 16
951
952 layer POLYPIN
953 labels allpoly port
954 calma 66 5
955
956#----------------------------------------------------------------
957# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
958#----------------------------------------------------------------
959
960 templayer baseTHKOX *mvpsd
961 grow-min 470
962 or alldiffmv,mvvar
963 grow 185
964 bloat-all alldiffmv nwell
965 grow-min 600
966 bridge 700 600
967
968 templayer extendTHKOX baseTHKOX,CELLRING
969 grow 345
970 shrink 345
971 and-not CELLRING
972
973 layer THKOX baseTHKOX,extendTHKOX
974 calma 75 20
975
976#----------------------------------------------------------------
977# CONT (LICON)
978#----------------------------------------------------------------
979
980 layer CONT allcont
981 squares-grid 0 170 170
982 calma 66 44
983
984 # Contact for pres is different than other LICON contacts
985 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
986 templayer xpc_horiz xpc
987 shrink 1007
988 grow 1007
989
990 layer CONT xpc
991 and-not xpc_horiz
992 # Force long edge vertical for contacts narrower than 2um
993 # Minimum space is 350 but 520 satisfies no. of contacts rule
994 slots 80 190 520 80 2000 350
995 calma 66 44
996
997 layer CONT xpc
998 and xpc_horiz
999 # Force long edge vertical for contacts wider than 2um
1000 # Minimum space is 350 but 520 satisfies no. of contacts rule
1001 slots 80 2000 350 80 190 520
1002 calma 66 44
1003
1004#----------------------------------------------------------------
1005# NPC (Nitride poly cut)
1006# surrounds CONT (LICON) on poly only (i.e., pc)
1007#----------------------------------------------------------------
1008
1009 layer NPC pc
1010 squares-grid 0 170 170
1011 grow 100
1012 bridge 270 270
1013 grow 130
1014 shrink 130
1015 calma 95 20
1016
1017 # NPC is also generated on xhrpoly and uhrpoly resistors
1018
1019 layer NPC xpc,xhrpoly,uhrpoly
1020 # xpc surrounds precision_resistor by 0.095um
1021 grow 95
1022 grow 130
1023 shrink 130
1024 calma 95 20
1025
1026#----------------------------------------------------------------
1027# Device markers
1028#----------------------------------------------------------------
1029
1030 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1031 calma 65 13
1032
1033 layer POLYRES mrp1
1034 calma 66 13
1035
1036 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1037 layer POLYSHORT rmp
1038 calma 66 15
1039
1040 # POLYRES extends to edge of contact cut
1041 layer POLYRES xhrpoly,uhrpoly
1042 grow 60
1043 and xpc
1044 or xhrpoly,uhrpoly
1045 calma 66 13
1046
1047 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1048 # To be done: Expand to include anode, cathode, and guard ring
1049 calma 81 23
1050
1051#----------------------------------------------------------------
1052# LI
1053#----------------------------------------------------------------
1054 layer LI allli
1055 calma 67 20
1056
1057 layer LITXT
1058 labels *locali,coreli noport
1059 calma 67 16
1060
1061 layer LIPIN
1062 labels *locali,coreli port
1063 calma 67 5
1064
1065 layer LIRES rli
1066 labels rli
1067 calma 67 13
1068
1069#----------------------------------------------------------------
1070# MCON
1071#----------------------------------------------------------------
1072 layer MCON lic
1073 squares-grid 0 170 190
1074 calma 67 44
1075
1076#----------------------------------------------------------------
1077# MET1
1078#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1079 layer MET1 allm1,m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1080 calma 68 20
1081
1082 layer MET1TXT
1083 labels allm1 noport
1084 calma 68 16
1085
1086 layer MET1PIN
1087 labels allm1 port
1088 calma 68 5
1089
1090 layer MET1RES rm1
1091 labels rm1
1092 calma 68 13
1093
1094#----------------------------------------------------------------
1095# VIA1
1096#----------------------------------------------------------------
1097 layer VIA1 via1
1098 squares-grid 55 150 170
1099 calma 68 44
1100
1101#----------------------------------------------------------------
1102# MET2
1103#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1104 layer MET2 allm2,m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1105 calma 69 20
1106
1107 layer MET2TXT
1108 labels allm2 noport
1109 calma 69 16
1110
1111 layer MET2PIN
1112 labels allm2 port
1113 calma 69 5
1114
1115 layer MET2RES rm2
1116 labels rm2
1117 calma 69 13
1118
1119#----------------------------------------------------------------
1120# VIA2
1121#----------------------------------------------------------------
1122 layer VIA2 via2
1123 squares-grid 40 200 200
1124 calma 69 44
1125
1126#----------------------------------------------------------------
1127# MET3
1128#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1129 layer MET3 allm3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1130 calma 70 20
1131
1132 layer MET3TXT
1133 labels allm3 noport
1134 calma 70 16
1135
1136 layer MET3PIN
1137 labels allm3 port
1138 calma 70 5
1139
1140 layer MET3RES rm3
1141 labels rm3
1142 calma 70 13
1143
1144#ifdef METAL5
1145#----------------------------------------------------------------
1146# VIA3
1147#----------------------------------------------------------------
1148 layer VIA3 via3
1149#ifdef MIM
1150 or mimcc
1151#endif (MIM)
1152 squares-grid 60 200 200
1153 calma 70 44
1154
1155#----------------------------------------------------------------
1156# MET4
1157#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1158 layer MET4 allm4,m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1159 calma 71 20
1160
1161 layer MET4TXT
1162 labels allm4 noport
1163 calma 71 16
1164
1165 layer MET4PIN
1166 labels allm4 port
1167 calma 71 5
1168
1169 layer MET4RES rm4
1170 labels rm4
1171 calma 71 13
1172
1173#----------------------------------------------------------------
1174# VIA4
1175#----------------------------------------------------------------
1176 layer VIA4 via4
1177#ifdef MIM
1178 or mim2cc
1179#endif (MIM)
1180 squares-grid 190 800 800
1181 calma 71 44
1182
1183#----------------------------------------------------------------
1184# MET5
1185#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1186 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1187 calma 72 20
1188
1189 layer MET5TXT
1190 labels allm5 noport
1191 calma 72 16
1192
1193 layer MET5PIN
1194 labels allm5 port
1195 calma 72 5
1196
1197 layer MET5RES rm5
1198 labels rm5
1199 calma 72 13
1200
1201#endif (METAL5)
1202
1203#ifdef REDISTRIBUTION
1204#----------------------------------------------------------------
1205# RDL
1206#----------------------------------------------------------------
1207 layer RDL *metrdl
1208 calma 74 20
1209
1210 layer RDLTXT
1211 labels *metrdl noport
1212 calma 74 16
1213
1214 layer RDLPIN
1215 labels *metrdl port
1216 calma 74 5
1217
1218#endif REDISTRIBUTION
1219
1220#----------------------------------------------------------------
1221# GLASS
1222#----------------------------------------------------------------
1223 layer GLASS glass
1224 calma 76 20
1225
1226#ifdef MIM
1227#----------------------------------------------------------------
1228# CAPM
1229#----------------------------------------------------------------
1230 layer CAPM *mimcap
1231 labels mimcap
1232 calma 89 44
1233
1234 layer CAPM2 *mimcap2
1235 labels mimcap2
1236 calma 97 44
1237#endif (MIM)
1238
1239#----------------------------------------------------------------
1240# Chip top level marker for DRC latchup rules to check 15um
1241# distance to taps (otherwise 6um is used)
1242#----------------------------------------------------------------
1243
1244 layer LOWTAPDENSITY
1245 bbox top
1246 # Clear 200um for pads + 50um for required high tap density
1247 # in critical area.
1248 shrink 250000
1249 calma 81 14
1250
1251#----------------------------------------------------------------
1252# FILLBLOCK
1253#----------------------------------------------------------------
1254 layer FILLOBSM1 fillblock
1255 calma 62 24
1256
1257 layer FILLOBSM2 fillblock
1258 calma 105 52
1259
1260 layer FILLOBSM3 fillblock
1261 calma 107 24
1262
1263 layer FILLOBSM4 fillblock
1264 calma 112 4
1265
1266 render DNWELL cwell -0.1 0.1
1267 render NWELL nwell 0.0 0.2062
1268 render DIFF ndiffusion 0.2062 0.12
1269 render TAP pdiffusion 0.2062 0.12
1270 render POLY polysilicon 0.3262 0.18
1271 render CONT via 0.5062 0.43
1272 render LI metal1 0.9361 0.10
1273 render MCON via 1.0361 0.34
1274 render MET1 metal2 1.3761 0.36
1275 render VIA1 via 1.7361 0.27
1276 render MET2 metal3 2.0061 0.36
1277 render VIA2 via 2.3661 0.42
1278 render MET3 metal4 2.7861 0.845
1279#ifdef METAL5
1280 render VIA3 via 3.6311 0.39
1281 render MET4 metal5 4.0211 0.845
1282 render VIA4 via 4.8661 0.505
1283 render MET5 metal6 5.3711 1.26
1284 render CAPM metal8 2.4661 0.2
1285 render CAPM2 metal9 3.7311 0.2
1286#ifdef REDISTRIBUTION
1287 render RDL metal7 11.8834 4.0
1288#endif (!REDISTRIBUTION)
1289#endif (!METAL5)
1290
1291#----------------------------------------------------------------
1292style drc
1293#----------------------------------------------------------------
1294# NOTE: This style is used for DRC only, not for GDS output
1295#----------------------------------------------------------------
1296 scalefactor 10 nanometers
1297 options calma-permissive-labels
1298
1299 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1300 templayer dnwell_shrink dnwell
1301 shrink 1030
1302
1303 templayer nwell_missing dnwell
1304 grow 400
1305 and-not dnwell_shrink
1306 and-not nwell
1307
1308 # SONOS nFET devices must be in deep nwell
1309 templayer dnwell_missing nsonos
1310 and-not dnwell
1311
1312 # Define MiM cap bottom plate for spacing rule
1313 templayer mim_bottom
1314 bloat-all *mimcap *metal3
1315
1316 # Define MiM2 cap bottom plate for spacing rule
1317 templayer mim2_bottom
1318 bloat-all *mimcap2 *metal4
1319
1320 # Note that metal fill is performed by the foundry and so is not
1321 # an option for a cifoutput style.
1322
1323 # Check latchup rule (15um minimum from tap LICON center to any
1324 # non-tap diffusion. Note that to count as a tap, the diffusion
1325 # must be contacted to LI
1326
1327 templayer ptap_reach psc,mvpsc
1328 and-not dnwell
1329 # grow total is 15um. grow in 0.84um increments to ensure that
1330 # no nwell ring is crossed
1331 grow 840
1332 and-not nwell,dnwell
1333 grow 840
1334 and-not nwell,dnwell
1335 grow 840
1336 and-not nwell,dnwell
1337 grow 840
1338 and-not nwell,dnwell
1339 grow 840
1340 and-not nwell,dnwell
1341 grow 840
1342 and-not nwell,dnwell
1343 grow 840
1344 and-not nwell,dnwell
1345 grow 840
1346 and-not nwell,dnwell
1347 grow 840
1348 and-not nwell,dnwell
1349 grow 840
1350 and-not nwell,dnwell
1351 grow 840
1352 and-not nwell,dnwell
1353 grow 840
1354 and-not nwell,dnwell
1355 grow 840
1356 and-not nwell,dnwell
1357 grow 840
1358 and-not nwell,dnwell
1359 grow 840
1360 and-not nwell,dnwell
1361 grow 840
1362 and-not nwell,dnwell
1363 grow 840
1364 and-not nwell,dnwell
1365 grow 635
1366 and-not nwell,dnwell
1367
1368 templayer ptap_missing *ndiff,*mvndiff
1369 and-not dnwell
1370 and-not ptap_reach
1371
1372 templayer ntap_reach nsc,mvnsc
1373 # grow total is 15um. grow in 1.27um increments to ensure that
1374 # no nwell ring is crossed. There is no difference between
1375 # ntaps in and out of deep nwell.
1376 grow 1270
1377 and nwell
1378 grow 1270
1379 and nwell
1380 grow 1270
1381 and nwell
1382 grow 1270
1383 and nwell
1384 grow 1270
1385 and nwell
1386 grow 1270
1387 and nwell
1388 grow 1270
1389 and nwell
1390 grow 1270
1391 and nwell
1392 grow 1270
1393 and nwell
1394 grow 1270
1395 and nwell
1396 grow 1270
1397 and nwell
1398 grow 945
1399 and nwell
1400
1401 templayer ntap_missing *pdiff,*mvpdiff
1402 and-not dnwell
1403 and-not ntap_reach
1404
1405 templayer dptap_reach psc,mvpsc
1406 and dnwell
1407 grow 840
1408 and-not nwell
1409 and dnwell
1410 grow 840
1411 and-not nwell
1412 and dnwell
1413 grow 840
1414 and-not nwell
1415 and dnwell
1416 grow 840
1417 and-not nwell
1418 and dnwell
1419 grow 840
1420 and-not nwell
1421 and dnwell
1422 grow 840
1423 and-not nwell
1424 and dnwell
1425 grow 840
1426 and-not nwell
1427 and dnwell
1428 grow 840
1429 and-not nwell
1430 and dnwell
1431 grow 840
1432 and-not nwell
1433 and dnwell
1434 grow 840
1435 and-not nwell
1436 and dnwell
1437 grow 840
1438 and-not nwell
1439 and dnwell
1440 grow 840
1441 and-not nwell
1442 and dnwell
1443 grow 840
1444 and-not nwell
1445 and dnwell
1446 grow 840
1447 and-not nwell
1448 and dnwell
1449 grow 840
1450 and-not nwell
1451 and dnwell
1452 grow 840
1453 and-not nwell
1454 and dnwell
1455 grow 840
1456 and-not nwell
1457 and dnwell
1458 grow 635
1459 and-not nwell
1460 and dnwell
1461
1462 templayer dptap_missing *ndiff,*mvndiff
1463 and dnwell
1464 and-not dptap_reach
1465
1466 templayer m1_small_hole *m1
1467 close 140000
1468
1469 templayer m1_hole_empty m1_small_hole
1470 and-not *m1
1471
1472 templayer m2_small_hole *m2
1473 close 140000
1474
1475 templayer m2_hole_empty m2_small_hole
1476 and-not *m2
1477
1478#ifdef EXPERIMENTAL
1479#----------------------------------------------------------------
1480style paint
1481#----------------------------------------------------------------
1482# NOTE: This style is used for database manipulations only via
1483# the "cif paint" command.
1484#----------------------------------------------------------------
1485
1486 scalefactor 10 nanometers
1487
1488 templayer m1grow *m1
1489 grow 290
1490
1491 # layer listrap: Use the following set of commands to strap local
1492 # interconnect wires with metal1 (inside the cursor box) to satisfy
1493 # the maximum aspect ratio rule for local interconnect:
1494 #
1495 # tech unlock *
1496 # cif ostyle paint
1497 # cif paint m1strap comment
1498 # cif paint m1strap m1
1499 # cif paint listrap licon
1500 # erase comment
1501
1502 templayer m1strap *li
1503 and-not m1grow
1504 grow 30
1505
1506 templayer listrap comment
1507 slots 30 170 170 60
1508
1509#endif (EXPERIMENTAL)
1510
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1511#----------------------------------------------------------------
1512style wafflefill
1513#----------------------------------------------------------------
1514# Style used by scripts for automatically generating fill layers
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1515#----------------------------------------------------------------
1516 scalefactor 10 nanometers
1517 options calma-permissive-labels
1518 gridlimit 5
1519
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1520#----------------------------------------------------------------
1521# Generate guard-band around nwells to keep FOM from crossing
1522# Spacing from nwell = Diff/Tap 9 = 0.34um
1523# Enclosure by nwell = Diff/Tap 8 = 0.18um
1524#----------------------------------------------------------------
1525 templayer well_shrink nwell
1526 shrink 180
1527 templayer well_guardband nwell
1528 grow 340
1529 and-not well_shrink
1530
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1531#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1532# Interleaved FOM and POLY fill
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1533#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1534 templayer slots_fom_pass1
1535 bbox top
1536 slots 0 4080 1320 0 4080 1320 1360 0
1537 templayer obstruct_fom_pass1 alldiff,allpoly,rpw
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1538 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1539 or well_guardband
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1540 templayer fomfill_pass1 slots_fom_pass1
1541 and-not obstruct_fom_pass1
1542 shrink 2035
1543 grow 2035
1544
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1545#---------------------------------------------------
1546
1547 templayer slots_poly_pass1
1548 bbox top
1549 slots 0 720 360 0 720 360 240 0
1550 templayer obstruct_poly_pass1 alldiff,allpoly,rpw
1551 grow 700
1552 or fomfill_pass1
1553 grow 300
1554 or well_guardband
1555 templayer polyfill_pass1 slots_poly_pass1
1556 and-not obstruct_poly_pass1
1557 shrink 355
1558 grow 355
1559
1560#---------------------------------------------------
1561
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1562 templayer slots_fom_pass2
1563 bbox top
1564 slots 0 2500 1320 0 2500 1320 1360 0
1565 templayer obstruct_fom_pass2 fomfill_pass1
1566 grow 820
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1567 grow 200
1568 or polyfill_pass1
1569 grow 300
1570 or obstruct_fom_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1571 templayer fomfill_pass2 slots_fom_pass2
1572 and-not obstruct_fom_pass2
1573 shrink 1245
1574 grow 1245
1575
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1576#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1577
1578 templayer slots_poly_coarse
1579 bbox top
1580 slots 0 720 360 0 720 360 240 120
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1581 templayer obstruct_poly_coarse polyfill_pass1
1582 grow 60
1583 or fomfill_pass1,fomfill_pass2
1584 grow 300
1585 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1586 templayer polyfill_coarse slots_poly_coarse
1587 and-not obstruct_poly_coarse
1588 shrink 355
1589 grow 355
1590
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1591#---------------------------------------------------
1592
1593 templayer slots_fom_coarse
1594 bbox top
1595 slots 0 1500 1320 0 1500 1320 1360 0
1596 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1597 grow 1020
1598 or polyfill_pass1,polyfill_coarse
1599 grow 300
1600 or obstruct_fom_pass1
1601 templayer fomfill_coarse slots_fom_coarse
1602 and-not obstruct_fom_coarse
1603 shrink 745
1604 grow 745
1605
1606#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1607 templayer slots_poly_medium
1608 bbox top
1609 slots 0 540 360 0 540 360 240 100
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1610 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
1611 grow 1010
1612 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1613 templayer polyfill_medium slots_poly_medium
1614 and-not obstruct_poly_medium
1615 shrink 265
1616 grow 265
1617
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1618#---------------------------------------------------
1619
1620 templayer slots_fom_fine
1621 bbox top
1622 slots 0 500 400 0 500 400 160 0
1623 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1624 grow 1320
1625 or obstruct_fom_pass1
1626 templayer fomfill_fine slots_fom_fine
1627 and-not obstruct_fom_fine
1628 shrink 245
1629 grow 245
1630
1631#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1632 templayer slots_poly_fine
1633 bbox top
1634 slots 0 480 360 0 480 360 240 200
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1635 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1636 grow 650
1637 or polyfill_pass1,polyfill_coarse,polyfill_medium
1638 grow 360
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1639 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1640 templayer polyfill_fine slots_poly_fine
1641 and-not obstruct_poly_fine
1642 shrink 235
1643 grow 235
1644
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1645#---------------------------------------------------
1646 templayer fomfill fomfill_pass1
1647 or fomfill_pass2
1648 or fomfill_coarse
1649 or fomfill_fine
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1650
1651 templayer polyfill polyfill_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1652 or polyfill_coarse
1653 or polyfill_medium
1654 or polyfill_fine
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1655
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1656 layer FOMMASK fomfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1657 calma 23 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1658 layer POLYMASK polyfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1659 calma 28 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1660
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1661#---------------------------------------------------
1662# MET1 fill
1663#---------------------------------------------------
1664 templayer slots_m1_coarse
1665 bbox top
1666 slots 0 2000 200 0 2000 200 700 0
1667 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
1668 grow 3000
1669 templayer met1fill_coarse slots_m1_coarse
1670 and-not obstruct_m1_coarse
1671 shrink 995
1672 grow 995
1673
1674 templayer slots_m1_medium
1675 bbox top
1676 slots 0 1000 200 0 1000 200 700 0
1677 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
1678 grow 2800
1679 or met1fill_coarse
1680 grow 200
1681 templayer met1fill_medium slots_m1_medium
1682 and-not obstruct_m1_medium
1683 shrink 495
1684 grow 495
1685
1686 templayer slots_m1_fine
1687 bbox top
1688 slots 0 580 200 0 580 200 700 0
1689 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
1690 grow 300
1691 or met1fill_coarse,met1fill_medium
1692 grow 200
1693 templayer met1fill_fine slots_m1_fine
1694 and-not obstruct_m1_fine
1695 shrink 285
1696 grow 285
1697
1698 templayer slots_m1_veryfine
1699 bbox top
1700 slots 0 300 200 0 300 200 100 50
1701 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
1702 grow 100
1703 or met1fill_coarse,met1fill_medium,met1fill_fine
1704 grow 200
1705 templayer met1fill_veryfine slots_m1_veryfine
1706 and-not obstruct_m1_veryfine
1707 shrink 145
1708 grow 145
1709
1710 layer MET1MASK met1fill_coarse
1711 or met1fill_medium
1712 or met1fill_fine
1713 or met1fill_veryfine
1714 calma 36 0
1715
1716#---------------------------------------------------
1717# MET2 fill
1718#---------------------------------------------------
1719 templayer slots_m2_coarse
1720 bbox top
1721 slots 0 2000 200 0 2000 200 700 350
1722 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
1723 grow 3000
1724 templayer met2fill_coarse slots_m2_coarse
1725 and-not obstruct_m2
1726 shrink 995
1727 grow 995
1728
1729 templayer slots_m2_medium
1730 bbox top
1731 slots 0 1000 200 0 1000 200 700 350
1732 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
1733 grow 2800
1734 or met2fill_coarse
1735 grow 200
1736 templayer met2fill_medium slots_m2_medium
1737 and-not obstruct_m2_medium
1738 shrink 495
1739 grow 495
1740
1741 templayer slots_m2_fine
1742 bbox top
1743 slots 0 580 200 0 580 200 700 350
1744 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
1745 grow 300
1746 or met2fill_coarse,met2fill_medium
1747 grow 200
1748 templayer met2fill_fine slots_m2_fine
1749 and-not obstruct_m2_fine
1750 shrink 285
1751 grow 285
1752
1753 templayer slots_m2_veryfine
1754 bbox top
1755 slots 0 300 200 0 300 200 100 100
1756 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
1757 grow 100
1758 or met2fill_coarse,met2fill_medium,met2fill_fine
1759 grow 200
1760 templayer met2fill_veryfine slots_m2_veryfine
1761 and-not obstruct_m2_veryfine
1762 shrink 145
1763 grow 145
1764
1765 layer MET2MASK met2fill_coarse
1766 or met2fill_medium
1767 or met2fill_fine
1768 or met2fill_veryfine
1769 calma 41 0
1770
1771#---------------------------------------------------
1772# MET3 fill
1773#---------------------------------------------------
1774 templayer slots_m3_coarse
1775 bbox top
1776 slots 0 2000 300 0 2000 300 700 700
1777 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
1778 grow 3000
1779 templayer met3fill_coarse slots_m3_coarse
1780 and-not obstruct_m3
1781 shrink 995
1782 grow 995
1783
1784 templayer slots_m3_medium
1785 bbox top
1786 slots 0 1000 300 0 1000 300 700 700
1787 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
1788 grow 2700
1789 or met3fill_coarse
1790 grow 300
1791 templayer met3fill_medium slots_m3_medium
1792 and-not obstruct_m3_medium
1793 shrink 495
1794 grow 495
1795
1796 templayer slots_m3_fine
1797 bbox top
1798 slots 0 580 300 0 580 300 700 700
1799 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
1800 grow 200
1801 or met3fill_coarse,met3fill_medium
1802 grow 300
1803 templayer met3fill_fine slots_m3_fine
1804 and-not obstruct_m3_fine
1805 shrink 285
1806 grow 285
1807
1808 templayer slots_m3_veryfine
1809 bbox top
1810 slots 0 400 300 0 400 300 150 200
1811 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
1812 or met3fill_coarse,met3fill_medium,met3fill_fine
1813 grow 300
1814 templayer met3fill_veryfine slots_m3_veryfine
1815 and-not obstruct_m3_veryfine
1816 shrink 195
1817 grow 195
1818
1819 layer MET3MASK met3fill_coarse
1820 or met3fill_medium
1821 or met3fill_fine
1822 or met3fill_veryfine
1823 calma 34 0
1824
1825#ifdef METAL5
1826#---------------------------------------------------
1827# MET4 fill
1828#---------------------------------------------------
1829 templayer slots_m4_coarse
1830 bbox top
1831 slots 0 2000 300 0 2000 300 700 1050
1832 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
1833 grow 3000
1834 templayer met4fill_coarse slots_m4_coarse
1835 and-not obstruct_m4
1836 shrink 995
1837 grow 995
1838
1839 templayer slots_m4_medium
1840 bbox top
1841 slots 0 1000 300 0 1000 300 700 1050
1842 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
1843 grow 2700
1844 or met4fill_coarse
1845 grow 300
1846 templayer met4fill_medium slots_m4_medium
1847 and-not obstruct_m4_medium
1848 shrink 495
1849 grow 495
1850
1851 templayer slots_m4_fine
1852 bbox top
1853 slots 0 580 300 0 580 300 700 1050
1854 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
1855 grow 200
1856 or met4fill_coarse,met4fill_medium
1857 grow 300
1858 templayer met4fill_fine slots_m4_fine
1859 and-not obstruct_m4_fine
1860 shrink 285
1861 grow 285
1862
1863 templayer slots_m4_veryfine
1864 bbox top
1865 slots 0 400 300 0 400 300 150 300
1866 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
1867 or met4fill_coarse,met4fill_medium,met4fill_fine
1868 grow 300
1869 templayer met4fill_veryfine slots_m4_veryfine
1870 and-not obstruct_m4_veryfine
1871 shrink 195
1872 grow 195
1873
1874 layer MET4MASK met4fill_coarse
1875 or met4fill_medium
1876 or met4fill_fine
1877 or met4fill_veryfine
1878 calma 51 0
1879
1880#---------------------------------------------------
1881# MET5 fill
1882#---------------------------------------------------
1883 templayer slots_m5
1884 bbox top
1885 slots 0 3000 1600 0 3000 1600 1000 100
1886 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
1887 grow 3000
1888 templayer met5fill_gen slots_m5
1889 and-not obstruct_m5
1890 shrink 1495
1891 grow 1495
1892
1893 layer MET5MASK met5fill_gen
1894 calma 59 0
1895#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1896
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1897end
1898
1899#-----------------------------------------------------------------------
1900cifinput
1901#-----------------------------------------------------------------------
1902# NOTE: All values in this section MUST be multiples of 25
1903# or else magic will scale below the allowed layout grid size
1904#-----------------------------------------------------------------------
1905
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]1906style sky130
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1907 scalefactor 10 nanometers
1908 gridlimit 5
1909
1910 options ignore-unknown-layer-labels no-reconnect-labels
1911
1912#ifndef MIM
1913 ignore CAPM
1914 ignore CAPM2
1915#endif (!MIM)
1916#ifndef METAL5
1917 ignore MET4,VIA3
1918 ignore MET5,VIA4
1919#endif
1920 ignore NPC
1921 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1922 ignore CAPID
1923 ignore LDNTM
1924 ignore HVNTM
1925 ignore POLYMOD
1926 ignore LOWTAPDENSITY
1927
1928 layer nwell NWELL,WELLTXT,WELLPIN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1929 and-not PNPID
1930 labels NWELL
1931 labels WELLTXT text
1932 labels WELLPIN port
1933
1934 layer pnp NWELL,WELLTXT,WELLPIN
1935 and PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1936 labels NWELL
1937 labels WELLTXT text
1938 labels WELLPIN port
1939
1940 layer pwell SUBTXT,SUBPIN
1941 labels SUBTXT text
1942 labels SUBPIN port
1943
1944 layer dnwell DNWELL
1945 labels DNWELL
1946
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1947 layer npn DNWELL
1948 and-not NWELL
1949 and NPNID
1950
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1951 layer rpw PWRES
1952 and DNWELL
1953 labels PWRES
1954
1955 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
1956 and-not POLY
1957 and-not NWELL
1958 and-not PPLUS
1959 and-not DIODE
1960 and-not DIFFRES
1961 and-not THKOX
1962 and NPLUS
1963 copyup ndifcheck
1964 labels DIFF
1965 labels DIFFTXT text
1966 labels DIFFPIN port
1967 labels TAPPIN port
1968
1969 layer ndiff ndiffarea
1970
1971 # Copy ndiff areas up for contact checks
1972 templayer xndifcheck ndifcheck
1973 copyup ndifcheck
1974
1975 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
1976 and-not POLY
1977 and-not NWELL
1978 and-not PPLUS
1979 and-not DIODE
1980 and-not DIFFRES
1981 and THKOX
1982 and NPLUS
1983 copyup ndifcheck
1984 labels DIFF
1985 labels DIFFTXT text
1986 labels DIFFPIN port
1987
1988 layer mvndiff mvndiffarea
1989
1990 # Copy ndiff areas up for contact checks
1991 templayer mvxndifcheck mvndifcheck
1992 copyup mvndifcheck
1993
1994 layer ndiode DIFF
1995 and NPLUS
1996 and DIODE
1997 and-not NWELL
1998 and-not POLY
1999 and-not PPLUS
2000 and-not THKOX
2001 and-not LVTN
2002 labels DIFF
2003
2004 layer ndiodelvt DIFF
2005 and NPLUS
2006 and DIODE
2007 and-not NWELL
2008 and-not POLY
2009 and-not PPLUS
2010 and-not THKOX
2011 and LVTN
2012 labels DIFF
2013
2014 templayer ndiodearea DIODE
2015 and NPLUS
2016 and-not THKOX
2017 and-not NWELL
2018 copyup DIODE,NPLUS
2019
2020 layer ndiffres DIFFRES
2021 and NPLUS
2022 and-not THKOX
2023 labels DIFF
2024
2025 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2026 and-not POLY
2027 and NWELL
2028 and-not NPLUS
2029 and-not DIODE
2030 and-not THKOX
2031 and PPLUS
2032 copyup pdifcheck
2033 labels DIFF
2034 labels DIFFTXT text
2035 labels DIFFPIN port
2036
2037 layer pdiff pdiffarea
2038
2039 layer mvndiode DIFF
2040 and NPLUS
2041 and DIODE
2042 and THKOX
2043 and-not POLY
2044 and-not PPLUS
2045 and-not LVTN
2046 labels DIFF
2047
2048 layer nndiode DIFF
2049 and NPLUS
2050 and DIODE
2051 and THKOX
2052 and-not POLY
2053 and-not PPLUS
2054 and LVTN
2055 labels DIFF
2056
2057 templayer mvndiodearea DIODE
2058 and NPLUS
2059 and THKOX
2060 and-not NWELL
2061 copyup DIODE,NPLUS
2062
2063 layer mvndiffres DIFFRES
2064 and NPLUS
2065 and THKOX
2066 labels DIFF
2067
2068 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2069 and-not POLY
2070 and NWELL
2071 and-not NPLUS
2072 and THKOX
2073 and-not DIODE
2074 and-not DIFFRES
2075 and PPLUS
2076 copyup mvpdifcheck
2077 labels DIFF
2078 labels DIFFTXT text
2079 labels DIFFPIN port
2080
2081 layer mvpdiff mvpdiffarea
2082
2083 # Copy pdiff areas up for contact checks
2084 templayer xpdifcheck pdifcheck
2085 copyup pdifcheck
2086
2087 layer pdiode DIFF
2088 and PPLUS
2089 and-not POLY
2090 and-not NPLUS
2091 and-not THKOX
2092 and-not LVTN
2093 and-not HVTP
2094 and DIODE
2095 labels DIFF
2096
2097 layer pdiodelvt DIFF
2098 and PPLUS
2099 and-not POLY
2100 and-not NPLUS
2101 and-not THKOX
2102 and LVTN
2103 and-not HVTP
2104 and DIODE
2105 labels DIFF
2106
2107 layer pdiodehvt DIFF
2108 and PPLUS
2109 and-not POLY
2110 and-not NPLUS
2111 and-not THKOX
2112 and-not LVTN
2113 and HVTP
2114 and DIODE
2115 labels DIFF
2116
2117 templayer pdiodearea DIODE
2118 and PPLUS
2119 and-not THKOX
2120 copyup DIODE,PPLUS
2121
2122 # Define pfet areas as known pdiff, regardless of the presence of a well.
2123
2124 templayer pfetarea DIFF
2125 and-not NPLUS
2126 and-not THKOX
2127 and POLY
2128
2129 layer pfet pfetarea
2130 and-not LVTN
2131 and-not HVTP
2132 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2133 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2134 labels DIFF
2135
2136 layer scpfet pfetarea
2137 and-not LVTN
2138 and-not HVTP
2139 and STDCELL
2140 labels DIFF
2141
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2142 layer ppu pfetarea
2143 and-not LVTN
2144 and-not HVTP
2145 and COREID
2146 labels DIFF
2147
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2148 layer pfetlvt pfetarea
2149 and LVTN
2150 labels DIFF
2151
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2152 layer pfetmvt pfetarea
2153 and HVTR
2154 labels DIFF
2155
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2156 layer pfethvt pfetarea
2157 and HVTP
2158 labels DIFF
2159
2160 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2161 layer nwell pfetarea
2162 grow 180
2163
2164 # Copy mvpdiff areas up for contact checks
2165 templayer mvxpdifcheck mvpdifcheck
2166 copyup mvpdifcheck
2167
2168 layer mvpdiode DIFF
2169 and PPLUS
2170 and-not POLY
2171 and-not NPLUS
2172 and THKOX
2173 and DIODE
2174 labels DIFF
2175
2176 templayer mvpdiodearea DIODE
2177 and PPLUS
2178 and THKOX
2179 copyup DIODE,PPLUS
2180
2181 # Define pfet areas as known pdiff,
2182 # regardless of the presence of a
2183 # well.
2184
2185 templayer mvpfetarea DIFF
2186 and-not NPLUS
2187 and THKOX
2188 and POLY
2189
2190 layer mvpfet mvpfetarea
2191 labels DIFF
2192
2193 layer pdiff DIFF,DIFFTXT,DIFFPIN
2194 and-not NPLUS
2195 and-not POLY
2196 and-not THKOX
2197 and-not DIODE
2198 and-not DIFFRES
2199 labels DIFF
2200 labels DIFFTXT text
2201 labels DIFFPIN port
2202
2203 layer pdiffres DIFFRES
2204 and PPLUS
2205 and NWELL
2206 and-not THKOX
2207 labels DIFF
2208
2209 layer nfet DIFF
2210 and POLY
2211 and-not PPLUS
2212 and NPLUS
2213 and-not THKOX
2214 and-not LVTN
2215 and-not SONOS
2216 and-not STDCELL
2217 labels DIFF
2218
2219 layer scnfet DIFF
2220 and POLY
2221 and-not PPLUS
2222 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2223 and-not NWELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2224 and-not THKOX
2225 and-not LVTN
2226 and-not SONOS
2227 and STDCELL
2228 labels DIFF
2229
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2230 layer npd DIFF
2231 and POLY
2232 and-not PPLUS
2233 and NPLUS
2234 and-not NWELL
2235 and COREID
2236 labels DIFF
2237
2238 # layer npass DIFF
2239 # and POLY
2240 # and-not PPLUS
2241 # and NPLUS
2242 # and-not NWELL
2243 # and COREID
2244 # labels DIFF
2245
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2246 layer nfetlvt DIFF
2247 and POLY
2248 and-not PPLUS
2249 and NPLUS
2250 and-not THKOX
2251 and LVTN
2252 and-not SONOS
2253 labels DIFF
2254
2255 layer nsonos DIFF
2256 and POLY
2257 and-not PPLUS
2258 and NPLUS
2259 and-not THKOX
2260 and LVTN
2261 and SONOS
2262 labels DIFF
2263
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2264 templayer nsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2265 and NPLUS
2266 and NWELL
2267 and-not POLY
2268 and-not PPLUS
2269 and-not THKOX
2270 copyup nsubcheck
2271
2272 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2273 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2274
2275 layer nsd TAP,TAPPIN
2276 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2277 and-not POLY
2278 and-not THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2279 labels TAP
2280 labels TAPPIN port
2281
2282 templayer nsdexpand nsdarea
2283 grow 500
2284
2285 # Copy nsub areas up for contact checks
2286 templayer xnsubcheck nsubcheck
2287 copyup nsubcheck
2288
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2289 templayer psdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2290 and PPLUS
2291 and-not NWELL
2292 and-not POLY
2293 and-not NPLUS
2294 and-not THKOX
2295 and-not pfetexpand
2296 copyup psubcheck
2297
2298 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2299 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2300
2301 layer psd TAP,TAPPIN
2302 and PPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2303 and-not POLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2304 and-not THKOX
2305 labels TAP
2306 labels TAPPIN port
2307
2308 templayer psdexpand psdarea
2309 grow 500
2310
2311 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
2312 and-not NPLUS
2313 and-not POLY
2314 and THKOX
2315 and mvpfetexpand
2316 labels DIFF
2317 labels DIFFTXT text
2318 labels DIFFPIN port
2319
2320 layer mvpdiffres DIFFRES
2321 and PPLUS
2322 and NWELL
2323 and THKOX
2324 and-not mvrdpioedge
2325 labels DIFF
2326
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2327 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2328 and POLY
2329 and-not PPLUS
2330 and NPLUS
2331 and-not LVTN
2332 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2333 grow 1000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2334
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2335 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2336 and POLY
2337 and-not PPLUS
2338 and NPLUS
2339 and LVTN
2340 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2341 and-not mvnfetarea
2342
2343 layer mvnfet DIFF
2344 and POLY
2345 and-not PPLUS
2346 and NPLUS
2347 and THKOX
2348 and-not mvnnfetarea
2349 labels DIFF
2350
2351 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2352 labels DIFF
2353
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2354 templayer mvnsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2355 and NPLUS
2356 and NWELL
2357 and-not POLY
2358 and-not PPLUS
2359 and THKOX
2360 copyup mvnsubcheck
2361
2362 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2363 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2364
2365 layer mvnsd TAP,TAPPIN
2366 and NPLUS
2367 and THKOX
2368 labels TAP
2369 labels TAPPIN port
2370
2371 templayer mvnsdexpand mvnsdarea
2372 grow 500
2373
2374 # Copy nsub areas up for contact checks
2375 templayer mvxnsubcheck mvnsubcheck
2376 copyup mvnsubcheck
2377
2378 templayer mvpsdarea DIFF
2379 and PPLUS
2380 and-not NWELL
2381 and-not POLY
2382 and-not NPLUS
2383 and THKOX
2384 and-not mvpfetexpand
2385 copyup mvpsubcheck
2386
2387 layer mvpsd mvpsdarea
2388 labels DIFF
2389
2390 layer mvpsd TAP,TAPPIN
2391 and PPLUS
2392 and THKOX
2393 labels TAP
2394 labels TAPPIN port
2395
2396 templayer mvpsdexpand mvpsdarea
2397 grow 500
2398
2399 # Copy psub areas up for contact checks
2400 templayer xpsubcheck psubcheck
2401 copyup psubcheck
2402
2403 templayer mvxpsubcheck mvpsubcheck
2404 copyup mvpsubcheck
2405
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2406 layer psd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2407 and-not PPLUS
2408 and-not NPLUS
2409 and-not POLY
2410 and-not THKOX
2411 and-not pfetexpand
2412 and psdexpand
2413
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2414 layer nsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2415 and-not PPLUS
2416 and-not NPLUS
2417 and-not POLY
2418 and-not THKOX
2419 and nsdexpand
2420
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2421 layer mvpsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2422 and-not PPLUS
2423 and-not NPLUS
2424 and-not POLY
2425 and THKOX
2426 and-not mvpfetexpand
2427 and mvpsdexpand
2428
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2429 layer mvnsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2430 and-not PPLUS
2431 and-not NPLUS
2432 and-not POLY
2433 and THKOX
2434 and mvnsdexpand
2435
2436 templayer hresarea POLY
2437 and RPM
2438 grow 3000
2439
2440 templayer uresarea POLY
2441 and URPM
2442 grow 3000
2443
2444 templayer diffresarea DIFFRES
2445 and-not THKOX
2446 grow 3000
2447
2448 templayer mvdiffresarea DIFFRES
2449 and THKOX
2450 grow 3000
2451
2452 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2453
2454 layer pfet POLY
2455 and DIFF
2456 and diffresarea
2457 and-not NPLUS
2458 and-not STDCELL
2459
2460 layer scpfet POLY
2461 and DIFF
2462 and diffresarea
2463 and-not NPLUS
2464 and STDCELL
2465
2466 templayer xpolyterm RPM,URPM
2467 and POLY
2468 and-not POLYRES
2469 # add back the 0.06um contact surround in the direction of the resistor
2470 grow 60
2471 and POLY
2472
2473 layer xpc xpolyterm
2474
2475 templayer polyarea POLY
2476 and-not POLYRES
2477 and-not POLYSHORT
2478 and-not DIFF
2479 and-not RPM
2480 and-not URPM
2481 copyup polycheck
2482
2483 layer poly polyarea,POLYTXT,POLYPIN
2484 labels POLY
2485 labels POLYTXT text
2486 labels POLYPIN port
2487
2488 # Copy (non-resistor) poly areas up for contact checks
2489 templayer xpolycheck polycheck
2490 copyup polycheck
2491
2492 layer mrp1 POLY
2493 and POLYRES
2494 and-not RPM
2495 and-not URPM
2496 labels POLY
2497
2498 layer rmp POLY
2499 and POLYSHORT
2500 labels POLY
2501
2502 layer xhrpoly POLY
2503 and POLYRES
2504 and RPM
2505 and-not URPM
2506 and PPLUS
2507 and NPC
2508 and-not xpolyterm
2509 labels POLY
2510
2511 layer uhrpoly POLY
2512 and POLYRES
2513 and URPM
2514 and-not RPM
2515 and NPC
2516 and-not xpolyterm
2517 labels POLY
2518
2519 templayer ndcbase CONT
2520 and DIFF
2521 and NPLUS
2522 and-not NWELL
2523 and LI
2524 and-not THKOX
2525
2526 layer ndc ndcbase
2527 grow 85
2528 shrink 85
2529 shrink 85
2530 grow 85
2531 or ndcbase
2532 labels CONT
2533
2534 templayer nscbase CONT
2535 and DIFF,TAP
2536 and NPLUS
2537 and NWELL
2538 and LI
2539 and-not THKOX
2540
2541 layer nsc nscbase
2542 grow 85
2543 shrink 85
2544 shrink 85
2545 grow 85
2546 or nscbase
2547 labels CONT
2548
2549 templayer pdcbase CONT
2550 and DIFF
2551 and PPLUS
2552 and NWELL
2553 and LI
2554 and-not THKOX
2555
2556 layer pdc pdcbase
2557 grow 85
2558 shrink 85
2559 shrink 85
2560 grow 85
2561 or pdcbase
2562 labels CONT
2563
2564 templayer pdcnowell CONT
2565 and DIFF
2566 and PPLUS
2567 and pfetexpand
2568 and LI
2569 and-not THKOX
2570
2571 layer pdc pdcnowell
2572 grow 85
2573 shrink 85
2574 shrink 85
2575 grow 85
2576 or pdcnowell
2577 labels CONT
2578
2579 templayer pscbase CONT
2580 and DIFF,TAP
2581 and PPLUS
2582 and-not NWELL
2583 and-not pfetexpand
2584 and LI
2585 and-not THKOX
2586
2587 layer psc pscbase
2588 grow 85
2589 shrink 85
2590 shrink 85
2591 grow 85
2592 or pscbase
2593 labels CONT
2594
2595 templayer pcbase CONT
2596 and POLY
2597 and-not DIFF
2598 and-not RPM,URPM
2599 and LI
2600
2601 layer pc pcbase
2602 grow 85
2603 shrink 85
2604 shrink 85
2605 grow 85
2606 or pcbase
2607 labels CONT
2608
2609 templayer ndicbase CONT
2610 and DIFF
2611 and NPLUS
2612 and DIODE
2613 and-not POLY
2614 and-not PPLUS
2615 and-not THKOX
2616 and-not LVTN
2617
2618 layer ndic ndicbase
2619 grow 85
2620 shrink 85
2621 shrink 85
2622 grow 85
2623 or ndicbase
2624 labels CONT
2625
2626 templayer ndilvtcbase CONT
2627 and DIFF
2628 and NPLUS
2629 and DIODE
2630 and-not POLY
2631 and-not PPLUS
2632 and-not THKOX
2633 and LVTN
2634
2635 layer ndilvtc ndilvtcbase
2636 grow 85
2637 shrink 85
2638 shrink 85
2639 grow 85
2640 or ndilvtcbase
2641 labels CONT
2642
2643 templayer pdicbase CONT
2644 and DIFF
2645 and PPLUS
2646 and DIODE
2647 and-not POLY
2648 and-not NPLUS
2649 and-not THKOX
2650 and-not LVTN
2651 and-not HVTP
2652
2653 layer pdic pdicbase
2654 grow 85
2655 shrink 85
2656 shrink 85
2657 grow 85
2658 or pdicbase
2659 labels CONT
2660
2661 templayer pdilvtcbase CONT
2662 and DIFF
2663 and PPLUS
2664 and DIODE
2665 and-not POLY
2666 and-not NPLUS
2667 and-not THKOX
2668 and LVTN
2669 and-not HVTP
2670
2671 layer pdilvtc pdilvtcbase
2672 grow 85
2673 shrink 85
2674 shrink 85
2675 grow 85
2676 or pdilvtcbase
2677 labels CONT
2678
2679 templayer pdihvtcbase CONT
2680 and DIFF
2681 and PPLUS
2682 and DIODE
2683 and-not POLY
2684 and-not NPLUS
2685 and-not THKOX
2686 and-not LVTN
2687 and HVTP
2688
2689 layer pdihvtc pdihvtcbase
2690 grow 85
2691 shrink 85
2692 shrink 85
2693 grow 85
2694 or pdihvtcbase
2695 labels CONT
2696
2697 templayer mvndcbase CONT
2698 and DIFF
2699 and NPLUS
2700 and-not NWELL
2701 and LI
2702 and THKOX
2703
2704 layer mvndc mvndcbase
2705 grow 85
2706 shrink 85
2707 shrink 85
2708 grow 85
2709 or mvndcbase
2710 labels CONT
2711
2712 templayer mvnscbase CONT
2713 and DIFF,TAP
2714 and NPLUS
2715 and NWELL
2716 and LI
2717 and THKOX
2718
2719 layer mvnsc mvnscbase
2720 grow 85
2721 shrink 85
2722 shrink 85
2723 grow 85
2724 or mvnscbase
2725 labels CONT
2726
2727 templayer mvpdcbase CONT
2728 and DIFF
2729 and PPLUS
2730 and NWELL
2731 and LI
2732 and THKOX
2733
2734 layer mvpdc mvpdcbase
2735 grow 85
2736 shrink 85
2737 shrink 85
2738 grow 85
2739 or mvpdcbase
2740 labels CONT
2741
2742 templayer mvpdcnowell CONT
2743 and DIFF
2744 and PPLUS
2745 and mvpfetexpand
2746 and MET1
2747 and THKOX
2748
2749 layer mvpdc mvpdcnowell
2750 grow 85
2751 shrink 85
2752 shrink 85
2753 grow 85
2754 or mvpdcnowell
2755 labels CONT
2756
2757 templayer mvpscbase CONT
2758 and DIFF,TAP
2759 and PPLUS
2760 and-not NWELL
2761 and-not mvpfetexpand
2762 and LI
2763 and THKOX
2764
2765 layer mvpsc mvpscbase
2766 grow 85
2767 shrink 85
2768 shrink 85
2769 grow 85
2770 or mvpscbase
2771 labels CONT
2772
2773 templayer mvndicbase CONT
2774 and DIFF
2775 and NPLUS
2776 and DIODE
2777 and-not POLY
2778 and-not PPLUS
2779 and-not LVTN
2780 and THKOX
2781
2782 layer mvndic mvndicbase
2783 grow 85
2784 shrink 85
2785 shrink 85
2786 grow 85
2787 or mvndicbase
2788 labels CONT
2789
2790 templayer nndicbase CONT
2791 and DIFF
2792 and NPLUS
2793 and DIODE
2794 and-not POLY
2795 and-not PPLUS
2796 and LVTN
2797 and THKOX
2798
2799 layer nndic nndicbase
2800 grow 85
2801 shrink 85
2802 shrink 85
2803 grow 85
2804 or nndicbase
2805 labels CONT
2806
2807 templayer mvpdicbase CONT
2808 and DIFF
2809 and PPLUS
2810 and DIODE
2811 and-not POLY
2812 and-not NPLUS
2813 and THKOX
2814
2815 layer mvpdic mvpdicbase
2816 grow 85
2817 shrink 85
2818 shrink 85
2819 grow 85
2820 or mvpdicbase
2821 labels CONT
2822
2823 layer locali LI,LITXT,LIPIN
2824 and-not LIRES,LISHORT
2825 and-not COREID
2826 labels LI
2827 labels LITXT text
2828 labels LIPIN port
2829
2830 layer coreli LI,LITXT,LIPIN
2831 and-not LIRES,LISHORT
2832 and COREID
2833 labels LI
2834 labels LITXT text
2835 labels LIPIN port
2836
2837 layer rli LI
2838 and LIRES,LISHORT
2839 labels LIRES,LISHORT
2840
2841 layer lic MCON
2842 grow 95
2843 shrink 95
2844 shrink 85
2845 grow 85
2846 or MCON
2847 labels MCON
2848
2849 layer m1 MET1,MET1TXT,MET1PIN
2850 and-not MET1RES,MET1SHORT
2851 labels MET1
2852 labels MET1TXT text
2853 labels MET1PIN port
2854
2855 layer rm1 MET1
2856 and MET1RES,MET1SHORT
2857 labels MET1RES,MET1SHORT
2858
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2859 layer m1fill MET1FILL
2860 labels MET1FILL
2861
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2862#ifdef MIM
2863 layer mimcap MET3
2864 and CAPM
2865 labels CAPM
2866
2867 layer mimcc VIA3
2868 and CAPM
2869 grow 60
2870 grow 40
2871 shrink 40
2872 labels CAPM
2873
2874 layer mimcap2 MET4
2875 and CAPM2
2876 labels CAPM2
2877
2878 layer mim2cc VIA4
2879 and CAPM2
2880 grow 190
2881 grow 210
2882 shrink 210
2883 labels CAPM2
2884
2885#endif (MIM)
2886
2887 templayer m2cbase VIA1
2888 grow 55
2889
2890 layer m2c m2cbase
2891 grow 30
2892 shrink 30
2893 shrink 130
2894 grow 130
2895 or m2cbase
2896
2897 layer m2 MET2,MET2TXT,MET2PIN
2898 and-not MET2RES,MET2SHORT
2899 labels MET2
2900 labels MET2TXT text
2901 labels MET2PIN port
2902
2903 layer rm2 MET2
2904 and MET2RES,MET2SHORT
2905 labels MET2RES,MET2SHORT
2906
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2907 layer m2fill MET2FILL
2908 labels MET2FILL
2909
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2910 templayer m3cbase VIA2
2911 grow 40
2912
2913 layer m3c m3cbase
2914 grow 60
2915 shrink 60
2916 shrink 140
2917 grow 140
2918 or m3cbase
2919
2920 layer m3 MET3,MET3TXT,MET3PIN
2921 and-not MET3RES,MET3SHORT
2922#ifdef MIM
2923 and-not CAPM
2924#endif (MIM)
2925 labels MET3
2926 labels MET3TXT text
2927 labels MET3PIN port
2928
2929 layer rm3 MET3
2930 and MET3RES,MET3SHORT
2931 labels MET3RES,MET3SHORT
2932
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2933 layer m3fill MET3FILL
2934 labels MET3FILL
2935
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2936#ifdef (METAL5)
2937
2938 templayer via3base VIA3
2939#ifdef MIM
2940 and-not CAPM
2941#endif (MIM)
2942 grow 60
2943
2944 layer via3 via3base
2945 grow 40
2946 shrink 40
2947 shrink 160
2948 grow 160
2949 or via3base
2950
2951 layer m4 MET4,MET4TXT,MET4PIN
2952 and-not MET4RES,MET4SHORT
2953#ifdef MIM
2954 and-not CAPM2
2955#endif (MIM)
2956 labels MET4
2957 labels MET4TXT text
2958 labels MET4PIN port
2959
2960 layer rm4 MET4
2961 and MET4RES,MET4SHORT
2962 labels MET4RES,MET4SHORT
2963
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2964 layer m4fill MET4FILL
2965 labels MET4FILL
2966
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2967 layer m5 MET5,MET5TXT,MET5PIN
2968 and-not MET5RES,MET5SHORT
2969 labels MET5
2970 labels MET5TXT text
2971 labels MET5PIN port
2972
2973 layer rm5 MET5
2974 and MET5RES,MET5SHORT
2975 labels MET5RES,MET5SHORT
2976
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2977 layer m5fill MET5FILL
2978 labels MET5FILL
2979
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2980 templayer via4base VIA4
2981#ifdef MIM
2982 and-not CAPM2
2983#endif (MIM)
2984 grow 190
2985
2986 layer via4 via4base
2987 grow 210
2988 shrink 210
2989 shrink 590
2990 grow 590
2991 or via4base
2992#endif (METAL5)
2993
2994#ifdef REDISTRIBUTION
2995 layer metrdl RDL,RDLTXT,RDLPIN
2996 labels RDL
2997 labels RDLTXT text
2998 labels RDLPIN port
2999#endif
3000
3001 # Find diffusion not covered in
3002 # NPLUS or PPLUS and pull it into
3003 # the next layer up
3004
3005 templayer gentrans DIFF
3006 and-not PPLUS
3007 and-not NPLUS
3008 and POLY
3009 copyup DIFF,POLY
3010
3011 templayer gendiff DIFF,TAP
3012 and-not PPLUS
3013 and-not NPLUS
3014 and-not POLY
3015 copyup DIFF
3016
3017 # Handle contacts found by copyup
3018
3019 templayer ndiccopy CONT
3020 and LI
3021 and DIODE
3022 and NPLUS
3023 and-not THKOX
3024
3025 layer ndic ndiccopy
3026 grow 85
3027 shrink 85
3028 shrink 85
3029 grow 85
3030 or ndiccopy
3031 labels CONT
3032
3033 templayer mvndiccopy CONT
3034 and LI
3035 and DIODE
3036 and NPLUS
3037 and THKOX
3038
3039 layer mvndic mvndiccopy
3040 grow 85
3041 shrink 85
3042 shrink 85
3043 grow 85
3044 or mvndiccopy
3045 labels CONT
3046
3047 templayer pdiccopy CONT
3048 and LI
3049 and DIODE
3050 and PPLUS
3051 and-not THKOX
3052
3053 layer pdic pdiccopy
3054 grow 85
3055 shrink 85
3056 shrink 85
3057 grow 85
3058 or pdiccopy
3059 labels CONT
3060
3061 templayer mvpdiccopy CONT
3062 and LI
3063 and DIODE
3064 and PPLUS
3065 and THKOX
3066
3067 layer mvpdic mvpdiccopy
3068 grow 85
3069 shrink 85
3070 shrink 85
3071 grow 85
3072 or mvpdiccopy
3073 labels CONT
3074
3075 templayer ndccopy CONT
3076 and ndifcheck
3077
3078 layer ndc ndccopy
3079 grow 85
3080 shrink 85
3081 shrink 85
3082 grow 85
3083 or ndccopy
3084 labels CONT
3085
3086 templayer mvndccopy CONT
3087 and mvndifcheck
3088
3089 layer mvndc mvndccopy
3090 grow 85
3091 shrink 85
3092 shrink 85
3093 grow 85
3094 or mvndccopy
3095 labels CONT
3096
3097 templayer pdccopy CONT
3098 and pdifcheck
3099
3100 layer pdc pdccopy
3101 grow 85
3102 shrink 85
3103 shrink 85
3104 grow 85
3105 or pdccopy
3106 labels CONT
3107
3108 templayer mvpdccopy CONT
3109 and mvpdifcheck
3110
3111 layer mvpdc mvpdccopy
3112 grow 85
3113 shrink 85
3114 shrink 85
3115 grow 85
3116 or mvpdccopy
3117 labels CONT
3118
3119 templayer pccopy CONT
3120 and polycheck
3121
3122 layer pc pccopy
3123 grow 85
3124 shrink 85
3125 shrink 85
3126 grow 85
3127 or pccopy
3128 labels CONT
3129
3130 templayer nsccopy CONT
3131 and nsubcheck
3132
3133 layer nsc nsccopy
3134 grow 85
3135 shrink 85
3136 shrink 85
3137 grow 85
3138 or nsccopy
3139 labels CONT
3140
3141 templayer mvnsccopy CONT
3142 and mvnsubcheck
3143
3144 layer mvnsc mvnsccopy
3145 grow 85
3146 shrink 85
3147 shrink 85
3148 grow 85
3149 or mvnsccopy
3150 labels CONT
3151
3152 templayer psccopy CONT
3153 and psubcheck
3154
3155 layer psc psccopy
3156 grow 85
3157 shrink 85
3158 shrink 85
3159 grow 85
3160 or psccopy
3161 labels CONT
3162
3163 templayer mvpsccopy CONT
3164 and mvpsubcheck
3165
3166 layer mvpsc mvpsccopy
3167 grow 85
3168 shrink 85
3169 shrink 85
3170 grow 85
3171 or mvpsccopy
3172 labels CONT
3173
3174 # Find contacts not covered in
3175 # metal and pull them into the
3176 # next layer up
3177
3178 templayer gencont CONT
3179 and LI
3180 and-not DIFF,TAP
3181 and-not POLY
3182 and-not DIODE
3183 and-not nsubcheck
3184 and-not psubcheck
3185 and-not mvnsubcheck
3186 and-not mvpsubcheck
3187 copyup CONT,LI
3188
3189 templayer barecont CONT
3190 and-not LI
3191 and-not nsubcheck
3192 and-not psubcheck
3193 and-not mvnsubcheck
3194 and-not mvpsubcheck
3195 copyup CONT
3196
3197 layer glass GLASS,PADTXT,PADPIN
3198 labels GLASS
3199 labels PADTXT text
3200 labels PADPIN port
3201
3202 templayer boundary BOUND,STDCELL,PADCELL
3203 boundary
3204
3205 layer comment LVSTEXT
3206 labels LVSTEXT text
3207
3208 layer comment TTEXT
3209 labels TTEXT text
3210
3211 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3212 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3213
3214# MOS Varactor
3215
3216 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3217 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3218 and NPLUS
3219 and NWELL
3220 and-not THKOX
3221 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3222 # NOTE: Else forms a varactor that is not in the vendor netlist.
3223 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3224 labels POLY
3225
3226 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3227 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3228 and NPLUS
3229 and NWELL
3230 and-not THKOX
3231 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3232 labels POLY
3233
3234 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3235 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3236 and NPLUS
3237 and NWELL
3238 and THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3239 labels POLY
3240
3241 calma NWELL 64 20
3242 calma DIFF 65 20
3243 calma DNWELL 64 18
3244 calma PWRES 64 13
3245 calma TAP 65 44
3246 # LVTN
3247 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3248 # HVTR
3249 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3250 # HVTP
3251 calma HVTP 78 44
3252 # SONOS (TUNM)
3253 calma SONOS 80 20
3254 # NPLUS = NSDM
3255 calma NPLUS 93 44
3256 # PPLUS = PSDM
3257 calma PPLUS 94 20
3258 # HVI
3259 calma THKOX 75 20
3260 # NPC
3261 calma NPC 95 20
3262 # P+ POLY MASK
3263 calma RPM 86 20
3264 calma URPM 79 20
3265 calma LDNTM 11 44
3266 calma HVNTM 125 20
3267 # Poly resistor ID mark
3268 calma POLYRES 66 13
3269 # Diffusion resistor ID mark
3270 calma DIFFRES 65 13
3271 calma POLY 66 20
3272 calma POLYMOD 66 83
3273 # Diode ID mark
3274 calma DIODE 81 23
3275 # Bipolar NPN mark
3276 calma NPNID 82 20
3277 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3278 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3279 # Capacitor ID
3280 calma CAPID 82 64
3281 # Core area ID mark
3282 calma COREID 81 2
3283 # Standard cell ID mark
3284 calma STDCELL 81 4
3285 # Padframe cell ID mark
3286 calma PADCELL 81 3
3287 # Seal ring ID mark
3288 calma SEALID 81 1
3289 # Low tap density ID mark
3290 calma LOWTAPDENSITY 81 14
3291
3292 # LICON
3293 calma CONT 66 44
3294 calma LI 67 20
3295 calma MCON 67 44
3296
3297 calma MET1 68 20
3298 calma VIA1 68 44
3299 calma MET2 69 20
3300 calma VIA2 69 44
3301 calma MET3 70 20
3302#ifdef METAL5
3303 calma VIA3 70 44
3304 calma MET4 71 20
3305 calma VIA4 71 44
3306 calma MET5 72 20
3307#endif
3308#ifdef REDISTRIBUTION
3309 calma RDL 74 20
3310#endif
3311 calma GLASS 76 20
3312
3313 calma SUBPIN 64 59
3314 calma PADPIN 76 5
3315 calma DIFFPIN 65 6
3316 calma TAPPIN 65 5
3317 calma WELLPIN 64 5
3318 calma LIPIN 67 5
3319 calma POLYPIN 66 5
3320 calma MET1PIN 68 5
3321 calma MET2PIN 69 5
3322 calma MET3PIN 70 5
3323#ifdef METAL5
3324 calma MET4PIN 71 5
3325 calma MET5PIN 72 5
3326#endif
3327#ifdef REDISTRIBUTION
3328 calma RDLPIN 74 5
3329#endif
3330
3331 calma LIRES 67 13
3332 calma MET1RES 68 13
3333 calma MET2RES 69 13
3334 calma MET3RES 70 13
3335#ifdef METAL5
3336 calma MET4RES 71 13
3337 calma MET5RES 72 13
3338#endif
3339
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3340 calma MET1FILL 68 28
3341 calma MET2FILL 69 28
3342 calma MET3FILL 70 28
3343#ifdef METAL5
3344 calma MET4FILL 71 28
3345 calma MET5FILL 72 28
3346#endif
3347
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3348 calma POLYSHORT 66 15
3349 calma LISHORT 67 15
3350 calma MET1SHORT 68 15
3351 calma MET2SHORT 69 15
3352 calma MET3SHORT 70 15
3353#ifdef METAL5
3354 calma MET4SHORT 71 15
3355 calma MET5SHORT 72 15
3356#endif
3357
3358 calma SUBTXT 122 16
3359 calma PADTXT 76 16
3360 calma DIFFTXT 65 16
3361 calma POLYTXT 66 16
3362 calma WELLTXT 64 16
3363 calma LITXT 67 16
3364 calma MET1TXT 68 16
3365 calma MET2TXT 69 16
3366 calma MET3TXT 70 16
3367#ifdef METAL5
3368 calma MET4TXT 71 16
3369 calma MET5TXT 72 16
3370#endif
3371#ifdef REDISTRIBUTION
3372 calma RDLPIN 74 16
3373#endif
3374
3375 calma BOUND 235 4
3376
3377 calma LVSTEXT 83 44
3378
3379#ifdef (MIM)
3380 calma CAPM 89 44
3381 calma CAPM2 97 44
3382#endif (MIM)
3383
3384 calma FILLOBSM1 62 24
3385 calma FILLOBSM2 105 52
3386 calma FILLOBSM3 107 24
3387 calma FILLOBSM4 112 4
3388
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3389#-----------------------------------------------------------------------
3390
3391style vendorimport
3392 scalefactor 10 nanometers
3393 gridlimit 5
3394
3395 options ignore-unknown-layer-labels no-reconnect-labels
3396
3397#ifndef MIM
3398 ignore CAPM
3399 ignore CAPM2
3400#endif (!MIM)
3401#ifndef METAL5
3402 ignore MET4,VIA3
3403 ignore MET5,VIA4
3404#endif
3405 ignore NPC
3406 ignore SEALID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3407 ignore CAPID
3408 ignore LDNTM
3409 ignore HVNTM
3410 ignore POLYMOD
3411 ignore LOWTAPDENSITY
3412
3413 layer nwell NWELL,WELLTXT,WELLPIN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3414 and-not PNPID
3415 labels NWELL
3416 labels WELLTXT port
3417 labels WELLPIN port
3418
3419 layer pnp NWELL,WELLTXT,WELLPIN
3420 and PNPID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3421 labels NWELL
3422 labels WELLTXT port
3423 labels WELLPIN port
3424
3425 layer pwell SUBTXT,SUBPIN
3426 labels SUBTXT port
3427 labels SUBPIN port
3428
3429 layer dnwell DNWELL
3430 labels DNWELL
3431
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3432 layer npn DNWELL
3433 and-not NWELL
3434 and NPNID
3435
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3436 layer rpw PWRES
3437 and DNWELL
3438 labels PWRES
3439
3440 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
3441 and-not POLY
3442 and-not NWELL
3443 and-not PPLUS
3444 and-not DIODE
3445 and-not DIFFRES
3446 and-not THKOX
3447 and NPLUS
3448 copyup ndifcheck
3449 labels DIFF
3450 labels DIFFTXT port
3451 labels DIFFPIN port
3452 labels TAPPIN port
3453
3454 layer ndiff ndiffarea
3455
3456 # Copy ndiff areas up for contact checks
3457 templayer xndifcheck ndifcheck
3458 copyup ndifcheck
3459
3460 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
3461 and-not POLY
3462 and-not NWELL
3463 and-not PPLUS
3464 and-not DIODE
3465 and-not DIFFRES
3466 and THKOX
3467 and NPLUS
3468 copyup ndifcheck
3469 labels DIFF
3470 labels DIFFTXT port
3471 labels DIFFPIN port
3472
3473 layer mvndiff mvndiffarea
3474
3475 # Copy ndiff areas up for contact checks
3476 templayer mvxndifcheck mvndifcheck
3477 copyup mvndifcheck
3478
3479 layer ndiode DIFF
3480 and NPLUS
3481 and DIODE
3482 and-not NWELL
3483 and-not POLY
3484 and-not PPLUS
3485 and-not THKOX
3486 and-not LVTN
3487 labels DIFF
3488
3489 layer ndiodelvt DIFF
3490 and NPLUS
3491 and DIODE
3492 and-not NWELL
3493 and-not POLY
3494 and-not PPLUS
3495 and-not THKOX
3496 and LVTN
3497 labels DIFF
3498
3499 templayer ndiodearea DIODE
3500 and NPLUS
3501 and-not THKOX
3502 and-not NWELL
3503 copyup DIODE,NPLUS
3504
3505 layer ndiffres DIFFRES
3506 and NPLUS
3507 and-not THKOX
3508 labels DIFF
3509
3510 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
3511 and-not POLY
3512 and NWELL
3513 and-not NPLUS
3514 and-not DIODE
3515 and-not THKOX
3516 and PPLUS
3517 copyup pdifcheck
3518 labels DIFF
3519 labels DIFFTXT port
3520 labels DIFFPIN port
3521
3522 layer pdiff pdiffarea
3523
3524 layer mvndiode DIFF
3525 and NPLUS
3526 and DIODE
3527 and THKOX
3528 and-not POLY
3529 and-not PPLUS
3530 and-not LVTN
3531 labels DIFF
3532
3533 layer nndiode DIFF
3534 and NPLUS
3535 and DIODE
3536 and THKOX
3537 and-not POLY
3538 and-not PPLUS
3539 and LVTN
3540 labels DIFF
3541
3542 templayer mvndiodearea DIODE
3543 and NPLUS
3544 and THKOX
3545 and-not NWELL
3546 copyup DIODE,NPLUS
3547
3548 layer mvndiffres DIFFRES
3549 and NPLUS
3550 and THKOX
3551 labels DIFF
3552
3553 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
3554 and-not POLY
3555 and NWELL
3556 and-not NPLUS
3557 and THKOX
3558 and-not DIODE
3559 and-not DIFFRES
3560 and PPLUS
3561 copyup mvpdifcheck
3562 labels DIFF
3563 labels DIFFTXT port
3564 labels DIFFPIN port
3565
3566 layer mvpdiff mvpdiffarea
3567
3568 # Copy pdiff areas up for contact checks
3569 templayer xpdifcheck pdifcheck
3570 copyup pdifcheck
3571
3572 layer pdiode DIFF
3573 and PPLUS
3574 and-not POLY
3575 and-not NPLUS
3576 and-not THKOX
3577 and-not LVTN
3578 and-not HVTP
3579 and DIODE
3580 labels DIFF
3581
3582 layer pdiodelvt DIFF
3583 and PPLUS
3584 and-not POLY
3585 and-not NPLUS
3586 and-not THKOX
3587 and LVTN
3588 and-not HVTP
3589 and DIODE
3590 labels DIFF
3591
3592 layer pdiodehvt DIFF
3593 and PPLUS
3594 and-not POLY
3595 and-not NPLUS
3596 and-not THKOX
3597 and-not LVTN
3598 and HVTP
3599 and DIODE
3600 labels DIFF
3601
3602 templayer pdiodearea DIODE
3603 and PPLUS
3604 and-not THKOX
3605 copyup DIODE,PPLUS
3606
3607 # Define pfet areas as known pdiff, regardless of the presence of a well.
3608
3609 templayer pfetarea DIFF
3610 and-not NPLUS
3611 and-not THKOX
3612 and POLY
3613
3614 layer pfet pfetarea
3615 and-not LVTN
3616 and-not HVTP
3617 and-not STDCELL
3618 and-not COREID
3619 labels DIFF
3620
3621 layer scpfet pfetarea
3622 and-not LVTN
3623 and-not HVTP
3624 and STDCELL
3625 labels DIFF
3626
3627 layer ppu pfetarea
3628 and-not LVTN
3629 and-not HVTP
3630 and COREID
3631 labels DIFF
3632
3633 layer pfetlvt pfetarea
3634 and LVTN
3635 labels DIFF
3636
3637 layer pfetmvt pfetarea
3638 and HVTR
3639 labels DIFF
3640
3641 layer pfethvt pfetarea
3642 and HVTP
3643 labels DIFF
3644
3645 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
3646 layer nwell pfetarea
3647 grow 180
3648
3649 # Copy mvpdiff areas up for contact checks
3650 templayer mvxpdifcheck mvpdifcheck
3651 copyup mvpdifcheck
3652
3653 layer mvpdiode DIFF
3654 and PPLUS
3655 and-not POLY
3656 and-not NPLUS
3657 and THKOX
3658 and DIODE
3659 labels DIFF
3660
3661 templayer mvpdiodearea DIODE
3662 and PPLUS
3663 and THKOX
3664 copyup DIODE,PPLUS
3665
3666 # Define pfet areas as known pdiff,
3667 # regardless of the presence of a
3668 # well.
3669
3670 templayer mvpfetarea DIFF
3671 and-not NPLUS
3672 and THKOX
3673 and POLY
3674
3675 layer mvpfet mvpfetarea
3676 labels DIFF
3677
3678 layer pdiff DIFF,DIFFTXT,DIFFPIN
3679 and-not NPLUS
3680 and-not POLY
3681 and-not THKOX
3682 and-not DIODE
3683 and-not DIFFRES
3684 labels DIFF
3685 labels DIFFTXT port
3686 labels DIFFPIN port
3687
3688 layer pdiffres DIFFRES
3689 and PPLUS
3690 and NWELL
3691 and-not THKOX
3692 labels DIFF
3693
3694 layer nfet DIFF
3695 and POLY
3696 and-not PPLUS
3697 and NPLUS
3698 and-not THKOX
3699 and-not LVTN
3700 and-not SONOS
3701 and-not STDCELL
3702 labels DIFF
3703
3704 layer scnfet DIFF
3705 and POLY
3706 and-not PPLUS
3707 and NPLUS
3708 and-not NWELL
3709 and-not THKOX
3710 and-not LVTN
3711 and-not SONOS
3712 and STDCELL
3713 labels DIFF
3714
3715 layer npd DIFF
3716 and POLY
3717 and-not PPLUS
3718 and NPLUS
3719 and-not NWELL
3720 and COREID
3721 labels DIFF
3722
3723 # layer npass DIFF
3724 # and POLY
3725 # and-not PPLUS
3726 # and NPLUS
3727 # and-not NWELL
3728 # and COREID
3729 # labels DIFF
3730
3731 layer nfetlvt DIFF
3732 and POLY
3733 and-not PPLUS
3734 and NPLUS
3735 and-not THKOX
3736 and LVTN
3737 and-not SONOS
3738 labels DIFF
3739
3740 layer nsonos DIFF
3741 and POLY
3742 and-not PPLUS
3743 and NPLUS
3744 and-not THKOX
3745 and LVTN
3746 and SONOS
3747 labels DIFF
3748
3749 templayer nsdarea TAP
3750 and NPLUS
3751 and NWELL
3752 and-not POLY
3753 and-not PPLUS
3754 and-not THKOX
3755 copyup nsubcheck
3756
3757 layer nsd nsdarea
3758 labels TAP
3759
3760 layer nsd TAP,TAPPIN
3761 and NPLUS
3762 and-not POLY
3763 and-not THKOX
3764 labels TAP
3765 labels TAPPIN port
3766
3767 templayer nsdexpand nsdarea
3768 grow 500
3769
3770 # Copy nsub areas up for contact checks
3771 templayer xnsubcheck nsubcheck
3772 copyup nsubcheck
3773
3774 templayer psdarea TAP
3775 and PPLUS
3776 and-not NWELL
3777 and-not POLY
3778 and-not NPLUS
3779 and-not THKOX
3780 and-not pfetexpand
3781 copyup psubcheck
3782
3783 layer psd psdarea
3784 labels TAP
3785
3786 layer psd TAP,TAPPIN
3787 and PPLUS
3788 and-not POLY
3789 and-not THKOX
3790 labels TAP
3791 labels TAPPIN port
3792
3793 templayer psdexpand psdarea
3794 grow 500
3795
3796 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
3797 and-not NPLUS
3798 and-not POLY
3799 and THKOX
3800 and mvpfetexpand
3801 labels DIFF
3802 labels DIFFTXT port
3803 labels DIFFPIN port
3804
3805 layer mvpdiffres DIFFRES
3806 and PPLUS
3807 and NWELL
3808 and THKOX
3809 and-not mvrdpioedge
3810 labels DIFF
3811
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3812 templayer mvnfetarea DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3813 and POLY
3814 and-not PPLUS
3815 and NPLUS
3816 and-not LVTN
3817 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3818 grow 1000
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3819
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3820 templayer mvnnfetarea DIFF,TAP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3821 and POLY
3822 and-not PPLUS
3823 and NPLUS
3824 and LVTN
3825 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3826 and-not mvnfetarea
3827
3828 layer mvnfet DIFF
3829 and POLY
3830 and-not PPLUS
3831 and NPLUS
3832 and THKOX
3833 and-not mvnnfetarea
3834 labels DIFF
3835
3836 layer mvnnfet mvnnfetarea
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3837 labels DIFF
3838
3839 templayer mvnsdarea TAP
3840 and NPLUS
3841 and NWELL
3842 and-not POLY
3843 and-not PPLUS
3844 and THKOX
3845 copyup mvnsubcheck
3846
3847 layer mvnsd mvnsdarea
3848 labels TAP
3849
3850 layer mvnsd TAP,TAPPIN
3851 and NPLUS
3852 and THKOX
3853 labels TAP
3854 labels TAPPIN port
3855
3856 templayer mvnsdexpand mvnsdarea
3857 grow 500
3858
3859 # Copy nsub areas up for contact checks
3860 templayer mvxnsubcheck mvnsubcheck
3861 copyup mvnsubcheck
3862
3863 templayer mvpsdarea DIFF
3864 and PPLUS
3865 and-not NWELL
3866 and-not POLY
3867 and-not NPLUS
3868 and THKOX
3869 and-not mvpfetexpand
3870 copyup mvpsubcheck
3871
3872 layer mvpsd mvpsdarea
3873 labels DIFF
3874
3875 layer mvpsd TAP,TAPPIN
3876 and PPLUS
3877 and THKOX
3878 labels TAP
3879 labels TAPPIN port
3880
3881 templayer mvpsdexpand mvpsdarea
3882 grow 500
3883
3884 # Copy psub areas up for contact checks
3885 templayer xpsubcheck psubcheck
3886 copyup psubcheck
3887
3888 templayer mvxpsubcheck mvpsubcheck
3889 copyup mvpsubcheck
3890
3891 layer psd TAP
3892 and-not PPLUS
3893 and-not NPLUS
3894 and-not POLY
3895 and-not THKOX
3896 and-not pfetexpand
3897 and psdexpand
3898
3899 layer nsd TAP
3900 and-not PPLUS
3901 and-not NPLUS
3902 and-not POLY
3903 and-not THKOX
3904 and nsdexpand
3905
3906 layer mvpsd TAP
3907 and-not PPLUS
3908 and-not NPLUS
3909 and-not POLY
3910 and THKOX
3911 and-not mvpfetexpand
3912 and mvpsdexpand
3913
3914 layer mvnsd TAP
3915 and-not PPLUS
3916 and-not NPLUS
3917 and-not POLY
3918 and THKOX
3919 and mvnsdexpand
3920
3921 templayer hresarea POLY
3922 and RPM
3923 grow 3000
3924
3925 templayer uresarea POLY
3926 and URPM
3927 grow 3000
3928
3929 templayer diffresarea DIFFRES
3930 and-not THKOX
3931 grow 3000
3932
3933 templayer mvdiffresarea DIFFRES
3934 and THKOX
3935 grow 3000
3936
3937 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
3938
3939 layer pfet POLY
3940 and DIFF
3941 and diffresarea
3942 and-not NPLUS
3943 and-not STDCELL
3944
3945 layer scpfet POLY
3946 and DIFF
3947 and diffresarea
3948 and-not NPLUS
3949 and STDCELL
3950
3951 templayer xpolyterm RPM,URPM
3952 and POLY
3953 and-not POLYRES
3954 # add back the 0.06um contact surround in the direction of the resistor
3955 grow 60
3956 and POLY
3957
3958 layer xpc xpolyterm
3959
3960 templayer polyarea POLY
3961 and-not POLYRES
3962 and-not POLYSHORT
3963 and-not DIFF
3964 and-not RPM
3965 and-not URPM
3966 copyup polycheck
3967
3968 layer poly polyarea,POLYTXT,POLYPIN
3969 labels POLY
3970 labels POLYTXT port
3971 labels POLYPIN port
3972
3973 # Copy (non-resistor) poly areas up for contact checks
3974 templayer xpolycheck polycheck
3975 copyup polycheck
3976
3977 layer mrp1 POLY
3978 and POLYRES
3979 and-not RPM
3980 and-not URPM
3981 labels POLY
3982
3983 layer rmp POLY
3984 and POLYSHORT
3985 labels POLY
3986
3987 layer xhrpoly POLY
3988 and POLYRES
3989 and RPM
3990 and-not URPM
3991 and PPLUS
3992 and NPC
3993 and-not xpolyterm
3994 labels POLY
3995
3996 layer uhrpoly POLY
3997 and POLYRES
3998 and URPM
3999 and-not RPM
4000 and NPC
4001 and-not xpolyterm
4002 labels POLY
4003
4004 templayer ndcbase CONT
4005 and DIFF
4006 and NPLUS
4007 and-not NWELL
4008 and LI
4009 and-not THKOX
4010
4011 layer ndc ndcbase
4012 grow 85
4013 shrink 85
4014 shrink 85
4015 grow 85
4016 or ndcbase
4017 labels CONT
4018
4019 templayer nscbase CONT
4020 and DIFF,TAP
4021 and NPLUS
4022 and NWELL
4023 and LI
4024 and-not THKOX
4025
4026 layer nsc nscbase
4027 grow 85
4028 shrink 85
4029 shrink 85
4030 grow 85
4031 or nscbase
4032 labels CONT
4033
4034 templayer pdcbase CONT
4035 and DIFF
4036 and PPLUS
4037 and NWELL
4038 and LI
4039 and-not THKOX
4040
4041 layer pdc pdcbase
4042 grow 85
4043 shrink 85
4044 shrink 85
4045 grow 85
4046 or pdcbase
4047 labels CONT
4048
4049 templayer pdcnowell CONT
4050 and DIFF
4051 and PPLUS
4052 and pfetexpand
4053 and LI
4054 and-not THKOX
4055
4056 layer pdc pdcnowell
4057 grow 85
4058 shrink 85
4059 shrink 85
4060 grow 85
4061 or pdcnowell
4062 labels CONT
4063
4064 templayer pscbase CONT
4065 and DIFF,TAP
4066 and PPLUS
4067 and-not NWELL
4068 and-not pfetexpand
4069 and LI
4070 and-not THKOX
4071
4072 layer psc pscbase
4073 grow 85
4074 shrink 85
4075 shrink 85
4076 grow 85
4077 or pscbase
4078 labels CONT
4079
4080 templayer pcbase CONT
4081 and POLY
4082 and-not DIFF
4083 and-not RPM,URPM
4084 and LI
4085
4086 layer pc pcbase
4087 grow 85
4088 shrink 85
4089 shrink 85
4090 grow 85
4091 or pcbase
4092 labels CONT
4093
4094 templayer ndicbase CONT
4095 and DIFF
4096 and NPLUS
4097 and DIODE
4098 and-not POLY
4099 and-not PPLUS
4100 and-not THKOX
4101 and-not LVTN
4102
4103 layer ndic ndicbase
4104 grow 85
4105 shrink 85
4106 shrink 85
4107 grow 85
4108 or ndicbase
4109 labels CONT
4110
4111 templayer ndilvtcbase CONT
4112 and DIFF
4113 and NPLUS
4114 and DIODE
4115 and-not POLY
4116 and-not PPLUS
4117 and-not THKOX
4118 and LVTN
4119
4120 layer ndilvtc ndilvtcbase
4121 grow 85
4122 shrink 85
4123 shrink 85
4124 grow 85
4125 or ndilvtcbase
4126 labels CONT
4127
4128 templayer pdicbase CONT
4129 and DIFF
4130 and PPLUS
4131 and DIODE
4132 and-not POLY
4133 and-not NPLUS
4134 and-not THKOX
4135 and-not LVTN
4136 and-not HVTP
4137
4138 layer pdic pdicbase
4139 grow 85
4140 shrink 85
4141 shrink 85
4142 grow 85
4143 or pdicbase
4144 labels CONT
4145
4146 templayer pdilvtcbase CONT
4147 and DIFF
4148 and PPLUS
4149 and DIODE
4150 and-not POLY
4151 and-not NPLUS
4152 and-not THKOX
4153 and LVTN
4154 and-not HVTP
4155
4156 layer pdilvtc pdilvtcbase
4157 grow 85
4158 shrink 85
4159 shrink 85
4160 grow 85
4161 or pdilvtcbase
4162 labels CONT
4163
4164 templayer pdihvtcbase CONT
4165 and DIFF
4166 and PPLUS
4167 and DIODE
4168 and-not POLY
4169 and-not NPLUS
4170 and-not THKOX
4171 and-not LVTN
4172 and HVTP
4173
4174 layer pdihvtc pdihvtcbase
4175 grow 85
4176 shrink 85
4177 shrink 85
4178 grow 85
4179 or pdihvtcbase
4180 labels CONT
4181
4182 templayer mvndcbase CONT
4183 and DIFF
4184 and NPLUS
4185 and-not NWELL
4186 and LI
4187 and THKOX
4188
4189 layer mvndc mvndcbase
4190 grow 85
4191 shrink 85
4192 shrink 85
4193 grow 85
4194 or mvndcbase
4195 labels CONT
4196
4197 templayer mvnscbase CONT
4198 and DIFF,TAP
4199 and NPLUS
4200 and NWELL
4201 and LI
4202 and THKOX
4203
4204 layer mvnsc mvnscbase
4205 grow 85
4206 shrink 85
4207 shrink 85
4208 grow 85
4209 or mvnscbase
4210 labels CONT
4211
4212 templayer mvpdcbase CONT
4213 and DIFF
4214 and PPLUS
4215 and NWELL
4216 and LI
4217 and THKOX
4218
4219 layer mvpdc mvpdcbase
4220 grow 85
4221 shrink 85
4222 shrink 85
4223 grow 85
4224 or mvpdcbase
4225 labels CONT
4226
4227 templayer mvpdcnowell CONT
4228 and DIFF
4229 and PPLUS
4230 and mvpfetexpand
4231 and MET1
4232 and THKOX
4233
4234 layer mvpdc mvpdcnowell
4235 grow 85
4236 shrink 85
4237 shrink 85
4238 grow 85
4239 or mvpdcnowell
4240 labels CONT
4241
4242 templayer mvpscbase CONT
4243 and DIFF,TAP
4244 and PPLUS
4245 and-not NWELL
4246 and-not mvpfetexpand
4247 and LI
4248 and THKOX
4249
4250 layer mvpsc mvpscbase
4251 grow 85
4252 shrink 85
4253 shrink 85
4254 grow 85
4255 or mvpscbase
4256 labels CONT
4257
4258 templayer mvndicbase CONT
4259 and DIFF
4260 and NPLUS
4261 and DIODE
4262 and-not POLY
4263 and-not PPLUS
4264 and-not LVTN
4265 and THKOX
4266
4267 layer mvndic mvndicbase
4268 grow 85
4269 shrink 85
4270 shrink 85
4271 grow 85
4272 or mvndicbase
4273 labels CONT
4274
4275 templayer nndicbase CONT
4276 and DIFF
4277 and NPLUS
4278 and DIODE
4279 and-not POLY
4280 and-not PPLUS
4281 and LVTN
4282 and THKOX
4283
4284 layer nndic nndicbase
4285 grow 85
4286 shrink 85
4287 shrink 85
4288 grow 85
4289 or nndicbase
4290 labels CONT
4291
4292 templayer mvpdicbase CONT
4293 and DIFF
4294 and PPLUS
4295 and DIODE
4296 and-not POLY
4297 and-not NPLUS
4298 and THKOX
4299
4300 layer mvpdic mvpdicbase
4301 grow 85
4302 shrink 85
4303 shrink 85
4304 grow 85
4305 or mvpdicbase
4306 labels CONT
4307
4308 layer locali LI,LITXT,LIPIN
4309 and-not LIRES,LISHORT
4310 and-not COREID
4311 labels LI
4312 labels LITXT port
4313 labels LIPIN port
4314
4315 layer coreli LI,LITXT,LIPIN
4316 and-not LIRES,LISHORT
4317 and COREID
4318 labels LI
4319 labels LITXT port
4320 labels LIPIN port
4321
4322 layer rli LI
4323 and LIRES,LISHORT
4324 labels LIRES,LISHORT
4325
4326 layer lic MCON
4327 grow 95
4328 shrink 95
4329 shrink 85
4330 grow 85
4331 or MCON
4332 labels MCON
4333
4334 layer m1 MET1,MET1TXT,MET1PIN
4335 and-not MET1RES,MET1SHORT
4336 labels MET1
4337 labels MET1TXT port
4338 labels MET1PIN port
4339
4340 layer rm1 MET1
4341 and MET1RES,MET1SHORT
4342 labels MET1RES,MET1SHORT
4343
4344 layer m1fill MET1FILL
4345 labels MET1FILL
4346
4347#ifdef MIM
4348 layer mimcap MET3
4349 and CAPM
4350 labels CAPM
4351
4352 layer mimcc VIA3
4353 and CAPM
4354 grow 60
4355 grow 40
4356 shrink 40
4357 labels CAPM
4358
4359 layer mimcap2 MET4
4360 and CAPM2
4361 labels CAPM2
4362
4363 layer mim2cc VIA4
4364 and CAPM2
4365 grow 190
4366 grow 210
4367 shrink 210
4368 labels CAPM2
4369
4370#endif (MIM)
4371
4372 templayer m2cbase VIA1
4373 grow 55
4374
4375 layer m2c m2cbase
4376 grow 30
4377 shrink 30
4378 shrink 130
4379 grow 130
4380 or m2cbase
4381
4382 layer m2 MET2,MET2TXT,MET2PIN
4383 and-not MET2RES,MET2SHORT
4384 labels MET2
4385 labels MET2TXT port
4386 labels MET2PIN port
4387
4388 layer rm2 MET2
4389 and MET2RES,MET2SHORT
4390 labels MET2RES,MET2SHORT
4391
4392 layer m2fill MET2FILL
4393 labels MET2FILL
4394
4395 templayer m3cbase VIA2
4396 grow 40
4397
4398 layer m3c m3cbase
4399 grow 60
4400 shrink 60
4401 shrink 140
4402 grow 140
4403 or m3cbase
4404
4405 layer m3 MET3,MET3TXT,MET3PIN
4406 and-not MET3RES,MET3SHORT
4407#ifdef MIM
4408 and-not CAPM
4409#endif (MIM)
4410 labels MET3
4411 labels MET3TXT port
4412 labels MET3PIN port
4413
4414 layer rm3 MET3
4415 and MET3RES,MET3SHORT
4416 labels MET3RES,MET3SHORT
4417
4418 layer m3fill MET3FILL
4419 labels MET3FILL
4420
4421#ifdef (METAL5)
4422
4423 templayer via3base VIA3
4424#ifdef MIM
4425 and-not CAPM
4426#endif (MIM)
4427 grow 60
4428
4429 layer via3 via3base
4430 grow 40
4431 shrink 40
4432 shrink 160
4433 grow 160
4434 or via3base
4435
4436 layer m4 MET4,MET4TXT,MET4PIN
4437 and-not MET4RES,MET4SHORT
4438#ifdef MIM
4439 and-not CAPM2
4440#endif (MIM)
4441 labels MET4
4442 labels MET4TXT port
4443 labels MET4PIN port
4444
4445 layer rm4 MET4
4446 and MET4RES,MET4SHORT
4447 labels MET4RES,MET4SHORT
4448
4449 layer m4fill MET4FILL
4450 labels MET4FILL
4451
4452 layer m5 MET5,MET5TXT,MET5PIN
4453 and-not MET5RES,MET5SHORT
4454 labels MET5
4455 labels MET5TXT port
4456 labels MET5PIN port
4457
4458 layer rm5 MET5
4459 and MET5RES,MET5SHORT
4460 labels MET5RES,MET5SHORT
4461
4462 layer m5fill MET5FILL
4463 labels MET5FILL
4464
4465 templayer via4base VIA4
4466#ifdef MIM
4467 and-not CAPM2
4468#endif (MIM)
4469 grow 190
4470
4471 layer via4 via4base
4472 grow 210
4473 shrink 210
4474 shrink 590
4475 grow 590
4476 or via4base
4477#endif (METAL5)
4478
4479#ifdef REDISTRIBUTION
4480 layer metrdl RDL,RDLTXT,RDLPIN
4481 labels RDL
4482 labels RDLTXT port
4483 labels RDLPIN port
4484#endif
4485
4486 # Find diffusion not covered in
4487 # NPLUS or PPLUS and pull it into
4488 # the next layer up
4489
4490 templayer gentrans DIFF
4491 and-not PPLUS
4492 and-not NPLUS
4493 and POLY
4494 copyup DIFF,POLY
4495
4496 templayer gendiff DIFF,TAP
4497 and-not PPLUS
4498 and-not NPLUS
4499 and-not POLY
4500 copyup DIFF
4501
4502 # Handle contacts found by copyup
4503
4504 templayer ndiccopy CONT
4505 and LI
4506 and DIODE
4507 and NPLUS
4508 and-not THKOX
4509
4510 layer ndic ndiccopy
4511 grow 85
4512 shrink 85
4513 shrink 85
4514 grow 85
4515 or ndiccopy
4516 labels CONT
4517
4518 templayer mvndiccopy CONT
4519 and LI
4520 and DIODE
4521 and NPLUS
4522 and THKOX
4523
4524 layer mvndic mvndiccopy
4525 grow 85
4526 shrink 85
4527 shrink 85
4528 grow 85
4529 or mvndiccopy
4530 labels CONT
4531
4532 templayer pdiccopy CONT
4533 and LI
4534 and DIODE
4535 and PPLUS
4536 and-not THKOX
4537
4538 layer pdic pdiccopy
4539 grow 85
4540 shrink 85
4541 shrink 85
4542 grow 85
4543 or pdiccopy
4544 labels CONT
4545
4546 templayer mvpdiccopy CONT
4547 and LI
4548 and DIODE
4549 and PPLUS
4550 and THKOX
4551
4552 layer mvpdic mvpdiccopy
4553 grow 85
4554 shrink 85
4555 shrink 85
4556 grow 85
4557 or mvpdiccopy
4558 labels CONT
4559
4560 templayer ndccopy CONT
4561 and ndifcheck
4562
4563 layer ndc ndccopy
4564 grow 85
4565 shrink 85
4566 shrink 85
4567 grow 85
4568 or ndccopy
4569 labels CONT
4570
4571 templayer mvndccopy CONT
4572 and mvndifcheck
4573
4574 layer mvndc mvndccopy
4575 grow 85
4576 shrink 85
4577 shrink 85
4578 grow 85
4579 or mvndccopy
4580 labels CONT
4581
4582 templayer pdccopy CONT
4583 and pdifcheck
4584
4585 layer pdc pdccopy
4586 grow 85
4587 shrink 85
4588 shrink 85
4589 grow 85
4590 or pdccopy
4591 labels CONT
4592
4593 templayer mvpdccopy CONT
4594 and mvpdifcheck
4595
4596 layer mvpdc mvpdccopy
4597 grow 85
4598 shrink 85
4599 shrink 85
4600 grow 85
4601 or mvpdccopy
4602 labels CONT
4603
4604 templayer pccopy CONT
4605 and polycheck
4606
4607 layer pc pccopy
4608 grow 85
4609 shrink 85
4610 shrink 85
4611 grow 85
4612 or pccopy
4613 labels CONT
4614
4615 templayer nsccopy CONT
4616 and nsubcheck
4617
4618 layer nsc nsccopy
4619 grow 85
4620 shrink 85
4621 shrink 85
4622 grow 85
4623 or nsccopy
4624 labels CONT
4625
4626 templayer mvnsccopy CONT
4627 and mvnsubcheck
4628
4629 layer mvnsc mvnsccopy
4630 grow 85
4631 shrink 85
4632 shrink 85
4633 grow 85
4634 or mvnsccopy
4635 labels CONT
4636
4637 templayer psccopy CONT
4638 and psubcheck
4639
4640 layer psc psccopy
4641 grow 85
4642 shrink 85
4643 shrink 85
4644 grow 85
4645 or psccopy
4646 labels CONT
4647
4648 templayer mvpsccopy CONT
4649 and mvpsubcheck
4650
4651 layer mvpsc mvpsccopy
4652 grow 85
4653 shrink 85
4654 shrink 85
4655 grow 85
4656 or mvpsccopy
4657 labels CONT
4658
4659 # Find contacts not covered in
4660 # metal and pull them into the
4661 # next layer up
4662
4663 templayer gencont CONT
4664 and LI
4665 and-not DIFF,TAP
4666 and-not POLY
4667 and-not DIODE
4668 and-not nsubcheck
4669 and-not psubcheck
4670 and-not mvnsubcheck
4671 and-not mvpsubcheck
4672 copyup CONT,LI
4673
4674 templayer barecont CONT
4675 and-not LI
4676 and-not nsubcheck
4677 and-not psubcheck
4678 and-not mvnsubcheck
4679 and-not mvpsubcheck
4680 copyup CONT
4681
4682 layer glass GLASS,PADTXT,PADPIN
4683 labels GLASS
4684 labels PADTXT port
4685 labels PADPIN port
4686
4687 templayer boundary BOUND,STDCELL,PADCELL
4688 boundary
4689
4690 layer comment LVSTEXT
4691 labels LVSTEXT text
4692
4693 layer comment TTEXT
4694 labels TTEXT text
4695
4696 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4697 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4698
4699# MOS Varactor
4700
4701 layer var POLY
4702 and TAP
4703 and NPLUS
4704 and NWELL
4705 and-not THKOX
4706 and-not HVTP
4707 # NOTE: Else forms a varactor that is not in the vendor netlist.
4708 and-not COREID
4709 labels POLY
4710
4711 layer varhvt POLY
4712 and TAP
4713 and NPLUS
4714 and NWELL
4715 and-not THKOX
4716 and HVTP
4717 labels POLY
4718
4719 layer mvvar POLY
4720 and TAP
4721 and NPLUS
4722 and NWELL
4723 and THKOX
4724 labels POLY
4725
4726 calma NWELL 64 20
4727 calma DIFF 65 20
4728 calma DNWELL 64 18
4729 calma PWRES 64 13
4730 calma TAP 65 44
4731 # LVTN
4732 calma LVTN 125 44
4733 # HVTR
4734 calma HVTR 18 20
4735 # HVTP
4736 calma HVTP 78 44
4737 # SONOS (TUNM)
4738 calma SONOS 80 20
4739 # NPLUS = NSDM
4740 calma NPLUS 93 44
4741 # PPLUS = PSDM
4742 calma PPLUS 94 20
4743 # HVI
4744 calma THKOX 75 20
4745 # NPC
4746 calma NPC 95 20
4747 # P+ POLY MASK
4748 calma RPM 86 20
4749 calma URPM 79 20
4750 calma LDNTM 11 44
4751 calma HVNTM 125 20
4752 # Poly resistor ID mark
4753 calma POLYRES 66 13
4754 # Diffusion resistor ID mark
4755 calma DIFFRES 65 13
4756 calma POLY 66 20
4757 calma POLYMOD 66 83
4758 # Diode ID mark
4759 calma DIODE 81 23
4760 # Bipolar NPN mark
4761 calma NPNID 82 20
4762 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4763 calma PNPID 82 44
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4764 # Capacitor ID
4765 calma CAPID 82 64
4766 # Core area ID mark
4767 calma COREID 81 2
4768 # Standard cell ID mark
4769 calma STDCELL 81 4
4770 # Padframe cell ID mark
4771 calma PADCELL 81 3
4772 # Seal ring ID mark
4773 calma SEALID 81 1
4774 # Low tap density ID mark
4775 calma LOWTAPDENSITY 81 14
4776
4777 # LICON
4778 calma CONT 66 44
4779 calma LI 67 20
4780 calma MCON 67 44
4781
4782 calma MET1 68 20
4783 calma VIA1 68 44
4784 calma MET2 69 20
4785 calma VIA2 69 44
4786 calma MET3 70 20
4787#ifdef METAL5
4788 calma VIA3 70 44
4789 calma MET4 71 20
4790 calma VIA4 71 44
4791 calma MET5 72 20
4792#endif
4793#ifdef REDISTRIBUTION
4794 calma RDL 74 20
4795#endif
4796 calma GLASS 76 20
4797
4798 calma SUBPIN 64 59
4799 calma PADPIN 76 5
4800 calma DIFFPIN 65 6
4801 calma TAPPIN 65 5
4802 calma WELLPIN 64 5
4803 calma LIPIN 67 5
4804 calma POLYPIN 66 5
4805 calma MET1PIN 68 5
4806 calma MET2PIN 69 5
4807 calma MET3PIN 70 5
4808#ifdef METAL5
4809 calma MET4PIN 71 5
4810 calma MET5PIN 72 5
4811#endif
4812#ifdef REDISTRIBUTION
4813 calma RDLPIN 74 5
4814#endif
4815
4816 calma LIRES 67 13
4817 calma MET1RES 68 13
4818 calma MET2RES 69 13
4819 calma MET3RES 70 13
4820#ifdef METAL5
4821 calma MET4RES 71 13
4822 calma MET5RES 72 13
4823#endif
4824
4825 calma MET1FILL 68 28
4826 calma MET2FILL 69 28
4827 calma MET3FILL 70 28
4828#ifdef METAL5
4829 calma MET4FILL 71 28
4830 calma MET5FILL 72 28
4831#endif
4832
4833 calma POLYSHORT 66 15
4834 calma LISHORT 67 15
4835 calma MET1SHORT 68 15
4836 calma MET2SHORT 69 15
4837 calma MET3SHORT 70 15
4838#ifdef METAL5
4839 calma MET4SHORT 71 15
4840 calma MET5SHORT 72 15
4841#endif
4842
4843 calma SUBTXT 122 16
4844 calma PADTXT 76 16
4845 calma DIFFTXT 65 16
4846 calma POLYTXT 66 16
4847 calma WELLTXT 64 16
4848 calma LITXT 67 16
4849 calma MET1TXT 68 16
4850 calma MET2TXT 69 16
4851 calma MET3TXT 70 16
4852#ifdef METAL5
4853 calma MET4TXT 71 16
4854 calma MET5TXT 72 16
4855#endif
4856#ifdef REDISTRIBUTION
4857 calma RDLPIN 74 16
4858#endif
4859
4860 calma BOUND 235 4
4861
4862 calma LVSTEXT 83 44
4863
4864#ifdef (MIM)
4865 calma CAPM 89 44
4866 calma CAPM2 97 44
4867#endif (MIM)
4868
4869 calma FILLOBSM1 62 24
4870 calma FILLOBSM2 105 52
4871 calma FILLOBSM3 107 24
4872 calma FILLOBSM4 112 4
4873
4874end
4875
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4876#-----------------------------------------------------
4877# Digital flow maze router cost parameters
4878#-----------------------------------------------------
4879
4880mzrouter
4881end
4882
4883#-----------------------------------------------------
4884# Vendor DRC rules
4885#-----------------------------------------------------
4886
4887drc
4888
4889 style drc variants (fast),(full),(routing)
4890
4891 scalefactor 10
4892
4893 cifstyle drc
4894
4895 variants (fast),(full)
4896
4897#-----------------------------
4898# DNWELL
4899#-----------------------------
4900
4901 width dnwell 3000 "Deep N-well width < %d (Dnwell 2)"
4902 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)"
4903 spacing dnwell allnwell 4500 surround_ok \
4904 "Deep N-well spacing to N-well < %d (Nwell 7)"
4905 cifmaxwidth nwell_missing 0 bend_illegal \
4906 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)"
4907 cifmaxwidth dnwell_missing 0 bend_illegal \
4908 "SONOS nFET must be in Deep N-well (Tunm 6a)"
4909
4910#-----------------------------
4911# NWELL
4912#-----------------------------
4913
4914 width allnwell 840 "N-well width < %d (Nwell 1)"
4915 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)"
4916
4917#-----------------------------
4918# DIFF
4919#-----------------------------
4920
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4921 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,ppu,*psd,*pdiode,pdiffres \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4922 150 "Diffusion width < %d (Diff/tap 1)"
4923 width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
4924 "MV Diffusion width < %d (Diff/tap 14)"
4925 width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)"
4926 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)"
4927 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)"
4928 extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)"
4929 extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)"
4930 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)"
4931 spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
4932 "Diffusion spacing < %d (Diff/tap 3)"
4933 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
4934 "MV Diffusion spacing < %d (Diff/tap 15a)"
4935 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
4936 "MV Diffusion to MV tap spacing < %d (Diff/tap 3)"
4937 spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
4938 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b)"
4939 spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
4940 "MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19)"
4941 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
4942 "N-Diffusion spacing to N-well < %d (Diff/tap 9)"
4943 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
4944 "N-Diffusion spacing to N-well < %d (Diff/tap 9)"
4945 spacing *psd allnwell 130 touching_illegal \
4946 "P-tap spacing to N-well < %d (Diff/tap 11)"
4947 spacing *mvpsd allnwell 130 touching_illegal \
4948 "P-tap spacing to N-well < %d (Diff/tap 11)"
4949 surround *nsd allnwell 180 absence_illegal \
4950 "N-well overlap of N-tap < %d (Diff/tap 10)"
4951 surround *mvnsd allnwell 330 absence_illegal \
4952 "N-well overlap of MV N-tap < %d (Diff/tap 19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4953 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4954 "N-well overlap of P-Diffusion < %d (Diff/tap 8)"
4955 surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
4956 "N-well overlap of P-Diffusion < %d (Diff/tap 17)"
4957 surround mvvar allnwell 560 absence_illegal \
4958 "N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b)"
4959 spacing *mvndiode *mvndiode 1070 touching_ok \
4960 "MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3)"
4961
4962 # Butting junction rules
4963 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
4964 "N-Diffusion to P-tap spacing < %d across butted junction"
4965 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
4966 "N-Diffusion to P-tap spacing < %d across butted junction"
4967 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
4968 "P-Diffusion to N-tap spacing < %d across butted junction"
4969 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
4970 "P-Diffusion to N-tap spacing < %d across butted junction"
4971
4972 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
4973 "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
4974 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
4975 "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
4976 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
4977 "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
4978 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
4979 "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
4980
4981 variants (full)
4982
4983 # Latchup rules
4984 cifmaxwidth ptap_missing 0 bend_illegal \
4985 "N-diff distance to P-tap must be < 15.0um (LU 2)"
4986 cifmaxwidth dptap_missing 0 bend_illegal \
4987 "N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)"
4988 cifmaxwidth ntap_missing 0 bend_illegal \
4989 "P-diff distance to N-tap must be < 15.0um (LU 3)"
4990
4991 variants *
4992
4993#-----------------------------
4994# POLY
4995#-----------------------------
4996
4997 width allpoly 150 "Poly width < %d (Poly 1a)"
4998 spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)"
4999 spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
5000 "Poly spacing to Diffusion < %d (Poly 4a)"
5001 spacing npres *nsd 480 touching_illegal \
5002 "Poly resistor spacing to N-tap < %d (Poly 9)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5003 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5004 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
5005 "N-Diffusion overhang of nmos < %d (Poly 7)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5006 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5007 overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
5008 overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)"
5009 rect_only allfets "No bends in transistors (Poly 11)"
5010 rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)"
5011 extend xpc/a xhrpoly,uhrpoly 2160 \
5012 "Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)"
5013 spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \
5014 "Distance between precision resistors < %d (RPM 2 + 2 * RPM 3)"
5015
5016#--------------------------------------------------------------------
5017# NPC (Nitride Poly Cut)
5018#--------------------------------------------------------------------
5019
5020# Layer NPC is defined automatically around poly contacts (grow 0.1um)
5021
5022#--------------------------------------------------------------------
5023# CONT (LICON, contact between poly/diff and LI)
5024#--------------------------------------------------------------------
5025
5026 width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
5027 width nsc/li 170 "N-tap contact width < %d (LIcon 1)"
5028 width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
5029 width psc/li 170 "P-tap contact width < %d (LIcon 1)"
5030 width ndic/li 170 "N-diode contact width < %d (LIcon 1)"
5031 width pdic/li 170 "P-diode contact width < %d (LIcon 1)"
5032 width pc/li 170 "Poly contact width < %d (LIcon 1)"
5033
5034 width xpc/li 350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)"
5035
5036 width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
5037 width mvnsc/li 170 "N-tap contact width < %d (LIcon 1)"
5038 width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
5039 width mvpsc/li 170 "P-tap contact width < %d (LIcon 1)"
5040 width mvndic/li 170 "N-diode contact width < %d (LIcon 1)"
5041 width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)"
5042
5043 spacing allpdiffcont allndiffcont 170 touching_illegal \
5044 "Diffusion contact spacing < %d (LIcon 2)"
5045 spacing allndiffcont allndiffcont 170 touching_ok \
5046 "Diffusion contact spacing < %d (LIcon 2)"
5047 spacing allpdiffcont allpdiffcont 170 touching_ok \
5048 "Diffusion contact spacing < %d (LIcon 2)"
5049 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)"
5050
5051 spacing pc alldiff 190 touching_illegal \
5052 "Poly contact spacing to diffusion < %d (LIcon 14)"
5053 spacing pc allpfets 235 touching_illegal \
5054 "Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a)"
5055
5056 spacing ndc,pdc nfet,pfet 55 touching_illegal \
5057 "Diffusion contact to gate < %d (LIcon 11)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5058 spacing ndc,pdc scnfet,npd,npass,scpfet,ppu 50 touching_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5059 "Diffusion contact to standard cell gate < %d (LIcon 11)"
5060 spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
5061 "Diffusion contact to gate < %d (LIcon 11)"
5062 spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
5063 spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
5064 spacing nsc varactor,varhvt 250 touching_illegal \
5065 "Diffusion contact to varactor gate < %d (LIcon 10)"
5066 spacing mvnsc mvvar 250 touching_illegal \
5067 "Diffusion contact to varactor gate < %d (LIcon 10)"
5068
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5069 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 40 absence_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5070 "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5071 surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetmvt,pfetlvt 40 absence_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5072 "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
5073 surround ndic/a *ndi 40 absence_illegal \
5074 "N-diode overlap of N-diode contact < %d (LIcon 5a)"
5075 surround pdic/a *pdi 40 absence_illegal \
5076 "P-diode overlap of N-diode contact < %d (LIcon 5a)"
5077
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5078 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 60 directional \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5079 "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5080 surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetmvt,pfetlvt 60 directional \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5081 "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
5082 surround ndic/a *ndi 60 directional \
5083 "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
5084 surround pdic/a *pdi 60 directional \
5085 "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
5086
5087 surround nsc/a *nsd 120 directional \
5088 "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
5089 surround psc/a *psd 120 directional \
5090 "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
5091
5092 surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
5093 "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
5094 surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
5095 "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
5096 surround mvndic/a *mvndi 40 absence_illegal \
5097 "N-diode overlap of N-diode contact < %d (LIcon 5a)"
5098 surround mvpdic/a *mvpdi 40 absence_illegal \
5099 "P-diode overlap of N-diode contact < %d (LIcon 5a)"
5100
5101 surround mvndc/a *mvndiff,mvnfet 60 directional \
5102 "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
5103 surround mvpdc/a *mvpdiff,mvpfet 60 directional \
5104 "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
5105 surround mvndic/a *mvndi 60 directional \
5106 "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
5107 surround mvpdic/a *mvpdi 60 directional \
5108 "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
5109
5110 surround mvnsc/a *mvnsd 120 directional \
5111 "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
5112 surround mvpsc/a *mvpsd 120 directional \
5113 "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
5114
5115 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
5116 "Poly overlap of poly contact < %d (LIcon 8)"
5117 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
5118 "Poly overlap of poly contact < %d in one direction (LIcon 8a)"
5119
5120 exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
5121 exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
5122
5123#-------------------------------------------------------------
5124# LI - Local interconnect layer
5125#-------------------------------------------------------------
5126
5127 width *li,rli 170 "Local interconnect width < %d (LI 1)"
5128 width coreli 140 "Core local interconnect width < %d (LI c1)"
5129 spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (LI 3)"
5130 spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (LI c2)"
5131
5132 surround pc/li *li 80 directional \
5133 "Local interconnect overlap of poly contact < %d in one direction (LI 5)"
5134
5135 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
5136 *li,rli 80 directional \
5137 "Local interconnect overlap of diffusion contact < %d in one direction (LI 5)"
5138
5139 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)"
5140
5141#-------------------------------------------------------------
5142# MCON - Contact between local interconnect and metal1
5143#-------------------------------------------------------------
5144
5145 width lic/m1 170 "Mcon width < %d (Mcon 1)"
5146 spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)"
5147
5148 exact_overlap lic/m1
5149
5150#-------------------------------------------------------------
5151# METAL1 -
5152#-------------------------------------------------------------
5153
5154 width *m1,rm1 140 "Metal1 width < %d (Met1 1)"
5155 spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)"
5156 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)"
5157
5158 surround lic/m1 *met1 30 absence_illegal \
5159 "Metal1 overlap of local interconnect contact < %d (Met1 4)"
5160 surround lic/m1 *met1 60 directional \
5161 "Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)"
5162
5163variants (fast),(full)
5164 widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
5165 "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
5166 widespacing *obsm1 3000 allm1 280 touching_ok \
5167 "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
5168
5169variants (full)
5170 cifmaxwidth m1_hole_empty 0 bend_illegal \
5171 "Min area of metal1 holes > 0.14um^2 (Met1 7)"
5172variants *
5173
5174#--------------------------------------------------
5175# VIA1
5176#--------------------------------------------------
5177
5178 width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)"
5179 spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)"
5180 surround v1/m1 *m1 30 directional \
5181 "Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)"
5182 surround v1/m2 *m2 30 directional \
5183 "Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)"
5184
5185 exact_overlap v1/m2
5186
5187#--------------------------------------------------
5188# METAL2 -
5189#--------------------------------------------------
5190
5191 width allm2 140 "Metal2 width < %d (Met2 1)"
5192 spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (Met2 2)"
5193 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)"
5194
5195variants (fast),(full)
5196 widespacing allm2 3000 allm2,obsm2 280 touching_ok \
5197 "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
5198 widespacing obsm2 3000 allm2 280 touching_ok \
5199 "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
5200
5201variants (full)
5202 cifmaxwidth m2_hole_empty 0 bend_illegal \
5203 "Min area of metal2 holes > 0.14um^2 (Met2 7)"
5204variants *
5205
5206#--------------------------------------------------
5207# VIA2
5208#--------------------------------------------------
5209
5210 width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)"
5211
5212 spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)"
5213
5214 surround v2/m2 *m2 45 directional \
5215 "Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)"
5216 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)"
5217
5218 exact_overlap v2/m2
5219
5220#--------------------------------------------------
5221# METAL3 -
5222#--------------------------------------------------
5223
5224 width allm3 300 "Metal3 width < %d (Met3 1)"
5225 spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (Met3 2)"
5226 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)"
5227
5228variants (fast),(full)
5229 widespacing allm3 3000 allm3,obsm3 400 touching_ok \
5230 "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
5231 widespacing obsm3 3000 allm3 400 touching_ok \
5232 "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
5233variants *
5234
5235
5236#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5237#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5238#--------------------------------------------------
5239# VIA3 - Requires METAL5 Module
5240#--------------------------------------------------
5241
5242 width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)"
5243 spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)"
5244 surround v3/m3 *m3 30 directional \
5245 "Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5246 surround v3/m4 *m4 5 absence_illegal \
5247 "Metal4 overlap of Via3 < %d (Met4 3 - Via3 4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5248
5249 exact_overlap v3/m3
5250
5251#-----------------------------
5252# METAL4 - METAL4 Module
5253#-----------------------------
5254
5255variants *
5256
5257 width allm4 300 "Metal4 width < %d (Met4 1)"
5258 spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (Met4 2)"
5259 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)"
5260
5261variants (fast),(full)
5262 widespacing allm4 3000 allm4,obsm4 400 touching_ok \
5263 "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
5264 widespacing obsm4 3000 allm4 400 touching_ok \
5265 "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
5266variants *
5267
5268#--------------------------------------------------
5269# VIA4 - Requires METAL5 Module
5270#--------------------------------------------------
5271
5272 width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)"
5273 spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)"
5274 surround v4/m5 *m5 120 absence_illegal \
5275 "Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)"
5276
5277 exact_overlap v4/m4
5278
5279#-----------------------------
5280# METAL5 - METAL5 Module
5281#-----------------------------
5282
5283 width allm5 1600 "Metal5 width < %d (Met5 1)"
5284 spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)"
5285 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)"
5286
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5287#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5288#endif (METAL5)
5289
5290#ifdef REDISTRIBUTION
5291
5292variants (full)
5293
5294 width metrdl 10000 "RDL width < %d (Rdl 1)"
5295 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (Rdl 2)"
5296 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (Rdl 3)"
5297 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (Rdl 6)"
5298
5299variants *
5300
5301#endif (REDISTRIBUTION)
5302
5303#--------------------------------------------------
5304# NMOS, PMOS
5305#--------------------------------------------------
5306
5307 extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)"
5308 # Except: Note that standard cells allow transistor width minimum 0.36um
5309 width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)"
5310
5311 spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \
5312 "N-tap spacing to field poly < %d (Poly 5)"
5313 spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \
5314 "P-tap spacing to field poly < %d (Poly 5)"
5315
5316 # Full edge rule required to describe FET to butted tap distance
5317 edge4way *psd *ndiff 300 *ndiff *psd 300 \
5318 "Butting P-tap spacing to NMOS gate < %d (Poly 6)"
5319 edge4way *nsd *pdiff 300 *pdiff *nsd 300 \
5320 "Butting N-tap spacing to PMOS gate < %d (Poly 6)"
5321 edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \
5322 "Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)"
5323 edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \
5324 "Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)"
5325
5326 # No LV FETs in HV diff
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5327 spacing pfet,scpfet,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5328 "LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
5329
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5330 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5331 "LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
5332
5333 # No HV FETs in LV diff
5334 spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
5335 "MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
5336
5337 spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
5338 "MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
5339
5340 # Minimum length of MV FETs. Note that this is larger than the minimum
5341 # width (0.29um), so an edge rule is required
5342
5343 edge4way mvndiff mvnfet 500 mvnfet 0 0 \
5344 "MV NMOS minimum length < %d (Poly 13)"
5345
5346 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
5347 "MV Varactor minimum length < %d (Poly 13)"
5348
5349 edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
5350 "MV PMOS minimum length < %d (Poly 13)"
5351
5352#--------------------------------------------------
5353# mrp1 (N+ poly resistor)
5354#--------------------------------------------------
5355
5356 width mrp1 330 "mrp1 resistor width < %d (Poly 3)"
5357
5358#--------------------------------------------------
5359# xhrpoly (P+ poly resistor)
5360#--------------------------------------------------
5361
5362 width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)"
5363 # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
5364
5365#--------------------------------------------------
5366# uhrpoly (P+ poly resistor, 2kOhm/sq)
5367#--------------------------------------------------
5368
5369 width uhrpoly 350 "uhrpoly resistor width < %d"
5370 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
5371 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9)"
5372
5373#------------------------------------
5374# MOS Varactor device rules
5375#------------------------------------
5376
5377 overhang *nsd var,varhvt 250 \
5378 "N-Tap overhang of Varactor < %d (Var 4)"
5379
5380 overhang *mvnsd mvvar 250 \
5381 "N-Tap overhang of Varactor < %d (Var 4)"
5382
5383 width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)"
5384 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)"
5385
5386#ifdef MIM
5387#-----------------------------------------------------------
5388# MiM CAP (CAPM) -
5389#-----------------------------------------------------------
5390
5391 width *mimcap 2000 "MiM cap width < %d (Capm 1)"
5392 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a)"
5393 spacing *mimcap via2/m3 1270 touching_illegal \
5394 "MiM cap spacing to via2 < %d (Capm 5)"
5395 surround *mimcc *mimcap 200 absence_illegal \
5396 "MiM cap must surround MiM cap contact by %d (Capm 4)"
5397 rect_only *mimcap "MiM cap must be rectangular (Capm 7)
5398
5399 surround *mimcap *metal3/m3 140 absence_illegal \
5400 "Metal3 must surround MiM cap by %d (Capm 3)"
5401 spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8)"
5402 spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8)"
5403 # (resolve scaling issue!)
5404 # cifspacing mim_bottom mim_bottom 1200 touching_ok \
5405 # "MiM cap bottom plate spacing < %d (Capm 2b)"
5406
5407 # MiM cap contact rules (VIA3)
5408
5409 width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)"
5410 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4)"
5411 surround mimcc/m4 *m4 5 directional \
5412 "Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4)"
5413 exact_overlap mimcc/m3
5414
5415 width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)"
5416 spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a)"
5417 spacing *mimcap2 via3/m4 1270 touching_illegal \
5418 "MiM cap spacing to via3 < %d (Cap2m 5)"
5419 surround *mim2cc *mimcap2 200 absence_illegal \
5420 "MiM cap must surround MiM cap contact by %d (Cap2m 4)"
5421 rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7)
5422
5423 surround *mimcap2 *metal4/m4 140 absence_illegal \
5424 "Metal4 must surround MiM cap by %d (Cap2m 3)"
5425 spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8)"
5426 spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8)"
5427 # (resolve scaling issue!)
5428 # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
5429 # "MiM2 cap bottom plate spacing < %d (Cap2m 2b)"
5430
5431 # MiM cap contact rules (VIA4)
5432
5433 width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)"
5434 spacing mim2cc mim2cc 420 touching_ok \
5435 "MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4)"
5436 surround mim2cc/m5 *m5 120 absence_illegal \
5437 "Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4)"
5438 exact_overlap mim2cc/m4
5439
5440#endif (MIM)
5441
5442#----------------------------
5443# End DRC style
5444#----------------------------
5445
5446end
5447
5448#----------------------------
5449# LEF format definitions
5450#----------------------------
5451
5452lef
5453
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]5454 masterslice pwell pwell PWELL substrate
5455 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]5456
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5457 routing li li1 LI1 LI li
5458
5459 routing m1 met1 MET1 m1
5460 routing m2 met2 MET2 m2
5461 routing m3 met3 MET3 m3
5462#ifdef METAL5
5463 routing m4 met4 MET4 m4
5464 routing m5 met5 MET5 m5
5465#endif (METAL5)
5466#ifdef REDISTRIBUTION
5467 routing mrdl met6 MET6 m6 MRDL METRDL
5468#endif
5469
5470 cut lic mcon MCON Mcon
5471 cut m2c via via1 VIA VIA1 cont2 via12
5472 cut m3c via2 VIA2 cont3 via23
5473#ifdef METAL5
5474 cut via3 via3 VIA3 cont4 via34
5475 cut via4 via4 VIA4 cont5 via45
5476#endif (METAL5)
5477
5478 obs obsli li1
5479 obs obsm1 met1
5480 obs obsm2 met2
5481 obs obsm3 met3
5482
5483#ifdef METAL5
5484 obs obsm4 met4
5485 obs obsm5 met5
5486#endif (METAL5)
5487#ifdef REDISTRIBUTION
5488 obs obsmrdl met6
5489#endif
5490
5491 obs obslic mcon
5492
5493end
5494
5495#-----------------------------------------------------
5496# Device and Parasitic extraction
5497#-----------------------------------------------------
5498
5499
5500extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5501 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5502 cscale 1
5503 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5504 # dimensions must be in units of microns in the extract file.
5505 # Use extract style "ngspice(si)" to override this and produce
5506 # a file with SI units for length/area.
5507
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5508 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5509 lambda 1E6
5510 variants (si)
5511 lambda 1.0
5512 variants *
5513
5514 units microns
5515 step 7
5516 sidehalo 2
5517
5518 # NOTE: MiM cap layers have been purposely put out of order,
5519 # may want to reconsider.
5520
5521 planeorder dwell 0
5522 planeorder well 1
5523 planeorder active 2
5524 planeorder locali 3
5525 planeorder metal1 4
5526 planeorder metal2 5
5527 planeorder metal3 6
5528#ifdef METAL5
5529 planeorder metal4 7
5530 planeorder metal5 8
5531#ifdef REDISTRIBUTION
5532 planeorder metali 9
5533 planeorder block 10
5534 planeorder comment 11
5535 planeorder cap1 12
5536 planeorder cap2 13
5537#else (!REDISTRIBUTION)
5538 planeorder block 9
5539 planeorder comment 10
5540 planeorder cap1 11
5541 planeorder cap2 12
5542#endif (!REDISTRIBUTION)
5543#else (!METAL5)
5544#ifdef REDISTRIBUTION
5545 planeorder metali 7
5546 planeorder block 8
5547 planeorder comment 9
5548 planeorder cap1 10
5549 planeorder cap2 11
5550#else (!REDISTRIBUTION)
5551 planeorder block 7
5552 planeorder comment 8
5553 planeorder cap1 9
5554 planeorder cap2 10
5555#endif (!REDISTRIBUTION)
5556#endif (!METAL5)
5557
5558 height dnwell -0.1 0.1
5559 height nwell,pwell 0.0 0.2062
5560 height alldiff 0.2062 0.12
5561 height allpoly 0.3262 0.18
5562 height alldiffcont 0.3262 0.61
5563 height pc 0.5062 0.43
5564 height allli 0.9361 0.10
5565 height lic 1.0361 0.34
5566 height allm1 1.3761 0.36
5567 height v1 1.7361 0.27
5568 height allm2 2.0061 0.36
5569 height v2 2.3661 0.42
5570 height allm3 2.7861 0.845
5571#ifdef METAL5
5572 height v3 3.6311 0.39
5573 height allm4 4.0211 0.845
5574 height v4 4.8661 0.505
5575 height allm5 5.3711 1.26
5576 height mimcap 2.4661 0.2
5577 height mimcap2 3.7311 0.2
5578 height mimcc 2.6661 0.12
5579 height mim2cc 3.9311 0.09
5580#ifdef REDISTRIBUTION
5581 height mrdlc 6.6311 5.2523
5582 height mrdl 11.8834 4.0
5583#endif (!REDISTRIBUTION)
5584#endif (!METAL5)
5585
5586 # Antenna check parameters
5587 # Note that checks w/diode diffusion are not modeled
5588 model partial
5589 antenna poly sidewall 50 none
5590 antenna allcont surface 3 none
5591 antenna li sidewall 75 0 450
5592 antenna lic surface 3 0 18
5593 antenna m1,m2,m3 sidewall 400 2600 400
5594 antenna v1 surface 3 0 18
5595 antenna v2 surface 6 0 36
5596#ifdef METAL5
5597 antenna m4,m5 sidewall 400 2600 400
5598 antenna v3,v4 surface 6 0 36
5599#endif (METAL5)
5600
5601 tiedown alldiffnonfet
5602
5603 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
5604
5605# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
5606
5607# Resistances are in milliohms per square
5608# Optional 3rd argument is the corner adjustment fraction
5609# Device values come from trtc.cor (typical corner)
5610 resist (dnwell)/dwell 2200000
5611 resist (pwell)/well 3050000
5612 resist (nwell)/well 1700000
5613 resist (rpw)/well 3050000 0.5
5614 resist (*ndiff,nsd)/active 120000
5615 resist (*pdiff,*psd)/active 197000
5616 resist (*mvndiff,mvnsd)/active 114000
5617 resist (*mvpdiff,*mvpsd)/active 191000
5618
5619 resist ndiffres/active 120000 0.5
5620 resist pdiffres/active 197000 0.5
5621 resist mvndiffres/active 114000 0.5
5622 resist mvpdiffres/active 191000 0.5
5623 resist mrp1/active 48200 0.5
5624 resist xhrpoly/active 319800 0.5
5625 resist uhrpoly/active 2000000 0.5
5626
5627 resist (allpolynonres)/active 48200
5628 resist rmp/active 48200
5629
5630 resist (allli)/locali 12200
5631 resist (allm1)/metal1 125
5632 resist (allm2)/metal2 125
5633 resist (allm3)/metal3 47
5634#ifdef METAL5
5635 resist (allm4)/metal4 47
5636 resist (allm5)/metal5 29
5637#endif (METAL5)
5638#ifdef REDISTRIBUTION
5639 resist mrdl/metali 5
5640#endif (REDISTRIBUTION)
5641
5642 contact ndc,nsc 15000
5643 contact pdc,psc 15000
5644 contact mvndc,mvnsc 15000
5645 contact mvpdc,mvpsc 15000
5646 contact pc 15000
5647 contact lic 152000
5648 contact m2c 4500
5649 contact m3c 3410
5650#ifdef METAL5
5651#ifdef MIM
5652 contact mimcc 4500
5653 contact mim2cc 3410
5654#endif (MIM)
5655 contact via3 3410
5656 contact via4 380
5657#endif (METAL5)
5658#ifdef REDISTRIBUTION
5659 contact mrdlc 6
5660#endif (REDISTRIBUTION)
5661
5662#-------------------------------------------------------------------------
5663# Parasitic capacitance values: Use document (...)
5664#-------------------------------------------------------------------------
5665# This uses the new "default" definitions that determine the intervening
5666# planes from the planeorder stack, take care of the reflexive sideoverlap
5667# definitions, and generally clean up the section and make it more readable.
5668#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5669# Also uses "units microns" statement. All values are taken from the
5670# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5671# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5672#-------------------------------------------------------------------------
5673# Remember that device capacitances to substrate are taken care of by the
5674# models. Thus, active and poly definitions ignore all "fet" types.
5675# fet types are excluded when computing parasitic capacitance to
5676# active from layers above them because poly is a shield; fet types are
5677# included for parasitics from layers above to poly. Resistor types
5678# should be removed from all parasitic capacitance calculations, or else
5679# they just create floating caps. Technically, the capacitance probably
5680# should be split between the two terminals. Unsure of the correct model.
5681#-------------------------------------------------------------------------
5682
5683#n-well
5684# NOTE: This value not found in PEX files
5685defaultareacap nwell well 120
5686
5687#n-active
5688# Rely on device models to capture *ndiff area cap
5689# Do not extract parasitics from resistors
5690# defaultareacap allnactivenonfet active 790
5691# defaultperimeter allnactivenonfet active 280
5692
5693#p-active
5694# Rely on device models to capture *pdiff area cap
5695# Do not extract parasitics from resistors
5696# defaultareacap allpactivenonfet active 810
5697# defaultperimeter allpactivenonfet active 300
5698
5699#poly
5700# Do not extract parasitics from resistors
5701# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5702# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5703# defaultperimeter allpolynonfet active 57
5704
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5705 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5706 defaultareacap *poly active nwell,obswell,pwell well 106
5707 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5708
5709#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5710 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5711 defaultareacap allli locali nwell,obswell,pwell well 37
5712 defaultperimeter allli locali nwell,obswell,pwell well 55
5713 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5714
5715#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5716 defaultoverlap allli locali allactivenonfet active 37
5717 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5718
5719#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5720 defaultoverlap allli locali allpolynonres active 94
5721 defaultsideoverlap allli locali allpolynonres active 52
5722 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5723
5724#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5725 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5726 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5727 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5728 defaultoverlap allm1 metal1 nwell well 26
5729
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5730#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5731 defaultoverlap allm1 metal1 allactivenonfet active 26
5732 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5733
5734#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5735 defaultoverlap allm1 metal1 allpolynonres active 45
5736 defaultsideoverlap allm1 metal1 allpolynonres active 47
5737 defaultsideoverlap *poly active allm1 metal1 17
5738
5739#metal1->locali
5740 defaultoverlap allm1 metal1 allli locali 114
5741 defaultsideoverlap allm1 metal1 allli locali 59
5742 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5743
5744#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5745 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5746 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5747 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5748 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5749
5750#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5751 defaultoverlap allm2 metal2 allactivenonfet active 17
5752 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5753
5754#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5755 defaultoverlap allm2 metal2 allpolynonres active 24
5756 defaultsideoverlap allm2 metal2 allpolynonres active 41
5757 defaultsideoverlap *poly active allm2 metal2 11
5758
5759#metal2->locali
5760 defaultoverlap allm2 metal2 allli locali 38
5761 defaultsideoverlap allm2 metal2 allli locali 46
5762 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5763
5764#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5765 defaultoverlap allm2 metal2 allm1 metal1 134
5766 defaultsideoverlap allm2 metal2 allm1 metal1 67
5767 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5768
5769#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5770 defaultsidewall allm3 metal3 63
5771 defaultoverlap allm3 metal3 nwell well 12
5772 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5773 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5774
5775#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5776 defaultoverlap allm3 metal3 allactive active 12
5777 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5778
5779#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5780 defaultoverlap allm3 metal3 allpolynonres active 16
5781 defaultsideoverlap allm3 metal3 allpolynonres active 44
5782 defaultsideoverlap *poly active allm3 metal3 9
5783
5784#metal3->locali
5785 defaultoverlap allm3 metal3 allli locali 21
5786 defaultsideoverlap allm3 metal3 allli locali 47
5787 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5788
5789#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5790 defaultoverlap allm3 metal3 allm1 metal1 35
5791 defaultsideoverlap allm3 metal3 allm1 metal1 55
5792 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5793
5794#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5795 defaultoverlap allm3 metal3 allm2 metal2 86
5796 defaultsideoverlap allm3 metal3 allm2 metal2 70
5797 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5798
5799#ifdef METAL5
5800#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5801 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5802# defaultareacap alltopm metal4 well 6
5803 areacap allm4/m4 8
5804 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5805 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5806
5807#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5808 defaultoverlap allm4 metal4 allactivenonfet active 8
5809 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5810
5811#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5812 defaultoverlap allm4 metal4 allpolynonres active 10
5813 defaultsideoverlap allm4 metal4 allpolynonres active 38
5814 defaultsideoverlap *poly active allm4 metal4 6
5815
5816#metal4->locali
5817 defaultoverlap allm4 metal4 allli locali 12
5818 defaultsideoverlap allm4 metal4 allli locali 40
5819 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5820
5821#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5822 defaultoverlap allm4 metal4 allm1 metal1 15
5823 defaultsideoverlap allm4 metal4 allm1 metal1 43
5824 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5825
5826#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5827 defaultoverlap allm4 metal4 allm2 metal2 20
5828 defaultsideoverlap allm4 metal4 allm2 metal2 46
5829 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5830
5831#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5832 defaultoverlap allm4 metal4 allm3 metal3 84
5833 defaultsideoverlap allm4 metal4 allm3 metal3 71
5834 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5835
5836#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5837 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5838# defaultareacap allm5 metal5 well 6
5839 areacap allm5/m5 6
5840 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5841 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5842
5843#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5844 defaultoverlap allm5 metal5 allactivenonfet active 6
5845 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5846
5847#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5848 defaultoverlap allm5 metal5 allpolynonres active 7
5849 defaultsideoverlap allm5 metal5 allpolynonres active 40
5850 defaultsideoverlap *poly active allm5 metal5 6
5851
5852#metal5->locali
5853 defaultoverlap allm5 metal5 allli locali 8
5854 defaultsideoverlap allm5 metal5 allli locali 41
5855 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5856
5857#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5858 defaultoverlap allm5 metal5 allm1 metal1 9
5859 defaultsideoverlap allm5 metal5 allm1 metal1 43
5860 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5861
5862#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5863 defaultoverlap allm5 metal5 allm2 metal2 11
5864 defaultsideoverlap allm5 metal5 allm2 metal2 46
5865 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5866
5867#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5868 defaultoverlap allm5 metal5 allm3 metal3 20
5869 defaultsideoverlap allm5 metal5 allm3 metal3 54
5870 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5871
5872#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5873 defaultoverlap allm5 metal5 allm4 metal4 68
5874 defaultsideoverlap allm5 metal5 allm4 metal4 83
5875 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5876#endif (METAL5)
5877
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5878#ifdef REDISTRIBUTION
5879#endif (REDISTRIBUTION)
5880
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5881# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5882
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5883variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5884
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5885 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
5886 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5887 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5888 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5889 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
5890 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5891 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
5892 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5893 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt \
5894 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5895
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5896 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5897 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5898 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5899 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5900 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
5901 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5902
5903 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5904 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5905 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5906 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
5907 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
5908 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5909 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5910 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5911 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5912 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5913 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5914 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5915 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5916 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5917
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5918 # Extended drain devices (must appear before the regular devices)
5919 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5920 dnwell pwell,space/w error l=l w=w
5921 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5922 dnwell pwell,space/w error l=l w=w
5923 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5924 pwell,space/w nwell error l=l w=w
5925
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5926 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
5927 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
5928 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
5929 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5930 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
5931 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5932
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5933 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a1=area
5934 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a1=area
5935
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5936 device rsubcircuit sky130_fd_pr__res_generic_po rmp \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5937 *poly space/w,pwell,nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5938 device rsubcircuit sky130_fd_pr__res_generic_l1 rli1 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5939 *li,coreli space/w,pwell,nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5940 device rsubcircuit sky130_fd_pr__res_generic_m1 rmetal1 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5941 *metal1 space/w,pwell,nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5942 device rsubcircuit sky130_fd_pr__res_generic_m2 rmetal2 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5943 *metal2 space/w,pwell,nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5944 device rsubcircuit sky130_fd_pr__res_generic_m3 rmetal3 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5945 *metal3 space/w,pwell,nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5946#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5947 device rsubcircuit sky130_fd_pr__res_generic_m4 rm4 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5948 *m4 space/w,pwell,nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5949 device rsubcircuit sky130_fd_pr__res_generic_m5 rm5 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5950 *m5 space/w,pwell,nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5951#endif (METAL5)
5952
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5953 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5954 xpc pwell,space/w error +res0p35 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5955 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5956 xpc pwell,space/w error +res0p69 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5957 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5958 xpc pwell,space/w error +res1p41 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5959 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5960 xpc pwell,space/w error +res2p85 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5961 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5962 xpc pwell,space/w error +res5p73 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5963 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5964 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5965 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5966 xpc pwell,space/w error +res0p35 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5967 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5968 xpc pwell,space/w error +res0p69 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5969 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5970 xpc pwell,space/w error +res1p41 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5971 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5972 xpc pwell,space/w error +res2p85 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5973 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5974 xpc pwell,space/w error +res5p73 l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5975 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5976 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5977
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5978 device rsubcircuit sky130_fd_pr__res_generic_po mrp1 \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5979 *poly pwell,space/w error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5980
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5981 device rsubcircuit sky130_fd_pr_res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5982 *ndiff pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5983 device rsubcircuit sky130_fd_pr_res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5984 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5985 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5986 pwell dnwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5987
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5988 device rsubcircuit mrdn_hv mvndiffres \
5989 *mvndiff pwell,space/w error l=l w=w
5990 device rsubcircuit mrdp_hv mvpdiffres \
5991 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5992
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5993 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5994 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5995 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5996 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5997 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5998 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]5999 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6000 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6001
6002 # These are parasitic devices
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6003 device msubcircuit sky130_fd_pr__diode_pw2nd_lvt *ndiodelvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6004 pwell,space/w a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6005 device subcircuit sky130_fd_pr__diode_pd2nw_lvt *pdiodelvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6006 nwell a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6007 device subcircuit sky130_fd_pr_diode_pd2nw_hvt *pdiodehvt \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6008 nwell a=area
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6009 device msubcircuit sky130_fd_pr__diode_pw2nd_nvt *nndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6010 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6011
6012#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6013 device subcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap m3 nwell,pwell,space/w error a=area s=subs
6014 device subcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=area s=subs
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6015#endif (MIM)
6016
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6017 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6018
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6019 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
6020 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
6021 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
6022 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
6023 device mosfet sky130_fd_pr__pfet_01v8_hvt pfethvt pdiff,pdiffres,pdc nwell
6024 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
6025 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
6026 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6027 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6028 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
6029 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
6030 pwell,space/w
6031
6032 # Extended drain devices (must appear before the regular devices)
6033 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6034 dnwell pwell,space/w error
6035 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6036 dnwell pwell,space/w error
6037 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6038 pwell,space/w nwell error
6039
6040 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
6041 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
6042 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6043
6044 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6045 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
6046 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
6047 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6048
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6049 device resistor sky130_fd_pr__res_generic_po rmp *poly
6050 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6051 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6052 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6053 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6054#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6055 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6056 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6057#endif (METAL5)
6058
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6059 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
6060 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
6061 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
6062 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
6063 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
6064 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
6065 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
6066 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
6067 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
6068 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
6069 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
6070 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
6071 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
6072 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
6073 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6074 device resistor mrdn_hv mvndiffres *mvndiff
6075 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6076 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6077
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6078 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
6079 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
6080 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
6081 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6082
6083 # These are parasitic devices
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6084 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
6085 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
6086 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
6087 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6088
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6089 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a1=area
6090 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a1=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6091
6092#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame^]6093 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
6094 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6095#endif (MIM)
6096
6097end
6098
6099#-----------------------------------------------------
6100# Wiring tool definitions
6101#-----------------------------------------------------
6102
6103wiring
6104 # All wiring values are in nanometers
6105 scalefactor 10
6106
6107 contact lic 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6108 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6109 contact v2 280 m2 0 45 m3 25 0
6110#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]6111 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6112 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6113#endif (METAL5)
6114
6115 contact pc 170 poly 50 80 li 0 80
6116 contact pdc 170 pdiff 40 60 li 0 80
6117 contact ndc 170 ndiff 40 60 li 0 80
6118 contact psc 170 psd 40 60 li 0 80
6119 contact nsc 170 nsd 40 60 li 0 80
6120
6121end
6122
6123#-----------------------------------------------------
6124# Plain old router. . .
6125#-----------------------------------------------------
6126
6127router
6128end
6129
6130#------------------------------------------------------------
6131# Plowing (restored in magic 8.2, need to fill this section)
6132#------------------------------------------------------------
6133
6134plowing
6135end
6136
6137#-----------------------------------------------------------------
6138# No special plot layers defined (use default PNM color choices)
6139#-----------------------------------------------------------------
6140
6141plot
6142 style pnm
6143 default
6144 draw fillblock no_color_at_all
6145 draw nwell cwell
6146end
6147