Google Git
Sign in
foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 8aa46807572dd985884e55898cd90bf20342156a / . / sky130 / magic / sky130.tech
blob: e68cad41ba11d159d4cb9837ca6ca739ea40b325 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
54# sky130_fd_pr__nfet_03v3_nvt --- native nFET
55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]66# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
144
145# Wells
146 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]147 well pwell,pw
148 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]149 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]152
153# Transistors
154 active nmos,ntransistor,nfet
155 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]156 -active npd,npdfet,sramnfet
157 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]158 active pmos,ptransistor,pfet
159 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]160 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]161 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]162 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]163 active mvnmos,mvntransistor,mvnfet
164 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]165 active mvnnmos,mvnntransistor,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]166 -active mvnmosesd,mvntransistoresd,mvnfetesd
167 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]168 active varactor,varact,var
169 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]170
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]171 active pmoslvt,pfetlvt
172 active pmosmvt,pfetmvt
173 active pmoshvt,pfethvt
174 active nmoslvt,nfetlvt
175 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]176 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]177 -active sramnvar,corenvar,corenvaractor
178 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]179
180# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]181 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182 active ndiff,ndiffusion,ndif
183 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]184 active mvndiff,mvndiffusion,mvndif
185 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]186 active ndiffc,ndcontact,ndc
187 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]188 active mvndiffc,mvndcontact,mvndc
189 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]190 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
191 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
192 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
193 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
194 active psubdiffcont,psubstratepcontact,psc,ptapc
195 active nsubdiffcont,nsubstratencontact,nsc,ntapc
196 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
197 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]198 -active obsactive
199 -active mvobsactive
200
201# Poly
202 active poly,p,polysilicon
203 active polycont,pc,pcontact,polycut,polyc
204 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]205 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]206
207# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]208 active npolyres,npres,mrp1
209 active ppolyres,ppres,xhrpoly
210 active xpolyres,xpres,xres,uhrpoly
211 active ndiffres,rnd,rdn,rndiff
212 active pdiffres,rpd,rdp,rpdiff
213 active mvndiffres,mvrnd,mvrdn,mvrndiff
214 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
215 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]216
217# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]218 active pdiode,pdi
219 active ndiode,ndi
220 active nndiode,nndi
221 active pdiodec,pdic
222 active ndiodec,ndic
223 active nndiodec,nndic
224 active mvpdiode,mvpdi
225 active mvndiode,mvndi
226 active mvpdiodec,mvpdic
227 active mvndiodec,mvndic
228 active pdiodelvt,pdilvt
229 active pdiodehvt,pdihvt
230 active ndiodelvt,ndilvt
231 active pdiodelvtc,pdilvtc
232 active pdiodehvtc,pdihvtc
233 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]234
235# Local Interconnect
236 locali locali,li1,li
237 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]238 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]239 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]240 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]241 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]242 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]243
244# Metal 1
245 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]246 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]247 metal1 via1,m2contact,m2cut,m2c,via,v,v1
248 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]249 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]250 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]251
252# Metal 2
253 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]254 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]255 metal2 via2,m3contact,m3cut,m3c,v2
256 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]257 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]258
259# Metal 3
260 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]261 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]262 -metal3 obsm3
263#ifdef METAL5
264 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]265 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]266
267#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 cap1 mimcap,mim,capm
269 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]270#endif
271
272# Metal 4
273 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]274 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]275 -metal4 obsm4
276 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]277 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]278
279#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]280 cap2 mimcap2,mim2,capm2
281 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]282#endif
283
284# Metal 5
285 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]286 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]287 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]288 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]289#endif (METAL5)
290
291#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]292 metal5 mrdlcontact,mrdlc,pi1
293 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]294 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]295 metali pi2
296 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]297#endif (REDISTRIBUTION)
298
299# Miscellaneous
300 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]301 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]302 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]303 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]304# fixed resistor width identifiers
305 -comment res0p35
306 -comment res0p69
307 -comment res1p41
308 -comment res2p85
309 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]310
311end
312
313#-----------------------------------------------------
314# Magic contact types
315#-----------------------------------------------------
316
317contact
318 pc poly locali
319 ndc ndiff locali
320 pdc pdiff locali
321 nsc nsd locali
322 psc psd locali
323 ndic ndiode locali
324 ndilvtc ndiodelvt locali
325 nndic nndiode locali
326 pdic pdiode locali
327 pdilvtc pdiodelvt locali
328 pdihvtc pdiodehvt locali
329 xpc xpc locali
330
331 mvndc mvndiff locali
332 mvpdc mvpdiff locali
333 mvnsc mvnsd locali
334 mvpsc mvpsd locali
335 mvndic mvndiode locali
336 mvpdic mvpdiode locali
337
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]338 mcon locali metal1
339 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]340
341 via1 metal1 metal2
342 via2 metal2 metal3
343#ifdef METAL5
344 via3 metal3 metal4
345 via4 metal4 metal5
346#endif (METAL5)
347 stackable
348
349#ifdef METAL5
350#ifdef MIM
351 # MiM cap contacts are not stackable!
352 mimcc mimcap metal4
353 mim2cc mimcap2 metal5
354#endif (MIM)
355
356 padl m1 m2 m3 m4 m5 glass
357#else
358 padl m1 m2 m3 glass
359#endif (!METAL5)
360
361#ifdef REDISTRIBUTION
362 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]363 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]364#endif (REDISTRIBUTION)
365end
366
367#-----------------------------------------------------
368# Layer aliases
369#-----------------------------------------------------
370
371aliases
372
373 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]374 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]375
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]376 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,nsonos
377 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]378 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]379 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]380 allfetsspecial scnfet,scpfet,scpfethvt
381 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]382 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]383
384 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
385 allnactive allnactivenonfet,allnfets
386 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388
389 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
390 allpactive allpactivenonfet,allpfets
391 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]392 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]393
394 allactivenonfet allnactivenonfet,allpactivenonfet
395 allactive allactivenonfet,allfets
396
397 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
398
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]399 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]400 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]401 alldifflv allndifflv,allpdifflv
402 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
403 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
404 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
405
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]406 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
407 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]408 alldiffmv allndiffmv,allpdiffmv
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]409 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
410 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]411 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
412 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
413 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
414 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
415
416 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]417 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]418
419 allpolyres mrp1,xhrpoly,uhrpoly,rmp
420 allpolynonfet *poly,allpolyres,xpc
421 allpolynonres *poly,allfets,xpc
422
423 allpoly allpolynonfet,allfets
424 allpolynoncap *poly,xpc,allfets,allpolyres
425
426 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
427 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
428 allndiffcontmv mvndc,mvnsc,mvndic
429 allpdiffcontmv mvpdc,mvpsc,mvpdic
430 allndiffcont allndiffcontlv,allndiffcontmv
431 allpdiffcont allpdiffcontlv,allpdiffcontmv
432 alldiffcontlv allndiffcontlv,allpdiffcontlv
433 alldiffcontmv allndiffcontmv,allpdiffcontmv
434 alldiffcont alldiffcontlv,alldiffcontmv
435
436 allcont alldiffcont,pc
437
438 allres allpolyres,allactiveres
439
440 allli *locali,coreli,rli
441 allm1 *m1,rm1
442 allm2 *m2,rm2
443 allm3 *m3,rm3
444#ifdef METAL5
445 allm4 *m4,rm4
446 allm5 *m5,rm5
447#endif (METAL5)
448
449 allpad padl
450
451 psub pwell
452
453end
454
455#-----------------------------------------------------
456# Layer drawing styles
457#-----------------------------------------------------
458
459styles
460 styletype mos
461 dnwell cwell
462 nwell nwell
463 pwell pwell
464 rpwell pwell ptransistor_stripes
465 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]466 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]467 pdiff pdiffusion
468 nsd ndiff_in_nwell
469 psd pdiff_in_pwell
470 nfet ntransistor ntransistor_stripes
471 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]472 npass ntransistor ntransistor_stripes
473 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]474 pfet ptransistor ptransistor_stripes
475 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]476 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]477 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]478 var polysilicon ndiff_in_nwell
479 ndc ndiffusion metal1 contact_X'es
480 pdc pdiffusion metal1 contact_X'es
481 nsc ndiff_in_nwell metal1 contact_X'es
482 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]483 corenvar polysilicon ndiff_in_nwell
484 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]485
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]486 pnp nwell ntransistor_stripes
487 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]488
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]489 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]490 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]491 pfethvt ptransistor ptransistor_stripes implant2
492 nfetlvt ntransistor ntransistor_stripes implant1
493 nsonos ntransistor implant3
494 varhvt polysilicon ndiff_in_nwell implant2
495
496 mvndiff ndiffusion hvndiff_mask
497 mvpdiff pdiffusion hvpdiff_mask
498 mvnsd ndiff_in_nwell hvndiff_mask
499 mvpsd pdiff_in_pwell hvpdiff_mask
500 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]501 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]502 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
503 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]504 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]505 mvvar polysilicon ndiff_in_nwell hvndiff_mask
506 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
507 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
508 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
509 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
510
511 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]512 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]513 pc polysilicon metal1 contact_X'es
514 npolyres polysilicon silicide_block nselect2
515 ppolyres polysilicon silicide_block pselect2
516 xpc polysilicon pselect2 metal1 contact_X'es
517 rmp polysilicon poly_resist_stripes
518
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]519 res0p35 implant1
520 res0p69 implant1
521 res1p41 implant1
522 res2p85 implant1
523 res5p73 implant1
524
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]525 pdiode pdiffusion pselect2
526 ndiode ndiffusion nselect2
527 pdiodec pdiffusion pselect2 metal1 contact_X'es
528 ndiodec ndiffusion nselect2 metal1 contact_X'es
529
530 nndiode ndiffusion nselect2 implant3
531 ndiodelvt ndiffusion nselect2 implant1
532 pdiodelvt pdiffusion pselect2 implant1
533 pdiodehvt pdiffusion pselect2 implant2
534 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
535 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
536 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
537
538 mvpdiode pdiffusion pselect2 hvpdiff_mask
539 mvndiode ndiffusion nselect2 hvndiff_mask
540 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
541 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
542 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
543
544 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]545 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]546 coreli metal1
547 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]548 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]549 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]550 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]551
552 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]553 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]554 rm1 metal2 poly_resist_stripes
555 obsm1 metal2
556 m2c metal2 metal3 via2arrow
557 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]558 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]559 rm2 metal3 poly_resist_stripes
560 obsm2 metal3
561 m3c metal3 metal4 via3alt
562 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]563 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]564 rm3 metal4 poly_resist_stripes
565 obsm3 metal4
566#ifdef METAL5
567#ifdef MIM
568 mimcap metal3 mems
569 mimcc metal3 contact_X'es mems
570 mimcap2 metal4 mems
571 mim2cc metal4 contact_X'es mems
572#endif (MIM)
573 via3 metal4 metal5 via4
574 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]575 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]576 rm4 metal5 poly_resist_stripes
577 obsm4 metal5
578 via4 metal5 metal6 via5
579 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]580 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]581 rm5 metal6 poly_resist_stripes
582 obsm5 metal6
583#endif (METAL5)
584#ifdef REDISTRIBUTION
585 mrdlc metal6 metal7 via6
586 metalrdl metal7
587 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]588 ubm metal8
589 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]590#endif (REDISTRIBUTION)
591
592 glass overglass
593 mrp1 poly_resist poly_resist_stripes
594 xhrpoly poly_resist silicide_block
595 uhrpoly poly_resist
596 ndiffres ndiffusion ndop_stripes
597 pdiffres pdiffusion pdop_stripes
598 mvndiffres ndiffusion hvndiff_mask ndop_stripes
599 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
600 comment comment
601 error_p error_waffle
602 error_s error_waffle
603 error_ps error_waffle
604 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]605 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]606
607 obswell cwell
608 obsactive implant4
609
610#ifndef METAL5
611 padl metal4 via4 overglass
612#else
613 padl metal6 via6 overglass
614#endif
615
616 magnet substrate_field_implant
617 rotate via3alt
618 fence via5
619end
620
621#-----------------------------------------------------
622# Special paint/erase rules
623#-----------------------------------------------------
624
625compose
626 compose nfet poly ndiff
627 compose pfet poly pdiff
628 compose var poly nsd
629
630 compose mvnfet poly mvndiff
631 compose mvpfet poly mvpdiff
632 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]633
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]634 paint obsmcon locali via1
635 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]636
637 paint ndc nwell pdc
638 paint nfet nwell pfet
639 paint scnfet nwell scpfet
640 paint ndiff nwell pdiff
641 paint psd nwell nsd
642 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]643 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]644
645 paint pdc pwell ndc
646 paint pfet pwell nfet
647 paint scpfet pwell scnfet
648 paint pdiff pwell ndiff
649 paint nsd pwell psd
650 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]651 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]652
653 paint pdc coreli pdc
654 paint ndc coreli ndc
655 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]656 paint nsc coreli nsc
657 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]658 paint viali coreli viali
659
660 paint coreli pdc pdc
661 paint coreli ndc ndc
662 paint coreli pc pc
663 paint coreli nsc nsc
664 paint coreli psc psc
665 paint coreli viali viali
666
667#ifdef METAL5
668 paint m4 obsm4 m4
669 paint m5 obsm5 m5
670#endif (METAL5)
671end
672
673#-----------------------------------------------------
674# Electrical connectivity
675#-----------------------------------------------------
676
677connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]678 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
679 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]680 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]681 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]682 *m2,m2fill *m2,m2fill
683 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]684#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]685 *m4,m4fill *m4,m4fill
686 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]687#ifdef MIM
688 *mimcap *mimcap
689 *mimcap2 *mimcap2
690#endif (MIM)
691#endif (METAL5)
692 allnactivenonfet allnactivenonfet
693 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]694 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]695#ifdef REDISTRIBUTION
696 # RDL connects to m5 (i.e., padl) through glass cut
697 *mrdl *mrdl
698 glass metrdl
699#endif (REDISTRIBUTION)
700end
701
702#-----------------------------------------------------
703# CIF/GDS output layer definitions
704#-----------------------------------------------------
705# NOTE: All values in this section MUST be multiples of 25
706# or else magic will scale below the allowed layout grid size
707
708cifoutput
709
710#----------------------------------------------------------------
711style gdsii
712# NOTE: This section is used for actual GDS output
713#----------------------------------------------------------------
714 scalefactor 10 nanometers
715 options calma-permissive-labels
716 gridlimit 5
717
718#----------------------------------------------------------------
719# Create a temp layer from the cell bounding box for use in
720# generating ID layers. Note that "boundary", unlike "bbox",
721# requires the FIXED_BBOX property (abutment box) in the cell.
722#----------------------------------------------------------------
723 templayer CELLBOUND
724 boundary
725
726#----------------------------------------------------------------
727# BOUND
728#----------------------------------------------------------------
729 layer BOUND CELLBOUND
730 calma 235 4
731
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]732#----------------------------------------------------------------
733# DNWELL
734#----------------------------------------------------------------
735
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]736 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]737 calma 64 18
738
739 layer PWRES rpw
740 and dnwell
741 calma 64 13
742
743#----------------------------------------------------------------
744# NWELL
745#----------------------------------------------------------------
746
747 layer NWELL allnwell
748 bloat-all rpw dnwell
749 and-not rpw,pwell
750 calma 64 20
751
752 layer WELLTXT
753 labels allnwell noport
754 calma 64 16
755
756 layer WELLPIN
757 labels allnwell port
758 calma 64 5
759
760#----------------------------------------------------------------
761# SUB (text/port only)
762#----------------------------------------------------------------
763
764 layer SUBTXT
765 labels pwell noport
766 calma 122 16
767
768 layer SUBPIN
769 labels pwell port
770 calma 64 59
771
772#----------------------------------------------------------------
773# DIFF
774#----------------------------------------------------------------
775
776 layer DIFF allnactivenontap,allpactivenontap,allactiveres
777 labels allnactivenontap,allpactivenontap
778 calma 65 20
779
780#----------------------------------------------------------------
781# TAP
782#----------------------------------------------------------------
783
784 layer TAP allnactivetap,allpactivetap
785 labels allnactivetap,allpactivetap
786 calma 65 44
787
788#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]789# FOM
790#----------------------------------------------------------------
791
792 layer FOMFILL fomfill
793 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]794 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]795
796#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]797# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]798#----------------------------------------------------------------
799
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]800 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]801 grow 15
802 or xhrpoly,uhrpoly,xpc
803 grow 110
804 bloat-or allpactivetap * 125 allnactivenontap 0
805 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]806
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]807 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]808 grow 125
809 bloat-or allnactivetap * 125 allpactivenontap 0
810 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]811
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]812 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]813 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]814 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]815
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]816 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]817 grow 185
818 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]819 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]820 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]821 calma 94 20
822
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]823 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]824 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]825 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]826
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]827 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]828 grow 185
829 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]830 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]831 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]832 calma 93 44
833
834#----------------------------------------------------------------
835# LVTN
836#----------------------------------------------------------------
837
838 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
839 grow 180
840 bridge 380 380
841 grow 185
842 shrink 185
843 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]844 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]845 calma 125 44
846
847#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]848# HVTR
849#----------------------------------------------------------------
850
851 layer HVTR pfetmvt
852 grow 180
853 bridge 380 380
854 grow 185
855 shrink 185
856 close 265000
857 calma 18 20
858
859#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]860# HVTP
861#----------------------------------------------------------------
862
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]863 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]864 grow 180
865 bridge 380 380
866 grow 185
867 shrink 185
868 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]869 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]870 calma 78 44
871
872#----------------------------------------------------------------
873# SONOS
874#----------------------------------------------------------------
875
876 layer SONOS nsonos
877 grow 100
878 grow-min 410
879 bridge 500 410
880 grow 250
881 shrink 250
882 calma 80 20
883
884#----------------------------------------------------------------
885# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]886# coreli layer indicates a cell needing COREID. Also, devices
887# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]888#----------------------------------------------------------------
889
890 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]891 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]892 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]893 calma 81 2
894
895#----------------------------------------------------------------
896# STDCELL applies to all cells containing scnfet or scpfet.
897#----------------------------------------------------------------
898
899 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]900 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]901 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]902 calma 81 4
903
904#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]905# ESDID is a marker layer for ESD devices in the padframe I/O.
906#----------------------------------------------------------------
907
908 layer ESDID
909 bloat-all mvnfetesd *mvndiff,*poly
910 bloat-all mvpfetesd *mvpdiff,*poly
911 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]912 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]913 calma 81 19
914
915#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]916# NPNID and PNPID apply to bipolar transistors
917#----------------------------------------------------------------
918
919 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]920 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]921 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]922 calma 82 20
923
924 templayer pnparea pnp
925 grow 400
926
927 layer PNPID
928 bloat-all pnparea *psd
929 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]930 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]931 calma 82 44
932
933#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]934# RPM
935#----------------------------------------------------------------
936
937 layer RPM
938 bloat-all xhrpoly xpc
939 grow 200
940 grow-min 1270
941 grow 420
942 shrink 420
943 calma 86 20
944
945#----------------------------------------------------------------
946# URPM (2kOhms/sq. poly implant)
947#----------------------------------------------------------------
948
949 layer URPM
950 bloat-all uhrpoly xpc
951 grow 200
952 grow-min 1270
953 grow 420
954 shrink 420
955 calma 79 20
956
957#----------------------------------------------------------------
958# LDNTM (Tip implant for SONOS FETs)
959#----------------------------------------------------------------
960
961 layer LDNTM
962 bloat-all nsonos *ndiff
963 grow 185
964 grow 345
965 shrink 345
966 calma 11 44
967
968#----------------------------------------------------------------
969# HVNTM (Tip implant for MV ndiff devices)
970#----------------------------------------------------------------
971
972 templayer hvntm_block *mvpsd
973 grow 185
974
975 layer HVNTM
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]976 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]977 bloat-all mvvaractor *mvnsd
978 and-not hvntm_block
979 grow 185
980 grow 345
981 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]982 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]983 calma 125 20
984
985#----------------------------------------------------------------
986# POLY
987#----------------------------------------------------------------
988
989 layer POLY allpoly
990 calma 66 20
991
992 layer POLYTXT
993 labels allpoly noport
994 calma 66 16
995
996 layer POLYPIN
997 labels allpoly port
998 calma 66 5
999
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1000 layer POLYFILL polyfill
1001 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1002 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1003
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1004#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1005# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1006#----------------------------------------------------------------
1007
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1008 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1009 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1010 bloat-all alldiffmv nwell
1011 grow 345
1012 shrink 345
1013
1014 templayer large_ptap_mv thkox_area
1015 shrink 420
1016 grow 420
1017
1018 templayer small_ptap_mv thkox_area
1019 and-not large_ptap_mv
1020 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1021 grow-min 840
1022
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1023 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1024 bridge 700 600
1025 grow 345
1026 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1027 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1028 calma 75 20
1029
1030#----------------------------------------------------------------
1031# CONT (LICON)
1032#----------------------------------------------------------------
1033
1034 layer CONT allcont
1035 squares-grid 0 170 170
1036 calma 66 44
1037
1038 # Contact for pres is different than other LICON contacts
1039 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1040 templayer xpc_horiz xpc
1041 shrink 1007
1042 grow 1007
1043
1044 layer CONT xpc
1045 and-not xpc_horiz
1046 # Force long edge vertical for contacts narrower than 2um
1047 # Minimum space is 350 but 520 satisfies no. of contacts rule
1048 slots 80 190 520 80 2000 350
1049 calma 66 44
1050
1051 layer CONT xpc
1052 and xpc_horiz
1053 # Force long edge vertical for contacts wider than 2um
1054 # Minimum space is 350 but 520 satisfies no. of contacts rule
1055 slots 80 2000 350 80 190 520
1056 calma 66 44
1057
1058#----------------------------------------------------------------
1059# NPC (Nitride poly cut)
1060# surrounds CONT (LICON) on poly only (i.e., pc)
1061#----------------------------------------------------------------
1062
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1063 # Avoids a common case of NPC bridges too close to other LICON shapes.
1064 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1065 grow 90
1066
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1067 layer NPC pc
1068 squares-grid 0 170 170
1069 grow 100
1070 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1071 and-not diffcutarea
1072 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1073 grow 130
1074 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1075 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1076 calma 95 20
1077
1078 # NPC is also generated on xhrpoly and uhrpoly resistors
1079
1080 layer NPC xpc,xhrpoly,uhrpoly
1081 # xpc surrounds precision_resistor by 0.095um
1082 grow 95
1083 grow 130
1084 shrink 130
1085 calma 95 20
1086
1087#----------------------------------------------------------------
1088# Device markers
1089#----------------------------------------------------------------
1090
1091 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1092 calma 65 13
1093
1094 layer POLYRES mrp1
1095 calma 66 13
1096
1097 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1098 layer POLYSHORT rmp
1099 calma 66 15
1100
1101 # POLYRES extends to edge of contact cut
1102 layer POLYRES xhrpoly,uhrpoly
1103 grow 60
1104 and xpc
1105 or xhrpoly,uhrpoly
1106 calma 66 13
1107
1108 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1109 # To be done: Expand to include anode, cathode, and guard ring
1110 calma 81 23
1111
1112#----------------------------------------------------------------
1113# LI
1114#----------------------------------------------------------------
1115 layer LI allli
1116 calma 67 20
1117
1118 layer LITXT
1119 labels *locali,coreli noport
1120 calma 67 16
1121
1122 layer LIPIN
1123 labels *locali,coreli port
1124 calma 67 5
1125
1126 layer LIRES rli
1127 labels rli
1128 calma 67 13
1129
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1130 layer LIFILL lifill
1131 labels lifill
1132 calma 56 28
1133
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1134#----------------------------------------------------------------
1135# MCON
1136#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1137 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1138 squares-grid 0 170 190
1139 calma 67 44
1140
1141#----------------------------------------------------------------
1142# MET1
1143#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1144 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1145 calma 68 20
1146
1147 layer MET1TXT
1148 labels allm1 noport
1149 calma 68 16
1150
1151 layer MET1PIN
1152 labels allm1 port
1153 calma 68 5
1154
1155 layer MET1RES rm1
1156 labels rm1
1157 calma 68 13
1158
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1159 layer MET1FILL m1fill
1160 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1161 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1162
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1163#----------------------------------------------------------------
1164# VIA1
1165#----------------------------------------------------------------
1166 layer VIA1 via1
1167 squares-grid 55 150 170
1168 calma 68 44
1169
1170#----------------------------------------------------------------
1171# MET2
1172#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1173 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1174 calma 69 20
1175
1176 layer MET2TXT
1177 labels allm2 noport
1178 calma 69 16
1179
1180 layer MET2PIN
1181 labels allm2 port
1182 calma 69 5
1183
1184 layer MET2RES rm2
1185 labels rm2
1186 calma 69 13
1187
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1188 layer MET2FILL m2fill
1189 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1190 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1191
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1192#----------------------------------------------------------------
1193# VIA2
1194#----------------------------------------------------------------
1195 layer VIA2 via2
1196 squares-grid 40 200 200
1197 calma 69 44
1198
1199#----------------------------------------------------------------
1200# MET3
1201#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1202 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1203 calma 70 20
1204
1205 layer MET3TXT
1206 labels allm3 noport
1207 calma 70 16
1208
1209 layer MET3PIN
1210 labels allm3 port
1211 calma 70 5
1212
1213 layer MET3RES rm3
1214 labels rm3
1215 calma 70 13
1216
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1217 layer MET3FILL m3fill
1218 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1219 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1220
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1221#ifdef METAL5
1222#----------------------------------------------------------------
1223# VIA3
1224#----------------------------------------------------------------
1225 layer VIA3 via3
1226#ifdef MIM
1227 or mimcc
1228#endif (MIM)
1229 squares-grid 60 200 200
1230 calma 70 44
1231
1232#----------------------------------------------------------------
1233# MET4
1234#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1235 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1236 calma 71 20
1237
1238 layer MET4TXT
1239 labels allm4 noport
1240 calma 71 16
1241
1242 layer MET4PIN
1243 labels allm4 port
1244 calma 71 5
1245
1246 layer MET4RES rm4
1247 labels rm4
1248 calma 71 13
1249
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1250 layer MET4FILL m4fill
1251 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1252 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1253
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1254#----------------------------------------------------------------
1255# VIA4
1256#----------------------------------------------------------------
1257 layer VIA4 via4
1258#ifdef MIM
1259 or mim2cc
1260#endif (MIM)
1261 squares-grid 190 800 800
1262 calma 71 44
1263
1264#----------------------------------------------------------------
1265# MET5
1266#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1267 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1268 calma 72 20
1269
1270 layer MET5TXT
1271 labels allm5 noport
1272 calma 72 16
1273
1274 layer MET5PIN
1275 labels allm5 port
1276 calma 72 5
1277
1278 layer MET5RES rm5
1279 labels rm5
1280 calma 72 13
1281
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1282 layer MET5FILL m5fill
1283 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1284 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1285
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1286#endif (METAL5)
1287
1288#ifdef REDISTRIBUTION
1289#----------------------------------------------------------------
1290# RDL
1291#----------------------------------------------------------------
1292 layer RDL *metrdl
1293 calma 74 20
1294
1295 layer RDLTXT
1296 labels *metrdl noport
1297 calma 74 16
1298
1299 layer RDLPIN
1300 labels *metrdl port
1301 calma 74 5
1302
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1303 layer PI1 *metrdl
1304 and padl,glass
1305 # Test only---needs GDS layer number
1306
1307 layer UBM *metrdl
1308 shrink 50000
1309 grow 40000
1310 # Test only---needs GDS layer number
1311
1312 layer PI2 *metrdl
1313 shrink 50000
1314 grow 25000
1315 # Test only---needs GDS layer number
1316
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1317#endif REDISTRIBUTION
1318
1319#----------------------------------------------------------------
1320# GLASS
1321#----------------------------------------------------------------
1322 layer GLASS glass
1323 calma 76 20
1324
1325#ifdef MIM
1326#----------------------------------------------------------------
1327# CAPM
1328#----------------------------------------------------------------
1329 layer CAPM *mimcap
1330 labels mimcap
1331 calma 89 44
1332
1333 layer CAPM2 *mimcap2
1334 labels mimcap2
1335 calma 97 44
1336#endif (MIM)
1337
1338#----------------------------------------------------------------
1339# Chip top level marker for DRC latchup rules to check 15um
1340# distance to taps (otherwise 6um is used)
1341#----------------------------------------------------------------
1342
1343 layer LOWTAPDENSITY
1344 bbox top
1345 # Clear 200um for pads + 50um for required high tap density
1346 # in critical area.
1347 shrink 250000
1348 calma 81 14
1349
1350#----------------------------------------------------------------
1351# FILLBLOCK
1352#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1353 layer FILLOBSFOM obsactive
1354 calma 22 24
1355
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1356 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1357 calma 62 24
1358
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1359 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1360 calma 105 52
1361
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1362 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1363 calma 107 24
1364
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1365 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1366 calma 112 4
1367
1368 render DNWELL cwell -0.1 0.1
1369 render NWELL nwell 0.0 0.2062
1370 render DIFF ndiffusion 0.2062 0.12
1371 render TAP pdiffusion 0.2062 0.12
1372 render POLY polysilicon 0.3262 0.18
1373 render CONT via 0.5062 0.43
1374 render LI metal1 0.9361 0.10
1375 render MCON via 1.0361 0.34
1376 render MET1 metal2 1.3761 0.36
1377 render VIA1 via 1.7361 0.27
1378 render MET2 metal3 2.0061 0.36
1379 render VIA2 via 2.3661 0.42
1380 render MET3 metal4 2.7861 0.845
1381#ifdef METAL5
1382 render VIA3 via 3.6311 0.39
1383 render MET4 metal5 4.0211 0.845
1384 render VIA4 via 4.8661 0.505
1385 render MET5 metal6 5.3711 1.26
1386 render CAPM metal8 2.4661 0.2
1387 render CAPM2 metal9 3.7311 0.2
1388#ifdef REDISTRIBUTION
1389 render RDL metal7 11.8834 4.0
1390#endif (!REDISTRIBUTION)
1391#endif (!METAL5)
1392
1393#----------------------------------------------------------------
1394style drc
1395#----------------------------------------------------------------
1396# NOTE: This style is used for DRC only, not for GDS output
1397#----------------------------------------------------------------
1398 scalefactor 10 nanometers
1399 options calma-permissive-labels
1400
1401 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1402 templayer dnwell_shrink dnwell
1403 shrink 1030
1404
1405 templayer nwell_missing dnwell
1406 grow 400
1407 and-not dnwell_shrink
1408 and-not nwell
1409
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1410 templayer pwell_in_dnwell dnwell
1411 and-not nwell
1412
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1413 # SONOS nFET devices must be in deep nwell
1414 templayer dnwell_missing nsonos
1415 and-not dnwell
1416
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1417 # SONOS nFET devices must be in cell with abutment box
1418 templayer abutment_box
1419 boundary
1420
1421 templayer bbox_missing nsonos
1422 and-not abutment_box
1423
1424 # Make sure nwell covers varactor poly
1425 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1426 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1427 grow 150
1428 and-not nwell
1429
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1430 # Define MiM cap bottom plate for spacing rule
1431 templayer mim_bottom
1432 bloat-all *mimcap *metal3
1433
1434 # Define MiM2 cap bottom plate for spacing rule
1435 templayer mim2_bottom
1436 bloat-all *mimcap2 *metal4
1437
1438 # Note that metal fill is performed by the foundry and so is not
1439 # an option for a cifoutput style.
1440
1441 # Check latchup rule (15um minimum from tap LICON center to any
1442 # non-tap diffusion. Note that to count as a tap, the diffusion
1443 # must be contacted to LI
1444
1445 templayer ptap_reach psc,mvpsc
1446 and-not dnwell
1447 # grow total is 15um. grow in 0.84um increments to ensure that
1448 # no nwell ring is crossed
1449 grow 840
1450 and-not nwell,dnwell
1451 grow 840
1452 and-not nwell,dnwell
1453 grow 840
1454 and-not nwell,dnwell
1455 grow 840
1456 and-not nwell,dnwell
1457 grow 840
1458 and-not nwell,dnwell
1459 grow 840
1460 and-not nwell,dnwell
1461 grow 840
1462 and-not nwell,dnwell
1463 grow 840
1464 and-not nwell,dnwell
1465 grow 840
1466 and-not nwell,dnwell
1467 grow 840
1468 and-not nwell,dnwell
1469 grow 840
1470 and-not nwell,dnwell
1471 grow 840
1472 and-not nwell,dnwell
1473 grow 840
1474 and-not nwell,dnwell
1475 grow 840
1476 and-not nwell,dnwell
1477 grow 840
1478 and-not nwell,dnwell
1479 grow 840
1480 and-not nwell,dnwell
1481 grow 840
1482 and-not nwell,dnwell
1483 grow 635
1484 and-not nwell,dnwell
1485
1486 templayer ptap_missing *ndiff,*mvndiff
1487 and-not dnwell
1488 and-not ptap_reach
1489
1490 templayer ntap_reach nsc,mvnsc
1491 # grow total is 15um. grow in 1.27um increments to ensure that
1492 # no nwell ring is crossed. There is no difference between
1493 # ntaps in and out of deep nwell.
1494 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1495 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1496 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1497 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1498 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1499 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1500 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1501 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1502 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1503 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1504 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1505 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1506 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1507 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1508 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1509 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1510 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1511 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1512 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1513 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1514 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1515 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1516 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1517 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1518
1519 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1520 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1521 and-not ntap_reach
1522
1523 templayer dptap_reach psc,mvpsc
1524 and dnwell
1525 grow 840
1526 and-not nwell
1527 and dnwell
1528 grow 840
1529 and-not nwell
1530 and dnwell
1531 grow 840
1532 and-not nwell
1533 and dnwell
1534 grow 840
1535 and-not nwell
1536 and dnwell
1537 grow 840
1538 and-not nwell
1539 and dnwell
1540 grow 840
1541 and-not nwell
1542 and dnwell
1543 grow 840
1544 and-not nwell
1545 and dnwell
1546 grow 840
1547 and-not nwell
1548 and dnwell
1549 grow 840
1550 and-not nwell
1551 and dnwell
1552 grow 840
1553 and-not nwell
1554 and dnwell
1555 grow 840
1556 and-not nwell
1557 and dnwell
1558 grow 840
1559 and-not nwell
1560 and dnwell
1561 grow 840
1562 and-not nwell
1563 and dnwell
1564 grow 840
1565 and-not nwell
1566 and dnwell
1567 grow 840
1568 and-not nwell
1569 and dnwell
1570 grow 840
1571 and-not nwell
1572 and dnwell
1573 grow 840
1574 and-not nwell
1575 and dnwell
1576 grow 635
1577 and-not nwell
1578 and dnwell
1579
1580 templayer dptap_missing *ndiff,*mvndiff
1581 and dnwell
1582 and-not dptap_reach
1583
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1584 templayer pdiff_crosses_dnwell dnwell
1585 grow 20
1586 and-not dnwell
1587 and allpdifflv,allpdiffmv
1588
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1589 # MV nwell must be 2um from any other nwell
1590 templayer mvnwell
1591 bloat-all alldiffmv nwell
1592 grow-min 840
1593 bridge 700 600
1594
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1595 # Simple spacing checks to lvnwell must use CIF-DRC rule
1596 templayer allmvdiffnowell *mvndiff,*mvpsd
1597
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1598 templayer lvnwell nwell
1599 and-not mvnwell
1600
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1601 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1602 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1603
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1604 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1605 and-not nwell_with_tap
1606
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1607 templayer tap_with_licon
1608 bloat-all psc,mvpsc psd,mvpsd
1609 bloat-all nsc,mvnsc nsd,mvnsd
1610
1611 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1612 and-not tap_with_licon
1613
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1614 # Make sure varactor nwell contains no P diffusion
1615 templayer pdiff_in_varactor_well
1616 bloat-all varactor,mvvaractor nwell
1617 and allpactive
1618
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1619 # HVNTM spacing requires recreating HVNTM
1620 templayer hvntm_block *mvpsd
1621 grow 185
1622
1623 templayer hvntm_generate
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]1624 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1625 bloat-all mvvaractor *mvnsd
1626 and-not hvntm_block
1627 grow 185
1628 grow 345
1629 shrink 345
1630 and-not hvntm_block
1631
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1632 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1633 close 140000
1634
1635 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1636 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1637
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1638 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1639 close 140000
1640
1641 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1642 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1643
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1644 templayer m1_huge allm1
1645 shrink 1500
1646 grow 1500
1647
1648 templayer m1_large_halo m1_huge
1649 grow 280
1650 and-not m1_huge
1651 and allm1
1652
1653 templayer m2_huge allm2
1654 shrink 1500
1655 grow 1500
1656
1657 templayer m2_large_halo m2_huge
1658 grow 280
1659 and-not m2_huge
1660 and allm2
1661
1662 templayer m3_huge allm3
1663 shrink 1500
1664 grow 1500
1665
1666 templayer m3_large_halo m3_huge
1667 grow 400
1668 and-not m3_huge
1669 and allm3
1670
1671 templayer m4_huge allm4
1672 shrink 1500
1673 grow 1500
1674
1675 templayer m4_large_halo m4_huge
1676 grow 400
1677 and-not m4_huge
1678 and allm4
1679
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1680#ifdef EXPERIMENTAL
1681#----------------------------------------------------------------
1682style paint
1683#----------------------------------------------------------------
1684# NOTE: This style is used for database manipulations only via
1685# the "cif paint" command.
1686#----------------------------------------------------------------
1687
1688 scalefactor 10 nanometers
1689
1690 templayer m1grow *m1
1691 grow 290
1692
1693 # layer listrap: Use the following set of commands to strap local
1694 # interconnect wires with metal1 (inside the cursor box) to satisfy
1695 # the maximum aspect ratio rule for local interconnect:
1696 #
1697 # tech unlock *
1698 # cif ostyle paint
1699 # cif paint m1strap comment
1700 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1701 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1702 # erase comment
1703
1704 templayer m1strap *li
1705 and-not m1grow
1706 grow 30
1707
1708 templayer listrap comment
1709 slots 30 170 170 60
1710
1711#endif (EXPERIMENTAL)
1712
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1713#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1714style density
1715#----------------------------------------------------------------
1716# Style used by scripts to check for fill density
1717#----------------------------------------------------------------
1718 scalefactor 10 nanometers
1719 options calma-permissive-labels
1720 gridlimit 5
1721
1722 templayer fom_all alldiff,fomfill
1723
1724 templayer poly_all allpoly,polyfill
1725
1726 templayer li_all allli,lifill
1727
1728 templayer m1_all allm1,m1fill
1729
1730 templayer m2_all allm2,m2fill
1731
1732 templayer m3_all allm3,m3fill
1733
1734 templayer m4_all allm4,m4fill
1735
1736 templayer m5_all allm5,m5fill
1737
1738#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1739style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1740#----------------------------------------------------------------
1741# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1742# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1743#----------------------------------------------------------------
1744 scalefactor 10 nanometers
1745 options calma-permissive-labels
1746 gridlimit 5
1747
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1748#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1749# Generate and retain a layer representing the bounding box.
1750#
1751# For variant ():
1752# The bounding box is the full extent of geometry on the top level
1753# cell.
1754#
1755# For variant (tiled):
1756# Use with a script that breaks layout into flattened tiles and runs
1757# fill individually on each. The tiles should be larger than the
1758# step size, and each should draw a layer "comment" the size of the
1759# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1760#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1761
1762 variants ()
1763 templayer topbox
1764 bbox top
1765
1766 variants (tiled)
1767 templayer topbox comment
1768 # Each tile imposes the full keepout distance rule of
1769 # 3um on all sides.
1770 shrink 1500
1771
1772 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1773
1774#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1775# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1776# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1777# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1778# Enclosure by nwell = Diff/Tap 8 = 0.18um
1779#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1780
1781 templayer mvnwell
1782 bloat-all alldiffmv nwell
1783
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1784 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1785 and-not mvnwell
1786
1787 templayer well_shrink mvnwell
1788 shrink 250
1789 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1790 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1791 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1792 grow 340
1793 and-not well_shrink
1794
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1795#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1796# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1797#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1798 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1799 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1800 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1801 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1802
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1803 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1804 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1805 grow 1000
1806
1807#---------------------------------------------------
1808# FOM and POLY fill
1809#---------------------------------------------------
1810 templayer fomfill_pass1 topbox
1811 slots 0 4080 1320 0 4080 1320 1360 0
1812 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1813 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1814 shrink 2035
1815 grow 2035
1816
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1817#---------------------------------------------------
1818
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1819 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1820 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1821 or obstruct_poly
1822 templayer polyfill_pass1 topbox
1823 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1824 and-not obstruct_poly_pass1
1825 and topbox
1826 shrink 355
1827 grow 355
1828
1829#---------------------------------------------------
1830
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1831 templayer obstruct_fom_pass2 fomfill_pass1
1832 grow 1290
1833 or polyfill_pass1
1834 grow 300
1835 or obstruct_fom
1836 templayer fomfill_pass2 topbox
1837 slots 0 2500 1320 0 2500 1320 1360 0
1838 and-not obstruct_fom_pass2
1839 and topbox
1840 shrink 1245
1841 grow 1245
1842
1843#---------------------------------------------------
1844
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1845 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1846 grow 60
1847 or fomfill_pass1,fomfill_pass2
1848 grow 300
1849 or obstruct_poly
1850 templayer polyfill_coarse topbox
1851 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1852 and-not obstruct_poly_coarse
1853 and topbox
1854 shrink 355
1855 grow 355
1856
1857#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1858 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1859 grow 60
1860 or fomfill_pass1,fomfill_pass2
1861 grow 300
1862 or obstruct_poly
1863 templayer polyfill_medium topbox
1864 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1865 and-not obstruct_poly_medium
1866 and topbox
1867 shrink 265
1868 grow 265
1869
1870#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1871 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1872 grow 60
1873 or fomfill_pass1,fomfill_pass2
1874 grow 300
1875 or obstruct_poly
1876 templayer polyfill_fine topbox
1877 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1878 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1879 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1880 shrink 235
1881 grow 235
1882
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1883#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1884
1885 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1886 grow 1290
1887 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1888 grow 300
1889 or obstruct_fom
1890 templayer fomfill_coarse topbox
1891 slots 0 1500 1320 0 1500 1320 1360 0
1892 and-not obstruct_fom_coarse
1893 and topbox
1894 shrink 745
1895 grow 745
1896
1897#---------------------------------------------------
1898
1899 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1900 grow 1290
1901 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1902 grow 300
1903 or obstruct_fom
1904 templayer fomfill_fine topbox
1905 slots 0 500 400 0 500 400 160 0
1906 and-not obstruct_fom_fine
1907 and topbox
1908 shrink 245
1909 grow 245
1910
1911#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1912 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1913 or fomfill_pass2
1914 or fomfill_coarse
1915 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1916 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1917
1918 layer POLYFILL polyfill_pass1
1919 or polyfill_coarse
1920 or polyfill_medium
1921 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1922 calma 28 28
1923
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1924#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1925# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1926# Note requirement that LI fill may not overlap (non-fill)
1927# diff or poly.
1928#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1929
1930 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1931 grow 2800
1932 or alldiff,allpoly
1933 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1934 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]1935 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame^]1936 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1937 and-not obstruct_li_coarse
1938 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1939 shrink 1495
1940 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1941
1942 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1943 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1944 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1945 grow 300
1946 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1947 grow 200
1948 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1949 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1950 and-not obstruct_li_medium
1951 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1952 shrink 745
1953 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1954
1955 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1956 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1957 grow 300
1958 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1959 grow 200
1960 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1961 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1962 and-not obstruct_li_fine
1963 and topbox
1964 shrink 285
1965 grow 285
1966
1967 layer LIFILL lifill_coarse
1968 or lifill_medium
1969 or lifill_fine
1970 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1971
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1972#---------------------------------------------------
1973# MET1 fill
1974#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1975
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1976 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1977 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1978 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]1979 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame^]1980 slots 0 2000 600 0 2000 600 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1981 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1982 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1983 shrink 995
1984 grow 995
1985
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1986 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1987 grow 2800
1988 or met1fill_coarse
1989 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1990 templayer met1fill_medium topbox
1991 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1992 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1993 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1994 shrink 495
1995 grow 495
1996
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1997 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1998 grow 300
1999 or met1fill_coarse,met1fill_medium
2000 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2001 templayer met1fill_fine topbox
2002 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2003 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2004 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2005 shrink 285
2006 grow 285
2007
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2008 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2009 grow 100
2010 or met1fill_coarse,met1fill_medium,met1fill_fine
2011 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2012 templayer met1fill_veryfine topbox
2013 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2014 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2015 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2016 shrink 145
2017 grow 145
2018
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2019 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2020 or met1fill_medium
2021 or met1fill_fine
2022 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2023 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2024
2025#---------------------------------------------------
2026# MET2 fill
2027#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2028 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2029 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2030 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2031 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame^]2032 slots 0 2000 600 0 2000 600 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2033 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2034 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2035 shrink 995
2036 grow 995
2037
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2038 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2039 grow 2800
2040 or met2fill_coarse
2041 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2042 templayer met2fill_medium topbox
2043 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2044 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2045 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2046 shrink 495
2047 grow 495
2048
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2049 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2050 grow 300
2051 or met2fill_coarse,met2fill_medium
2052 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2053 templayer met2fill_fine topbox
2054 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2055 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2056 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2057 shrink 285
2058 grow 285
2059
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2060 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2061 grow 100
2062 or met2fill_coarse,met2fill_medium,met2fill_fine
2063 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2064 templayer met2fill_veryfine topbox
2065 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2066 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2067 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2068 shrink 145
2069 grow 145
2070
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2071 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2072 or met2fill_medium
2073 or met2fill_fine
2074 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2075 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2076
2077#---------------------------------------------------
2078# MET3 fill
2079#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2080 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2081 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2082 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2083 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame^]2084 slots 0 2000 600 0 2000 600 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2085 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2086 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2087 shrink 995
2088 grow 995
2089
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2090 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2091 grow 2700
2092 or met3fill_coarse
2093 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2094 templayer met3fill_medium topbox
2095 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2096 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2097 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2098 shrink 495
2099 grow 495
2100
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2101 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2102 grow 200
2103 or met3fill_coarse,met3fill_medium
2104 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2105 templayer met3fill_fine topbox
2106 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2107 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2108 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2109 shrink 285
2110 grow 285
2111
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2112 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2113 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2114 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115 or met3fill_coarse,met3fill_medium,met3fill_fine
2116 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2117 templayer met3fill_veryfine topbox
2118 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2119 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2120 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2121 shrink 195
2122 grow 195
2123
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2124 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2125 or met3fill_medium
2126 or met3fill_fine
2127 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2128 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2129
2130#ifdef METAL5
2131#---------------------------------------------------
2132# MET4 fill
2133#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2134 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2135 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2136 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2137 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame^]2138 slots 0 2000 600 0 2000 600 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2139 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2140 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2141 shrink 995
2142 grow 995
2143
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2144 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2145 grow 2700
2146 or met4fill_coarse
2147 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2148 templayer met4fill_medium topbox
2149 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2150 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2151 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2152 shrink 495
2153 grow 495
2154
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2155 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2156 grow 200
2157 or met4fill_coarse,met4fill_medium
2158 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2159 templayer met4fill_fine topbox
2160 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2161 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2162 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2163 shrink 285
2164 grow 285
2165
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2166 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2167 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2168 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2169 or met4fill_coarse,met4fill_medium,met4fill_fine
2170 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2171 templayer met4fill_veryfine topbox
2172 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2173 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2174 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2175 shrink 195
2176 grow 195
2177
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2178 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2179 or met4fill_medium
2180 or met4fill_fine
2181 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2182 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2183
2184#---------------------------------------------------
2185# MET5 fill
2186#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2187 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2188 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2189 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2190 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2191 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2192 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2193 shrink 2495
2194 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2195
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2196 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2197 grow 1400
2198 or met5fill_coarse
2199 grow 1600
2200 templayer met5fill_medium topbox
2201 slots 0 3000 1600 0 3000 1600 1000 100
2202 and-not obstruct_m5_medium
2203 and topbox
2204 shrink 1495
2205 grow 1495
2206
2207 layer MET5FILL met5fill_coarse
2208 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2209 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2210#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2211
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2212end
2213
2214#-----------------------------------------------------------------------
2215cifinput
2216#-----------------------------------------------------------------------
2217# NOTE: All values in this section MUST be multiples of 25
2218# or else magic will scale below the allowed layout grid size
2219#-----------------------------------------------------------------------
2220
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2221style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2222 scalefactor 10 nanometers
2223 gridlimit 5
2224
2225 options ignore-unknown-layer-labels no-reconnect-labels
2226
2227#ifndef MIM
2228 ignore CAPM
2229 ignore CAPM2
2230#endif (!MIM)
2231#ifndef METAL5
2232 ignore MET4,VIA3
2233 ignore MET5,VIA4
2234#endif
2235 ignore NPC
2236 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2237 ignore CAPID
2238 ignore LDNTM
2239 ignore HVNTM
2240 ignore POLYMOD
2241 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2242 ignore FILLOBSPOLY
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2243 ignore OUTLINE
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2244
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2245 layer pnp NWELL,WELLTXT,WELLPIN
2246 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2247 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2248 variants (vendor)
2249 labels WELLTXT port
2250 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2251 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2252 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2253 labels WELLPIN port
2254
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2255 layer nwell NWELL,WELLTXT,WELLPIN
2256 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2257 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2258 variants (vendor)
2259 labels WELLTXT port
2260 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2261 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2262 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2263 labels WELLPIN port
2264
2265 layer pwell SUBTXT,SUBPIN
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2266 variants (vendor)
2267 labels SUBTXT port
2268 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2269 labels SUBTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2270 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2271 labels SUBPIN port
2272
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2273 # Always draw pwell under p-tap
2274 layer pwell TAP
2275 and-not NWELL
2276
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2277 layer dnwell DNWELL
2278 labels DNWELL
2279
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2280 layer npn DNWELL
2281 and-not NWELL
2282 and NPNID
2283
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2284 layer rpw PWRES
2285 and DNWELL
2286 labels PWRES
2287
2288 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2289 and-not POLY
2290 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2291 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2292 and-not DIODE
2293 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2294 and-not HVI
2295 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2296 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2297 copyup ndifcheck
2298 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2299 variants (vendor)
2300 labels DIFFTXT port
2301 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2302 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2303 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2304 labels DIFFPIN port
2305 labels TAPPIN port
2306
2307 layer ndiff ndiffarea
2308
2309 # Copy ndiff areas up for contact checks
2310 templayer xndifcheck ndifcheck
2311 copyup ndifcheck
2312
2313 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2314 and-not POLY
2315 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2316 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2317 and-not DIODE
2318 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2319 and HVI
2320 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2321 copyup ndifcheck
2322 labels DIFF
2323 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2324 variants (vendor)
2325 labels DIFFTXT port
2326 variants ()
2327 labels DIFFTXT text
2328 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2329 labels DIFFPIN port
2330
2331 layer mvndiff mvndiffarea
2332
2333 # Copy ndiff areas up for contact checks
2334 templayer mvxndifcheck mvndifcheck
2335 copyup mvndifcheck
2336
2337 layer ndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2338 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2339 and DIODE
2340 and-not NWELL
2341 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2342 and-not PSDM
2343 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2344 and-not LVTN
2345 labels DIFF
2346
2347 layer ndiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2348 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2349 and DIODE
2350 and-not NWELL
2351 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2352 and-not PSDM
2353 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2354 and LVTN
2355 labels DIFF
2356
2357 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2358 and NSDM
2359 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2360 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2361 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2362
2363 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2364 and NSDM
2365 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2366 labels DIFF
2367
2368 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2369 and-not POLY
2370 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2371 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2372 and-not DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2373 and-not HVI
2374 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2375 copyup pdifcheck
2376 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2377 variants (vendor)
2378 labels DIFFTXT port
2379 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2380 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2381 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2382 labels DIFFPIN port
2383
2384 layer pdiff pdiffarea
2385
2386 layer mvndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2387 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2388 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2389 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2390 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2391 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2392 and-not LVTN
2393 labels DIFF
2394
2395 layer nndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2396 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2397 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2398 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2399 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2400 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2401 and LVTN
2402 labels DIFF
2403
2404 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2405 and NSDM
2406 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2407 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2408 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2409
2410 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2411 and NSDM
2412 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2413 labels DIFF
2414
2415 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2416 and-not POLY
2417 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2418 and-not NSDM
2419 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2420 and-not DIODE
2421 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2422 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2423 copyup mvpdifcheck
2424 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2425 variants (vendor)
2426 labels DIFFTXT port
2427 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2428 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2429 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2430 labels DIFFPIN port
2431
2432 layer mvpdiff mvpdiffarea
2433
2434 # Copy pdiff areas up for contact checks
2435 templayer xpdifcheck pdifcheck
2436 copyup pdifcheck
2437
2438 layer pdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2439 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2440 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2441 and-not NSDM
2442 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2443 and-not LVTN
2444 and-not HVTP
2445 and DIODE
2446 labels DIFF
2447
2448 layer pdiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2449 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2450 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2451 and-not NSDM
2452 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2453 and LVTN
2454 and-not HVTP
2455 and DIODE
2456 labels DIFF
2457
2458 layer pdiodehvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2459 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2460 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2461 and-not NSDM
2462 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2463 and-not LVTN
2464 and HVTP
2465 and DIODE
2466 labels DIFF
2467
2468 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2469 and PSDM
2470 and-not HVI
2471 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2472
2473 # Define pfet areas as known pdiff, regardless of the presence of a well.
2474
2475 templayer pfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2476 and-not NSDM
2477 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2478 and POLY
2479
2480 layer pfet pfetarea
2481 and-not LVTN
2482 and-not HVTP
2483 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2484 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2485 labels DIFF
2486
2487 layer scpfet pfetarea
2488 and-not LVTN
2489 and-not HVTP
2490 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2491 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2492 labels DIFF
2493
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2494 layer scpfethvt pfetarea
2495 and-not LVTN
2496 and HVTP
2497 and STDCELL
2498 labels DIFF
2499
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2500 layer ppu pfetarea
2501 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2502 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2503 and COREID
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2504 # Shrink-grow operation eliminates the smaller ppass device
2505 shrink 70
2506 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2507 labels DIFF
2508
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2509 layer pfetlvt pfetarea
2510 and LVTN
2511 labels DIFF
2512
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2513 layer pfetmvt pfetarea
2514 and HVTR
2515 labels DIFF
2516
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2517 layer pfethvt pfetarea
2518 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2519 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2520 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2521 labels DIFF
2522
2523 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2524 layer nwell pfetarea
2525 grow 180
2526
2527 # Copy mvpdiff areas up for contact checks
2528 templayer mvxpdifcheck mvpdifcheck
2529 copyup mvpdifcheck
2530
2531 layer mvpdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2532 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2533 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2534 and-not NSDM
2535 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2536 and DIODE
2537 labels DIFF
2538
2539 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2540 and PSDM
2541 and HVI
2542 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2543
2544 # Define pfet areas as known pdiff,
2545 # regardless of the presence of a
2546 # well.
2547
2548 templayer mvpfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2549 and-not NSDM
2550 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2551 and POLY
2552
2553 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2554 and-not ESDID
2555 labels DIFF
2556
2557 layer mvpfetesd mvpfetarea
2558 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2559 labels DIFF
2560
2561 layer pdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2562 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2563 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2564 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2565 and-not DIODE
2566 and-not DIFFRES
2567 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2568 variants (vendor)
2569 labels DIFFTXT port
2570 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2571 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2572 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2573 labels DIFFPIN port
2574
2575 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2576 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2577 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2578 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2579 labels DIFF
2580
2581 layer nfet DIFF
2582 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2583 and-not PSDM
2584 and NSDM
2585 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2586 and-not LVTN
2587 and-not SONOS
2588 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2589 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2590 labels DIFF
2591
2592 layer scnfet DIFF
2593 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2594 and-not PSDM
2595 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2596 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2597 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2598 and-not LVTN
2599 and-not SONOS
2600 and STDCELL
2601 labels DIFF
2602
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2603 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2604 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2605 and-not PSDM
2606 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2607 and-not NWELL
2608 and COREID
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2609 # Shrink-grow operation eliminates the smaller npass device
2610 shrink 70
2611 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2612 labels DIFF
2613
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2614 layer npd DIFF
2615 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2616 and-not PSDM
2617 and NSDM
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2618 and-not NWELL
2619 and COREID
2620 # Shrink-grow operation eliminates the smaller npass device
2621 shrink 70
2622 grow 70
2623 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2624
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2625 layer nfetlvt DIFF
2626 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2627 and-not PSDM
2628 and NSDM
2629 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2630 and LVTN
2631 and-not SONOS
2632 labels DIFF
2633
2634 layer nsonos DIFF
2635 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2636 and-not PSDM
2637 and NSDM
2638 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2639 and LVTN
2640 and SONOS
2641 labels DIFF
2642
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2643 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2644 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2645 and NWELL
2646 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2647 and-not PSDM
2648 and-not HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2649 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2650 copyup nsubcheck
2651
2652 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2653 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2654
2655 layer nsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2656 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2657 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2658 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2659 labels TAP
2660 labels TAPPIN port
2661
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2662 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2663 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2664 and POLY
2665 and COREID
2666 labels TAP
2667
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2668 templayer nsdexpand nsdarea
2669 grow 500
2670
2671 # Copy nsub areas up for contact checks
2672 templayer xnsubcheck nsubcheck
2673 copyup nsubcheck
2674
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2675 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2676 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2677 and-not NWELL
2678 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2679 and-not NSDM
2680 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2681 and-not pfetexpand
2682 copyup psubcheck
2683
2684 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2685 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2686
2687 layer psd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2688 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2689 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2690 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2691 labels TAP
2692 labels TAPPIN port
2693
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2694 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2695 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2696 and POLY
2697 and COREID
2698 labels TAP
2699
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2700 templayer psdexpand psdarea
2701 grow 500
2702
2703 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2704 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2705 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2706 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2707 and mvpfetexpand
2708 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2709 variants (vendor)
2710 labels DIFFTXT port
2711 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2712 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2713 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2714 labels DIFFPIN port
2715
2716 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2717 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2718 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2719 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2720 and-not mvrdpioedge
2721 labels DIFF
2722
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2723 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2724 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2725 and-not PSDM
2726 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2727 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2728 and HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2729 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2730
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2731 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2732 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2733 and-not PSDM
2734 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2735 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2736 and HVI
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2737 and-not mvnfetarea
2738
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2739 layer mvnfetesd DIFF
2740 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2741 and-not PSDM
2742 and NSDM
2743 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2744 and ESDID
2745 and-not mvnnfetarea
2746 labels DIFF
2747
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2748 layer mvnfet DIFF
2749 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2750 and-not PSDM
2751 and NSDM
2752 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2753 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2754 and-not mvnnfetarea
2755 labels DIFF
2756
2757 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2758 labels DIFF
2759
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2760 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2761 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2762 and NWELL
2763 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2764 and-not PSDM
2765 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2766 copyup mvnsubcheck
2767
2768 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2769 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2770
2771 layer mvnsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2772 and NSDM
2773 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2774 labels TAP
2775 labels TAPPIN port
2776
2777 templayer mvnsdexpand mvnsdarea
2778 grow 500
2779
2780 # Copy nsub areas up for contact checks
2781 templayer mvxnsubcheck mvnsubcheck
2782 copyup mvnsubcheck
2783
2784 templayer mvpsdarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2785 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2786 and-not NWELL
2787 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2788 and-not NSDM
2789 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2790 and-not mvpfetexpand
2791 copyup mvpsubcheck
2792
2793 layer mvpsd mvpsdarea
2794 labels DIFF
2795
2796 layer mvpsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2797 and PSDM
2798 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2799 labels TAP
2800 labels TAPPIN port
2801
2802 templayer mvpsdexpand mvpsdarea
2803 grow 500
2804
2805 # Copy psub areas up for contact checks
2806 templayer xpsubcheck psubcheck
2807 copyup psubcheck
2808
2809 templayer mvxpsubcheck mvpsubcheck
2810 copyup mvpsubcheck
2811
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2812 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2813 and-not PSDM
2814 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2815 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2816 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2817 and-not pfetexpand
2818 and psdexpand
2819
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2820 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2821 and-not PSDM
2822 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2823 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2824 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2825 and nsdexpand
2826
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2827 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2828 and-not PSDM
2829 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2830 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2831 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2832 and-not mvpfetexpand
2833 and mvpsdexpand
2834
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2835 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2836 and-not PSDM
2837 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2838 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2839 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2840 and mvnsdexpand
2841
2842 templayer hresarea POLY
2843 and RPM
2844 grow 3000
2845
2846 templayer uresarea POLY
2847 and URPM
2848 grow 3000
2849
2850 templayer diffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2851 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2852 grow 3000
2853
2854 templayer mvdiffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2855 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2856 grow 3000
2857
2858 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2859
2860 layer pfet POLY
2861 and DIFF
2862 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2863 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2864 and-not STDCELL
2865
2866 layer scpfet POLY
2867 and DIFF
2868 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2869 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2870 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2871 and STDCELL
2872
2873 layer scpfethvt POLY
2874 and DIFF
2875 and diffresarea
2876 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2877 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2878 and STDCELL
2879
2880 templayer xpolyterm RPM,URPM
2881 and POLY
2882 and-not POLYRES
2883 # add back the 0.06um contact surround in the direction of the resistor
2884 grow 60
2885 and POLY
2886
2887 layer xpc xpolyterm
2888
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2889 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2890 and-not POLYRES
2891 and-not POLYSHORT
2892 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2893 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2894 and-not RPM
2895 and-not URPM
2896 copyup polycheck
2897
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2898 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2899 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2900 variants (vendor)
2901 labels POLYTXT port
2902 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2903 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2904 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2905 labels POLYPIN port
2906
2907 # Copy (non-resistor) poly areas up for contact checks
2908 templayer xpolycheck polycheck
2909 copyup polycheck
2910
2911 layer mrp1 POLY
2912 and POLYRES
2913 and-not RPM
2914 and-not URPM
2915 labels POLY
2916
2917 layer rmp POLY
2918 and POLYSHORT
2919 labels POLY
2920
2921 layer xhrpoly POLY
2922 and POLYRES
2923 and RPM
2924 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2925 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2926 and NPC
2927 and-not xpolyterm
2928 labels POLY
2929
2930 layer uhrpoly POLY
2931 and POLYRES
2932 and URPM
2933 and-not RPM
2934 and NPC
2935 and-not xpolyterm
2936 labels POLY
2937
2938 templayer ndcbase CONT
2939 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2940 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2941 and-not NWELL
2942 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2943 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2944
2945 layer ndc ndcbase
2946 grow 85
2947 shrink 85
2948 shrink 85
2949 grow 85
2950 or ndcbase
2951 labels CONT
2952
2953 templayer nscbase CONT
2954 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2955 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2956 and NWELL
2957 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2958 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2959
2960 layer nsc nscbase
2961 grow 85
2962 shrink 85
2963 shrink 85
2964 grow 85
2965 or nscbase
2966 labels CONT
2967
2968 templayer pdcbase CONT
2969 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2970 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2971 and NWELL
2972 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2973 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2974
2975 layer pdc pdcbase
2976 grow 85
2977 shrink 85
2978 shrink 85
2979 grow 85
2980 or pdcbase
2981 labels CONT
2982
2983 templayer pdcnowell CONT
2984 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2985 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2986 and pfetexpand
2987 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2988 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2989
2990 layer pdc pdcnowell
2991 grow 85
2992 shrink 85
2993 shrink 85
2994 grow 85
2995 or pdcnowell
2996 labels CONT
2997
2998 templayer pscbase CONT
2999 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3000 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3001 and-not NWELL
3002 and-not pfetexpand
3003 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3004 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3005
3006 layer psc pscbase
3007 grow 85
3008 shrink 85
3009 shrink 85
3010 grow 85
3011 or pscbase
3012 labels CONT
3013
3014 templayer pcbase CONT
3015 and POLY
3016 and-not DIFF
3017 and-not RPM,URPM
3018 and LI
3019
3020 layer pc pcbase
3021 grow 85
3022 shrink 85
3023 shrink 85
3024 grow 85
3025 or pcbase
3026 labels CONT
3027
3028 templayer ndicbase CONT
3029 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3030 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3031 and DIODE
3032 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3033 and-not PSDM
3034 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3035 and-not LVTN
3036
3037 layer ndic ndicbase
3038 grow 85
3039 shrink 85
3040 shrink 85
3041 grow 85
3042 or ndicbase
3043 labels CONT
3044
3045 templayer ndilvtcbase CONT
3046 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3047 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3048 and DIODE
3049 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3050 and-not PSDM
3051 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3052 and LVTN
3053
3054 layer ndilvtc ndilvtcbase
3055 grow 85
3056 shrink 85
3057 shrink 85
3058 grow 85
3059 or ndilvtcbase
3060 labels CONT
3061
3062 templayer pdicbase CONT
3063 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3064 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3065 and DIODE
3066 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3067 and-not NSDM
3068 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3069 and-not LVTN
3070 and-not HVTP
3071
3072 layer pdic pdicbase
3073 grow 85
3074 shrink 85
3075 shrink 85
3076 grow 85
3077 or pdicbase
3078 labels CONT
3079
3080 templayer pdilvtcbase CONT
3081 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3082 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3083 and DIODE
3084 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3085 and-not NSDM
3086 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3087 and LVTN
3088 and-not HVTP
3089
3090 layer pdilvtc pdilvtcbase
3091 grow 85
3092 shrink 85
3093 shrink 85
3094 grow 85
3095 or pdilvtcbase
3096 labels CONT
3097
3098 templayer pdihvtcbase CONT
3099 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3100 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3101 and DIODE
3102 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3103 and-not NSDM
3104 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3105 and-not LVTN
3106 and HVTP
3107
3108 layer pdihvtc pdihvtcbase
3109 grow 85
3110 shrink 85
3111 shrink 85
3112 grow 85
3113 or pdihvtcbase
3114 labels CONT
3115
3116 templayer mvndcbase CONT
3117 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3118 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3119 and-not NWELL
3120 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3121 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3122
3123 layer mvndc mvndcbase
3124 grow 85
3125 shrink 85
3126 shrink 85
3127 grow 85
3128 or mvndcbase
3129 labels CONT
3130
3131 templayer mvnscbase CONT
3132 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3133 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3134 and NWELL
3135 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3136 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3137
3138 layer mvnsc mvnscbase
3139 grow 85
3140 shrink 85
3141 shrink 85
3142 grow 85
3143 or mvnscbase
3144 labels CONT
3145
3146 templayer mvpdcbase CONT
3147 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3148 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3149 and NWELL
3150 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3151 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3152
3153 layer mvpdc mvpdcbase
3154 grow 85
3155 shrink 85
3156 shrink 85
3157 grow 85
3158 or mvpdcbase
3159 labels CONT
3160
3161 templayer mvpdcnowell CONT
3162 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3163 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3164 and mvpfetexpand
3165 and MET1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3166 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3167
3168 layer mvpdc mvpdcnowell
3169 grow 85
3170 shrink 85
3171 shrink 85
3172 grow 85
3173 or mvpdcnowell
3174 labels CONT
3175
3176 templayer mvpscbase CONT
3177 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3178 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3179 and-not NWELL
3180 and-not mvpfetexpand
3181 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3182 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3183
3184 layer mvpsc mvpscbase
3185 grow 85
3186 shrink 85
3187 shrink 85
3188 grow 85
3189 or mvpscbase
3190 labels CONT
3191
3192 templayer mvndicbase CONT
3193 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3194 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3195 and DIODE
3196 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3197 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3198 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3199 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3200
3201 layer mvndic mvndicbase
3202 grow 85
3203 shrink 85
3204 shrink 85
3205 grow 85
3206 or mvndicbase
3207 labels CONT
3208
3209 templayer nndicbase CONT
3210 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3211 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3212 and DIODE
3213 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3214 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3215 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3216 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3217
3218 layer nndic nndicbase
3219 grow 85
3220 shrink 85
3221 shrink 85
3222 grow 85
3223 or nndicbase
3224 labels CONT
3225
3226 templayer mvpdicbase CONT
3227 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3228 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3229 and DIODE
3230 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3231 and-not NSDM
3232 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3233
3234 layer mvpdic mvpdicbase
3235 grow 85
3236 shrink 85
3237 shrink 85
3238 grow 85
3239 or mvpdicbase
3240 labels CONT
3241
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3242 layer fomfill FOMFILL
3243 labels FOMFILL
3244
3245 layer polyfill POLYFILL
3246 labels POLYFILL
3247
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3248 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3249 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3250 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3251 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3252 variants (vendor)
3253 labels LITXT port
3254 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3255 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3256 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3257 labels LIPIN port
3258
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3259 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3260 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3261 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3262 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3263 variants (vendor)
3264 labels LITXT port
3265 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3266 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3267 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3268 labels LIPIN port
3269
3270 layer rli LI
3271 and LIRES,LISHORT
3272 labels LIRES,LISHORT
3273
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3274 layer lifill LIFILL
3275 labels LIFILL
3276
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3277 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3278 grow 95
3279 shrink 95
3280 shrink 85
3281 grow 85
3282 or MCON
3283 labels MCON
3284
3285 layer m1 MET1,MET1TXT,MET1PIN
3286 and-not MET1RES,MET1SHORT
3287 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3288 variants (vendor)
3289 labels MET1TXT port
3290 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3291 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3292 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3293 labels MET1PIN port
3294
3295 layer rm1 MET1
3296 and MET1RES,MET1SHORT
3297 labels MET1RES,MET1SHORT
3298
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3299 layer m1fill MET1FILL
3300 labels MET1FILL
3301
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3302#ifdef MIM
3303 layer mimcap MET3
3304 and CAPM
3305 labels CAPM
3306
3307 layer mimcc VIA3
3308 and CAPM
3309 grow 60
3310 grow 40
3311 shrink 40
3312 labels CAPM
3313
3314 layer mimcap2 MET4
3315 and CAPM2
3316 labels CAPM2
3317
3318 layer mim2cc VIA4
3319 and CAPM2
3320 grow 190
3321 grow 210
3322 shrink 210
3323 labels CAPM2
3324
3325#endif (MIM)
3326
3327 templayer m2cbase VIA1
3328 grow 55
3329
3330 layer m2c m2cbase
3331 grow 30
3332 shrink 30
3333 shrink 130
3334 grow 130
3335 or m2cbase
3336
3337 layer m2 MET2,MET2TXT,MET2PIN
3338 and-not MET2RES,MET2SHORT
3339 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3340 variants (vendor)
3341 labels MET2TXT port
3342 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3343 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3344 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3345 labels MET2PIN port
3346
3347 layer rm2 MET2
3348 and MET2RES,MET2SHORT
3349 labels MET2RES,MET2SHORT
3350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3351 layer m2fill MET2FILL
3352 labels MET2FILL
3353
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3354 templayer m3cbase VIA2
3355 grow 40
3356
3357 layer m3c m3cbase
3358 grow 60
3359 shrink 60
3360 shrink 140
3361 grow 140
3362 or m3cbase
3363
3364 layer m3 MET3,MET3TXT,MET3PIN
3365 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3366 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3367 variants (vendor)
3368 labels MET3TXT port
3369 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3370 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3371 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3372 labels MET3PIN port
3373
3374 layer rm3 MET3
3375 and MET3RES,MET3SHORT
3376 labels MET3RES,MET3SHORT
3377
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3378 layer m3fill MET3FILL
3379 labels MET3FILL
3380
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3381#ifdef (METAL5)
3382
3383 templayer via3base VIA3
3384#ifdef MIM
3385 and-not CAPM
3386#endif (MIM)
3387 grow 60
3388
3389 layer via3 via3base
3390 grow 40
3391 shrink 40
3392 shrink 160
3393 grow 160
3394 or via3base
3395
3396 layer m4 MET4,MET4TXT,MET4PIN
3397 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3398 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3399 variants (vendor)
3400 labels MET4TXT port
3401 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3402 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3403 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3404 labels MET4PIN port
3405
3406 layer rm4 MET4
3407 and MET4RES,MET4SHORT
3408 labels MET4RES,MET4SHORT
3409
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3410 layer m4fill MET4FILL
3411 labels MET4FILL
3412
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3413 layer m5 MET5,MET5TXT,MET5PIN
3414 and-not MET5RES,MET5SHORT
3415 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3416 variants (vendor)
3417 labels MET5TXT port
3418 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3419 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3420 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3421 labels MET5PIN port
3422
3423 layer rm5 MET5
3424 and MET5RES,MET5SHORT
3425 labels MET5RES,MET5SHORT
3426
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3427 layer m5fill MET5FILL
3428 labels MET5FILL
3429
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3430 templayer via4base VIA4
3431#ifdef MIM
3432 and-not CAPM2
3433#endif (MIM)
3434 grow 190
3435
3436 layer via4 via4base
3437 grow 210
3438 shrink 210
3439 shrink 590
3440 grow 590
3441 or via4base
3442#endif (METAL5)
3443
3444#ifdef REDISTRIBUTION
3445 layer metrdl RDL,RDLTXT,RDLPIN
3446 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3447 variants (vendor)
3448 labels RDLTXT port
3449 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3450 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3451 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3452 labels RDLPIN port
3453#endif
3454
3455 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3456 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3457 # the next layer up
3458
3459 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3460 and-not PSDM
3461 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3462 and POLY
3463 copyup DIFF,POLY
3464
3465 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3466 and-not PSDM
3467 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3468 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3469 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3470 copyup DIFF
3471
3472 # Handle contacts found by copyup
3473
3474 templayer ndiccopy CONT
3475 and LI
3476 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3477 and NSDM
3478 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3479
3480 layer ndic ndiccopy
3481 grow 85
3482 shrink 85
3483 shrink 85
3484 grow 85
3485 or ndiccopy
3486 labels CONT
3487
3488 templayer mvndiccopy CONT
3489 and LI
3490 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3491 and NSDM
3492 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3493
3494 layer mvndic mvndiccopy
3495 grow 85
3496 shrink 85
3497 shrink 85
3498 grow 85
3499 or mvndiccopy
3500 labels CONT
3501
3502 templayer pdiccopy CONT
3503 and LI
3504 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3505 and PSDM
3506 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3507
3508 layer pdic pdiccopy
3509 grow 85
3510 shrink 85
3511 shrink 85
3512 grow 85
3513 or pdiccopy
3514 labels CONT
3515
3516 templayer mvpdiccopy CONT
3517 and LI
3518 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3519 and PSDM
3520 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3521
3522 layer mvpdic mvpdiccopy
3523 grow 85
3524 shrink 85
3525 shrink 85
3526 grow 85
3527 or mvpdiccopy
3528 labels CONT
3529
3530 templayer ndccopy CONT
3531 and ndifcheck
3532
3533 layer ndc ndccopy
3534 grow 85
3535 shrink 85
3536 shrink 85
3537 grow 85
3538 or ndccopy
3539 labels CONT
3540
3541 templayer mvndccopy CONT
3542 and mvndifcheck
3543
3544 layer mvndc mvndccopy
3545 grow 85
3546 shrink 85
3547 shrink 85
3548 grow 85
3549 or mvndccopy
3550 labels CONT
3551
3552 templayer pdccopy CONT
3553 and pdifcheck
3554
3555 layer pdc pdccopy
3556 grow 85
3557 shrink 85
3558 shrink 85
3559 grow 85
3560 or pdccopy
3561 labels CONT
3562
3563 templayer mvpdccopy CONT
3564 and mvpdifcheck
3565
3566 layer mvpdc mvpdccopy
3567 grow 85
3568 shrink 85
3569 shrink 85
3570 grow 85
3571 or mvpdccopy
3572 labels CONT
3573
3574 templayer pccopy CONT
3575 and polycheck
3576
3577 layer pc pccopy
3578 grow 85
3579 shrink 85
3580 shrink 85
3581 grow 85
3582 or pccopy
3583 labels CONT
3584
3585 templayer nsccopy CONT
3586 and nsubcheck
3587
3588 layer nsc nsccopy
3589 grow 85
3590 shrink 85
3591 shrink 85
3592 grow 85
3593 or nsccopy
3594 labels CONT
3595
3596 templayer mvnsccopy CONT
3597 and mvnsubcheck
3598
3599 layer mvnsc mvnsccopy
3600 grow 85
3601 shrink 85
3602 shrink 85
3603 grow 85
3604 or mvnsccopy
3605 labels CONT
3606
3607 templayer psccopy CONT
3608 and psubcheck
3609
3610 layer psc psccopy
3611 grow 85
3612 shrink 85
3613 shrink 85
3614 grow 85
3615 or psccopy
3616 labels CONT
3617
3618 templayer mvpsccopy CONT
3619 and mvpsubcheck
3620
3621 layer mvpsc mvpsccopy
3622 grow 85
3623 shrink 85
3624 shrink 85
3625 grow 85
3626 or mvpsccopy
3627 labels CONT
3628
3629 # Find contacts not covered in
3630 # metal and pull them into the
3631 # next layer up
3632
3633 templayer gencont CONT
3634 and LI
3635 and-not DIFF,TAP
3636 and-not POLY
3637 and-not DIODE
3638 and-not nsubcheck
3639 and-not psubcheck
3640 and-not mvnsubcheck
3641 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3642 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3643 copyup CONT,LI
3644
3645 templayer barecont CONT
3646 and-not LI
3647 and-not nsubcheck
3648 and-not psubcheck
3649 and-not mvnsubcheck
3650 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3651 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3652 copyup CONT
3653
3654 layer glass GLASS,PADTXT,PADPIN
3655 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3656 variants (vendor)
3657 labels PADTXT port
3658 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3659 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3660 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3661 labels PADPIN port
3662
3663 templayer boundary BOUND,STDCELL,PADCELL
3664 boundary
3665
3666 layer comment LVSTEXT
3667 labels LVSTEXT text
3668
3669 layer comment TTEXT
3670 labels TTEXT text
3671
3672 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3673 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3674
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3675 layer obsactive FILLOBSFOM
3676
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3677# MOS Varactor
3678
3679 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3680 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3681 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3682 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3683 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3684 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3685 # NOTE: Else forms a varactor that is not in the vendor netlist.
3686 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3687 labels POLY
3688
3689 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3690 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3691 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3692 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3693 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3694 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3695 labels POLY
3696
3697 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3698 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3699 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3700 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3701 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3702 labels POLY
3703
3704 calma NWELL 64 20
3705 calma DIFF 65 20
3706 calma DNWELL 64 18
3707 calma PWRES 64 13
3708 calma TAP 65 44
3709 # LVTN
3710 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3711 # HVTR
3712 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3713 # HVTP
3714 calma HVTP 78 44
3715 # SONOS (TUNM)
3716 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3717 # NSDM (NPLUS)
3718 calma NSDM 93 44
3719 # PSDM (PPLUS)
3720 calma PSDM 94 20
3721 # HVI (THKOX)
3722 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3723 # NPC
3724 calma NPC 95 20
3725 # P+ POLY MASK
3726 calma RPM 86 20
3727 calma URPM 79 20
3728 calma LDNTM 11 44
3729 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3730 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3731 calma POLYRES 66 13
3732 # Diffusion resistor ID mark
3733 calma DIFFRES 65 13
3734 calma POLY 66 20
3735 calma POLYMOD 66 83
3736 # Diode ID mark
3737 calma DIODE 81 23
3738 # Bipolar NPN mark
3739 calma NPNID 82 20
3740 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3741 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3742 # Capacitor ID
3743 calma CAPID 82 64
3744 # Core area ID mark
3745 calma COREID 81 2
3746 # Standard cell ID mark
3747 calma STDCELL 81 4
3748 # Padframe cell ID mark
3749 calma PADCELL 81 3
3750 # Seal ring ID mark
3751 calma SEALID 81 1
3752 # Low tap density ID mark
3753 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3754 # ESD area ID
3755 calma ESDID 81 19
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]3756 calma OUTLINE 236 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3757
3758 # LICON
3759 calma CONT 66 44
3760 calma LI 67 20
3761 calma MCON 67 44
3762
3763 calma MET1 68 20
3764 calma VIA1 68 44
3765 calma MET2 69 20
3766 calma VIA2 69 44
3767 calma MET3 70 20
3768#ifdef METAL5
3769 calma VIA3 70 44
3770 calma MET4 71 20
3771 calma VIA4 71 44
3772 calma MET5 72 20
3773#endif
3774#ifdef REDISTRIBUTION
3775 calma RDL 74 20
3776#endif
3777 calma GLASS 76 20
3778
3779 calma SUBPIN 64 59
3780 calma PADPIN 76 5
3781 calma DIFFPIN 65 6
3782 calma TAPPIN 65 5
3783 calma WELLPIN 64 5
3784 calma LIPIN 67 5
3785 calma POLYPIN 66 5
3786 calma MET1PIN 68 5
3787 calma MET2PIN 69 5
3788 calma MET3PIN 70 5
3789#ifdef METAL5
3790 calma MET4PIN 71 5
3791 calma MET5PIN 72 5
3792#endif
3793#ifdef REDISTRIBUTION
3794 calma RDLPIN 74 5
3795#endif
3796
3797 calma LIRES 67 13
3798 calma MET1RES 68 13
3799 calma MET2RES 69 13
3800 calma MET3RES 70 13
3801#ifdef METAL5
3802 calma MET4RES 71 13
3803 calma MET5RES 72 13
3804#endif
3805
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3806 calma LIFILL 56 28
3807 calma MET1FILL 36 28
3808 calma MET2FILL 41 28
3809 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3810#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3811 calma MET4FILL 51 28
3812 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3813#endif
3814
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3815 calma POLYSHORT 66 15
3816 calma LISHORT 67 15
3817 calma MET1SHORT 68 15
3818 calma MET2SHORT 69 15
3819 calma MET3SHORT 70 15
3820#ifdef METAL5
3821 calma MET4SHORT 71 15
3822 calma MET5SHORT 72 15
3823#endif
3824
3825 calma SUBTXT 122 16
3826 calma PADTXT 76 16
3827 calma DIFFTXT 65 16
3828 calma POLYTXT 66 16
3829 calma WELLTXT 64 16
3830 calma LITXT 67 16
3831 calma MET1TXT 68 16
3832 calma MET2TXT 69 16
3833 calma MET3TXT 70 16
3834#ifdef METAL5
3835 calma MET4TXT 71 16
3836 calma MET5TXT 72 16
3837#endif
3838#ifdef REDISTRIBUTION
3839 calma RDLPIN 74 16
3840#endif
3841
3842 calma BOUND 235 4
3843
3844 calma LVSTEXT 83 44
3845
3846#ifdef (MIM)
3847 calma CAPM 89 44
3848 calma CAPM2 97 44
3849#endif (MIM)
3850
3851 calma FILLOBSM1 62 24
3852 calma FILLOBSM2 105 52
3853 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3854 calma FILLOBSM4 112 4
3855 calma FILLOBSFOM 22 24
3856 calma FILLOBSPOLY 33 24
3857
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3858 calma FOMFILL 23 28
3859 calma POLYFILL 28 28
3860 calma LIFILL 56 28
3861 calma MET1FILL 36 28
3862 calma MET2FILL 41 28
3863 calma MET3FILL 34 28
3864 calma MET4FILL 51 28
3865 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3866
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3867#-----------------------------------------------------------------------
3868
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3869style rdlimport
3870 # This style is for reading shapes generated with the RDL layers
3871
3872 scalefactor 10 nanometers
3873 gridlimit 5
3874
3875 options ignore-unknown-layer-labels no-reconnect-labels
3876
3877 layer mrdl RDL
3878 layer mrdlc RDLC
3879
3880 calma RDL 10 0
3881 calma RDLC 20 0
3882
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3883end
3884
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3885#-----------------------------------------------------
3886# Digital flow maze router cost parameters
3887#-----------------------------------------------------
3888
3889mzrouter
3890end
3891
3892#-----------------------------------------------------
3893# Vendor DRC rules
3894#-----------------------------------------------------
3895
3896drc
3897
3898 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3899 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3900 cifstyle drc
3901
3902 variants (fast),(full)
3903
3904#-----------------------------
3905# DNWELL
3906#-----------------------------
3907
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3908 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
3909 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3910 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3911 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3912
3913 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3914 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3915 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3916 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3917 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3918
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3919 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
3920 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3921 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3922
3923#-----------------------------
3924# NWELL
3925#-----------------------------
3926
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3927 width allnwell 840 "N-well width < %d (nwell.1)"
3928 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3929
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3930 variants (full)
3931 cifmaxwidth nwell_missing_tap 0 bend_illegal \
3932 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3933
3934 cifspacing mvnwell lvnwell 2000 touching_illegal \
3935 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
3936 cifspacing mvnwell mvnwell 2000 touching_ok \
3937 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3938 variants (fast),(full)
3939
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3940#-----------------------------
3941# DIFF
3942#-----------------------------
3943
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3944 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3945 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3946 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3947 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3948
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3949 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
3950 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
3951 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
3952 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
3953 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
3954 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3955 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3956 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3957 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3958 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3959 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3960 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3961 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3962 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3963 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3964 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3965 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3966 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3967 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3968 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3969 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3970 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3971 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3972 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3973 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3974 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3975 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3976 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3977 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3978 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3979 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3980 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3981 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3982 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3983 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3984 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]3985
3986variants (full)
3987 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
3988 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
3989variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3990
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3991 spacing allnfets allpactivenonfet 270 touching_illegal \
3992 "nFET cannot abut P-diffusion (diff/tap.3)"
3993 spacing allpfets allnactivenonfet 270 touching_illegal \
3994 "pFET cannot abut N-diffusion (diff/tap.3)"
3995
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3996 # Butting junction rules
3997 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3998 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3999 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4000 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4001 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4002 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4003 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4004 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4005
4006 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4007 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4008 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4009 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4010 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4011 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4012 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4013 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4014
4015 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4016 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4017 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4018
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4019 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4020 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4021
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4022 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4023
4024 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4025 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4026
4027 # Latchup rules
4028 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4029 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4030 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4031 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4032 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4033 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4034
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4035 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4036
4037#-----------------------------
4038# POLY
4039#-----------------------------
4040
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4041 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4042 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4043
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4044 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4045 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4046 75 corner_ok allfets \
4047 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4048 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4049 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4050 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4051 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4052 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4053 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4054 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4055 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4056 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4057 rect_only allfets "No bends in transistors (poly.11)"
4058 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4059 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4060 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4061 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4062 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4063
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4064 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
4065 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4066 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4067 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
4068 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
4069 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
4070
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4071 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4072
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4073#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4074# HVTP
4075#--------------------------------------------------------------------
4076
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4077 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4078 360 touching_illegal \
4079 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4080
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4081 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4082 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4083
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4084#--------------------------------------------------------------------
4085# LVTN
4086#--------------------------------------------------------------------
4087
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4088 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4089 allfetsnolvt 360 touching_illegal \
4090 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4091
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4092 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4093 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4094 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4095
4096 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4097 edge4way allfetsnolvt allactivenonfet 415 \
4098 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4099 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4100
4101#--------------------------------------------------------------------
4102# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4103#--------------------------------------------------------------------
4104
4105# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4106
4107#--------------------------------------------------------------------
4108# CONT (LICON, contact between poly/diff and LI)
4109#--------------------------------------------------------------------
4110
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4111 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4112 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4113 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4114 width psc/li 170 "P-tap contact width < %d (licon.1)"
4115 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4116 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4117 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4118
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4119 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4120 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4121 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4122
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4123 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4124 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4125 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4126 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4127 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4128 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4129
4130 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4131 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4132 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4133 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4134 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4135 "Diffusion contact spacing < %d (licon.2)"
4136 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4137
4138 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4139 "poly contact spacing to diffusion < %d (licon.14)"
4140 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4141 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4142
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4143 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4144 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4145 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4146 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4147 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4148 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4149 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4150 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4151 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4152 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4153 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4154 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4155
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4156 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4157 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4158 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4159 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4160 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4161 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4162 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4163 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4164 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4165
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4166 spacing psc/a allnactivenontap 60 touching_illegal \
4167 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4168 spacing nsc/a allpactivenontap 60 touching_illegal \
4169 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4170
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4171 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4172 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4173 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4174 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4175 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4176 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4177 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4178 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4179 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4180
4181 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4182 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4183 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4184 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4185
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4186 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4187 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4188 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4189 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4190 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4191 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4192 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4193 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4194
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4195 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4196 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4197 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4198 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4199
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4200 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4201 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4202 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4203 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4204 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4205 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4206 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4207 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4208
4209 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4210 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4211 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4212 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4213
4214 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4215 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4216 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4217 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4218
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4219 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4220
4221#-------------------------------------------------------------
4222# LI - Local interconnect layer
4223#-------------------------------------------------------------
4224
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4225variants *
4226
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4227 width *li 170 "Local interconnect width < %d (li.1)"
4228 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4229
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4230 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4231 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4232
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4233 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4234 # no special layers for the contacts in core cells, so they must be included
4235 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4236 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4237 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4238
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4239 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4240 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4241
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4242 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4243 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4244
4245 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4246 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4247 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4248
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4249 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4250
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4251 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4252 angles coreli 45 \
4253 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4254
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4255#-------------------------------------------------------------
4256# MCON - Contact between local interconnect and metal1
4257#-------------------------------------------------------------
4258
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4259 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4260 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4261
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4262 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4263
4264#-------------------------------------------------------------
4265# METAL1 -
4266#-------------------------------------------------------------
4267
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4268 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4269 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4270 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4271
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4272 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4273 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4274 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4275 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4276
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4277 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4278
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4279variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4280 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4281 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4282 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4283 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4284
4285variants (full)
4286 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4287 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4288
4289 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4290 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4291variants *
4292
4293#--------------------------------------------------
4294# VIA1
4295#--------------------------------------------------
4296
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4297 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4298 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4299 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4300 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4301 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4302 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4303
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4304 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4305
4306#--------------------------------------------------
4307# METAL2 -
4308#--------------------------------------------------
4309
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4310 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4311 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4312 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4313
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4314 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4315
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4316variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4317 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4318 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4319 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4320 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4321
4322variants (full)
4323 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4324 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4325
4326 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4327 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4328variants *
4329
4330#--------------------------------------------------
4331# VIA2
4332#--------------------------------------------------
4333
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4334 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4335
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4336 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4337
4338 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4339 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4340 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4341
4342 exact_overlap v2/m2
4343
4344#--------------------------------------------------
4345# METAL3 -
4346#--------------------------------------------------
4347
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4348 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4349 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4350 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4351
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4352 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4353
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4354variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4355 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4356 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4357 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4358 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4359variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4360 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4361 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4362variants *
4363
4364
4365#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4366#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4367#--------------------------------------------------
4368# VIA3 - Requires METAL5 Module
4369#--------------------------------------------------
4370
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4371 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4372 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4373 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4374 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4375 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4376 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4377
4378 exact_overlap v3/m3
4379
4380#-----------------------------
4381# METAL4 - METAL4 Module
4382#-----------------------------
4383
4384variants *
4385
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4386 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4387 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4388 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4389
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4390 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4391
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4392variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4393 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4394 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4395 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4396 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4397variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4398 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4399 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4400variants *
4401
4402#--------------------------------------------------
4403# VIA4 - Requires METAL5 Module
4404#--------------------------------------------------
4405
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4406 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4407 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4408 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4409 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4410
4411 exact_overlap v4/m4
4412
4413#-----------------------------
4414# METAL5 - METAL5 Module
4415#-----------------------------
4416
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4417 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4418 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4419 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4420
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4421 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4422
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4423#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4424#endif (METAL5)
4425
4426#ifdef REDISTRIBUTION
4427
4428variants (full)
4429
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4430 width metrdl 10000 "RDL width < %d (rdl.1)"
4431 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4432 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4433 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4434
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4435variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4436
4437#endif (REDISTRIBUTION)
4438
4439#--------------------------------------------------
4440# NMOS, PMOS
4441#--------------------------------------------------
4442
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4443 edge4way *poly allfetsstd 420 allfets 0 0 \
4444 "Transistor width < %d (diff/tap.2)"
4445 edge4way *poly allfetsspecial 360 allfets 0 0 \
4446 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4447 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4448 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4449 edge4way *poly ppu 140 allfets 0 0 \
4450 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4451
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4452 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4453 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4454
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4455 spacing allpolynonfet,polyfill *nsd 55 corner_ok varactor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4456 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4457 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvaractor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4458 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4459
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4460 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4461 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4462 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4463 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4464 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4465 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4466 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4467 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4468
4469 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4470 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4471 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4472
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4473 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4474 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4475
4476 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4477 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4478 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4479
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4480 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4481 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4482
4483 # Minimum length of MV FETs. Note that this is larger than the minimum
4484 # width (0.29um), so an edge rule is required
4485
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4486 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4487 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4488
4489 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4490 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4491
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4492 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4493 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4494
4495#--------------------------------------------------
4496# mrp1 (N+ poly resistor)
4497#--------------------------------------------------
4498
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4499 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4500
4501#--------------------------------------------------
4502# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4503# uhrpoly (P+ poly resistor, 2kOhm/sq)
4504#--------------------------------------------------
4505
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4506 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4507 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4508 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4509
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4510 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4511 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4512
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4513 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4514 "Poly resistor spacing to poly < %d (poly.9)"
4515
4516 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4517 "Poly resistor spacing to poly < %d (poly.9)"
4518
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4519 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4520 "Poly resistor spacing to poly < %d (poly.9)"
4521
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4522 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4523 "Poly resistor spacing to diffusion < %d (poly.9)"
4524
4525#------------------------------------
4526# nsonos
4527#------------------------------------
4528
4529variants (full)
4530 cifmaxwidth bbox_missing 0 bend_illegal \
4531 "SONOS transistor must be in cell with abutment box (tunm.8)"
4532variants (fast),(full)
4533
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4534#------------------------------------
4535# MOS Varactor device rules
4536#------------------------------------
4537
4538 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4539 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4540
4541 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4542 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4543
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4544 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4545 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4546
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4547variants (full)
4548 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4549 "N-well overlap of varactor poly < 0.15um (varac.5)"
4550
4551 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4552 "Varactor N-well must not contain P+ diffusion (varac.7)"
4553variants (fast),(full)
4554
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4555#ifdef MIM
4556#-----------------------------------------------------------
4557# MiM CAP (CAPM) -
4558#-----------------------------------------------------------
4559
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4560 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4561 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4562 spacing *mimcap via3/m3 80 touching_illegal \
4563 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4564 surround *mimcc *mimcap 80 absence_illegal \
4565 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4566 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4567
4568 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4569 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4570 spacing via2 *mimcap 100 touching_illegal \
4571 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4572 spacing *mimcap *metal3/m3 500 surround_ok \
4573 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4574
4575variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4576 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4577 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4578variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4579
4580 # MiM cap contact rules (VIA3)
4581
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4582 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4583 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4584 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4585 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4586 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4587
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4588 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4589 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4590 spacing *mimcap2 via4/m4 10 touching_illegal \
4591 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4592 surround *mim2cc *mimcap2 10 absence_illegal \
4593 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4594 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4595
4596 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4597 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4598 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4599 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4600 spacing *mimcap2 *metal4/m4 500 surround_ok \
4601 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4602
4603variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4604 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4605 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4606variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4607
4608 # MiM cap contact rules (VIA4)
4609
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4610 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4611 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4612 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4613 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4614 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4615 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4616
4617#endif (MIM)
4618
4619#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4620# HVNTM
4621#----------------------------
4622variants (full)
4623 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4624 "HVNTM spacing < %d (hvntm.2)"
4625variants (fast),(full)
4626
4627#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4628# End DRC style
4629#----------------------------
4630
4631end
4632
4633#----------------------------
4634# LEF format definitions
4635#----------------------------
4636
4637lef
4638
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4639 masterslice pwell pwell PWELL substrate
4640 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4641
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4642 routing li li1 LI1 LI li
4643
4644 routing m1 met1 MET1 m1
4645 routing m2 met2 MET2 m2
4646 routing m3 met3 MET3 m3
4647#ifdef METAL5
4648 routing m4 met4 MET4 m4
4649 routing m5 met5 MET5 m5
4650#endif (METAL5)
4651#ifdef REDISTRIBUTION
4652 routing mrdl met6 MET6 m6 MRDL METRDL
4653#endif
4654
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4655 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4656 cut m2c via via1 VIA VIA1 cont2 via12
4657 cut m3c via2 VIA2 cont3 via23
4658#ifdef METAL5
4659 cut via3 via3 VIA3 cont4 via34
4660 cut via4 via4 VIA4 cont5 via45
4661#endif (METAL5)
4662
4663 obs obsli li1
4664 obs obsm1 met1
4665 obs obsm2 met2
4666 obs obsm3 met3
4667
4668#ifdef METAL5
4669 obs obsm4 met4
4670 obs obsm5 met5
4671#endif (METAL5)
4672#ifdef REDISTRIBUTION
4673 obs obsmrdl met6
4674#endif
4675
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4676 # NOTE: obsmcon only used with li1, not obsli.
4677 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4678
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4679 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4680 obs obsm1 via
4681 obs obsm2 via2
4682#ifdef METAL5
4683 obs obsm3 via3
4684 obs obsm4 via4
4685#endif (METAL5)
4686
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4687end
4688
4689#-----------------------------------------------------
4690# Device and Parasitic extraction
4691#-----------------------------------------------------
4692
4693
4694extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4695 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4696 cscale 1
4697 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4698 # dimensions must be in units of microns in the extract file.
4699 # Use extract style "ngspice(si)" to override this and produce
4700 # a file with SI units for length/area.
4701
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4702 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4703 lambda 1E6
4704 variants (si)
4705 lambda 1.0
4706 variants *
4707
4708 units microns
4709 step 7
4710 sidehalo 2
4711
4712 # NOTE: MiM cap layers have been purposely put out of order,
4713 # may want to reconsider.
4714
4715 planeorder dwell 0
4716 planeorder well 1
4717 planeorder active 2
4718 planeorder locali 3
4719 planeorder metal1 4
4720 planeorder metal2 5
4721 planeorder metal3 6
4722#ifdef METAL5
4723 planeorder metal4 7
4724 planeorder metal5 8
4725#ifdef REDISTRIBUTION
4726 planeorder metali 9
4727 planeorder block 10
4728 planeorder comment 11
4729 planeorder cap1 12
4730 planeorder cap2 13
4731#else (!REDISTRIBUTION)
4732 planeorder block 9
4733 planeorder comment 10
4734 planeorder cap1 11
4735 planeorder cap2 12
4736#endif (!REDISTRIBUTION)
4737#else (!METAL5)
4738#ifdef REDISTRIBUTION
4739 planeorder metali 7
4740 planeorder block 8
4741 planeorder comment 9
4742 planeorder cap1 10
4743 planeorder cap2 11
4744#else (!REDISTRIBUTION)
4745 planeorder block 7
4746 planeorder comment 8
4747 planeorder cap1 9
4748 planeorder cap2 10
4749#endif (!REDISTRIBUTION)
4750#endif (!METAL5)
4751
4752 height dnwell -0.1 0.1
4753 height nwell,pwell 0.0 0.2062
4754 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4755 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4756 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4757 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4758 height alldiffcont 0.3262 0.61
4759 height pc 0.5062 0.43
4760 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4761 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4762 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4763 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4764 height v1 1.7361 0.27
4765 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4766 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4767 height v2 2.3661 0.42
4768 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4769 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4770#ifdef METAL5
4771 height v3 3.6311 0.39
4772 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4773 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4774 height v4 4.8661 0.505
4775 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4776 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4777 height mimcap 2.4661 0.2
4778 height mimcap2 3.7311 0.2
4779 height mimcc 2.6661 0.12
4780 height mim2cc 3.9311 0.09
4781#ifdef REDISTRIBUTION
4782 height mrdlc 6.6311 5.2523
4783 height mrdl 11.8834 4.0
4784#endif (!REDISTRIBUTION)
4785#endif (!METAL5)
4786
4787 # Antenna check parameters
4788 # Note that checks w/diode diffusion are not modeled
4789 model partial
4790 antenna poly sidewall 50 none
4791 antenna allcont surface 3 none
4792 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4793 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4794 antenna m1,m2,m3 sidewall 400 2600 400
4795 antenna v1 surface 3 0 18
4796 antenna v2 surface 6 0 36
4797#ifdef METAL5
4798 antenna m4,m5 sidewall 400 2600 400
4799 antenna v3,v4 surface 6 0 36
4800#endif (METAL5)
4801
4802 tiedown alldiffnonfet
4803
4804 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
4805
4806# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4807
4808# Resistances are in milliohms per square
4809# Optional 3rd argument is the corner adjustment fraction
4810# Device values come from trtc.cor (typical corner)
4811 resist (dnwell)/dwell 2200000
4812 resist (pwell)/well 3050000
4813 resist (nwell)/well 1700000
4814 resist (rpw)/well 3050000 0.5
4815 resist (*ndiff,nsd)/active 120000
4816 resist (*pdiff,*psd)/active 197000
4817 resist (*mvndiff,mvnsd)/active 114000
4818 resist (*mvpdiff,*mvpsd)/active 191000
4819
4820 resist ndiffres/active 120000 0.5
4821 resist pdiffres/active 197000 0.5
4822 resist mvndiffres/active 114000 0.5
4823 resist mvpdiffres/active 191000 0.5
4824 resist mrp1/active 48200 0.5
4825 resist xhrpoly/active 319800 0.5
4826 resist uhrpoly/active 2000000 0.5
4827
4828 resist (allpolynonres)/active 48200
4829 resist rmp/active 48200
4830
4831 resist (allli)/locali 12200
4832 resist (allm1)/metal1 125
4833 resist (allm2)/metal2 125
4834 resist (allm3)/metal3 47
4835#ifdef METAL5
4836 resist (allm4)/metal4 47
4837 resist (allm5)/metal5 29
4838#endif (METAL5)
4839#ifdef REDISTRIBUTION
4840 resist mrdl/metali 5
4841#endif (REDISTRIBUTION)
4842
4843 contact ndc,nsc 15000
4844 contact pdc,psc 15000
4845 contact mvndc,mvnsc 15000
4846 contact mvpdc,mvpsc 15000
4847 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4848 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4849 contact m2c 4500
4850 contact m3c 3410
4851#ifdef METAL5
4852#ifdef MIM
4853 contact mimcc 4500
4854 contact mim2cc 3410
4855#endif (MIM)
4856 contact via3 3410
4857 contact via4 380
4858#endif (METAL5)
4859#ifdef REDISTRIBUTION
4860 contact mrdlc 6
4861#endif (REDISTRIBUTION)
4862
4863#-------------------------------------------------------------------------
4864# Parasitic capacitance values: Use document (...)
4865#-------------------------------------------------------------------------
4866# This uses the new "default" definitions that determine the intervening
4867# planes from the planeorder stack, take care of the reflexive sideoverlap
4868# definitions, and generally clean up the section and make it more readable.
4869#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4870# Also uses "units microns" statement. All values are taken from the
4871# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
4872# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4873#-------------------------------------------------------------------------
4874# Remember that device capacitances to substrate are taken care of by the
4875# models. Thus, active and poly definitions ignore all "fet" types.
4876# fet types are excluded when computing parasitic capacitance to
4877# active from layers above them because poly is a shield; fet types are
4878# included for parasitics from layers above to poly. Resistor types
4879# should be removed from all parasitic capacitance calculations, or else
4880# they just create floating caps. Technically, the capacitance probably
4881# should be split between the two terminals. Unsure of the correct model.
4882#-------------------------------------------------------------------------
4883
4884#n-well
4885# NOTE: This value not found in PEX files
4886defaultareacap nwell well 120
4887
4888#n-active
4889# Rely on device models to capture *ndiff area cap
4890# Do not extract parasitics from resistors
4891# defaultareacap allnactivenonfet active 790
4892# defaultperimeter allnactivenonfet active 280
4893
4894#p-active
4895# Rely on device models to capture *pdiff area cap
4896# Do not extract parasitics from resistors
4897# defaultareacap allpactivenonfet active 810
4898# defaultperimeter allpactivenonfet active 300
4899
4900#poly
4901# Do not extract parasitics from resistors
4902# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4903# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4904# defaultperimeter allpolynonfet active 57
4905
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4906 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4907 defaultareacap *poly active nwell,obswell,pwell well 106
4908 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4909
4910#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4911 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4912 defaultareacap allli locali nwell,obswell,pwell well 37
4913 defaultperimeter allli locali nwell,obswell,pwell well 55
4914 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4915
4916#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4917 defaultoverlap allli locali allactivenonfet active 37
4918 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4919
4920#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4921 defaultoverlap allli locali allpolynonres active 94
4922 defaultsideoverlap allli locali allpolynonres active 52
4923 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4924
4925#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4926 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4927 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
4928 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4929 defaultoverlap allm1 metal1 nwell well 26
4930
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4931#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4932 defaultoverlap allm1 metal1 allactivenonfet active 26
4933 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4934
4935#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4936 defaultoverlap allm1 metal1 allpolynonres active 45
4937 defaultsideoverlap allm1 metal1 allpolynonres active 47
4938 defaultsideoverlap *poly active allm1 metal1 17
4939
4940#metal1->locali
4941 defaultoverlap allm1 metal1 allli locali 114
4942 defaultsideoverlap allm1 metal1 allli locali 59
4943 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4944
4945#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4946 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4947 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
4948 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
4949 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4950
4951#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4952 defaultoverlap allm2 metal2 allactivenonfet active 17
4953 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4954
4955#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4956 defaultoverlap allm2 metal2 allpolynonres active 24
4957 defaultsideoverlap allm2 metal2 allpolynonres active 41
4958 defaultsideoverlap *poly active allm2 metal2 11
4959
4960#metal2->locali
4961 defaultoverlap allm2 metal2 allli locali 38
4962 defaultsideoverlap allm2 metal2 allli locali 46
4963 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4964
4965#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4966 defaultoverlap allm2 metal2 allm1 metal1 134
4967 defaultsideoverlap allm2 metal2 allm1 metal1 67
4968 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4969
4970#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4971 defaultsidewall allm3 metal3 63
4972 defaultoverlap allm3 metal3 nwell well 12
4973 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
4974 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4975
4976#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4977 defaultoverlap allm3 metal3 allactive active 12
4978 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4979
4980#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4981 defaultoverlap allm3 metal3 allpolynonres active 16
4982 defaultsideoverlap allm3 metal3 allpolynonres active 44
4983 defaultsideoverlap *poly active allm3 metal3 9
4984
4985#metal3->locali
4986 defaultoverlap allm3 metal3 allli locali 21
4987 defaultsideoverlap allm3 metal3 allli locali 47
4988 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4989
4990#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4991 defaultoverlap allm3 metal3 allm1 metal1 35
4992 defaultsideoverlap allm3 metal3 allm1 metal1 55
4993 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4994
4995#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4996 defaultoverlap allm3 metal3 allm2 metal2 86
4997 defaultsideoverlap allm3 metal3 allm2 metal2 70
4998 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4999
5000#ifdef METAL5
5001#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5002 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5003# defaultareacap alltopm metal4 well 6
5004 areacap allm4/m4 8
5005 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5006 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5007
5008#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5009 defaultoverlap allm4 metal4 allactivenonfet active 8
5010 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5011
5012#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5013 defaultoverlap allm4 metal4 allpolynonres active 10
5014 defaultsideoverlap allm4 metal4 allpolynonres active 38
5015 defaultsideoverlap *poly active allm4 metal4 6
5016
5017#metal4->locali
5018 defaultoverlap allm4 metal4 allli locali 12
5019 defaultsideoverlap allm4 metal4 allli locali 40
5020 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5021
5022#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5023 defaultoverlap allm4 metal4 allm1 metal1 15
5024 defaultsideoverlap allm4 metal4 allm1 metal1 43
5025 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5026
5027#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5028 defaultoverlap allm4 metal4 allm2 metal2 20
5029 defaultsideoverlap allm4 metal4 allm2 metal2 46
5030 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5031
5032#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5033 defaultoverlap allm4 metal4 allm3 metal3 84
5034 defaultsideoverlap allm4 metal4 allm3 metal3 71
5035 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5036
5037#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5038 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5039# defaultareacap allm5 metal5 well 6
5040 areacap allm5/m5 6
5041 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5042 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5043
5044#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5045 defaultoverlap allm5 metal5 allactivenonfet active 6
5046 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5047
5048#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5049 defaultoverlap allm5 metal5 allpolynonres active 7
5050 defaultsideoverlap allm5 metal5 allpolynonres active 40
5051 defaultsideoverlap *poly active allm5 metal5 6
5052
5053#metal5->locali
5054 defaultoverlap allm5 metal5 allli locali 8
5055 defaultsideoverlap allm5 metal5 allli locali 41
5056 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5057
5058#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5059 defaultoverlap allm5 metal5 allm1 metal1 9
5060 defaultsideoverlap allm5 metal5 allm1 metal1 43
5061 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5062
5063#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5064 defaultoverlap allm5 metal5 allm2 metal2 11
5065 defaultsideoverlap allm5 metal5 allm2 metal2 46
5066 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5067
5068#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5069 defaultoverlap allm5 metal5 allm3 metal3 20
5070 defaultsideoverlap allm5 metal5 allm3 metal3 54
5071 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5072
5073#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5074 defaultoverlap allm5 metal5 allm4 metal4 68
5075 defaultsideoverlap allm5 metal5 allm4 metal4 83
5076 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5077#endif (METAL5)
5078
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5079#ifdef REDISTRIBUTION
5080#endif (REDISTRIBUTION)
5081
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5082# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5083
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5084variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5085
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5086 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5087 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5088 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5089 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5090 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5091 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5092 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5093 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5094 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5095 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5096 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5097 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5098 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5099 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5100 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5101
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5102 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5103 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5104 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5105 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5106 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5107 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5108 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5109 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5110 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5111 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5112 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5113 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5114 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5115 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5116 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5117 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5118 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5119 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5120 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5121 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5122 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5123
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5124 # Bipolars
5125 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
5126 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
5127 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
5128
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5129 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5130 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5131 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5132 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5133
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5134 # Extended drain devices (must appear before the regular devices)
5135 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5136 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5137 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5138 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5139 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5140 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5141
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5142 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5143 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5144 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5145 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5146 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5147 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5148 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5149 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5150 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5151 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5152 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5153 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5154 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5155 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5156 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5157
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5158 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5159 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5160 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5161 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5162#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5163 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5164 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5165#endif (METAL5)
5166
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5167 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5168 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5169 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5170 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5171 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5172 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5173 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5174 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5175 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5176 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5177 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5178 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5179 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5180 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5181 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5182 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5183 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5184 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5185 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5186 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5187 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5188 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5189 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5190 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5191
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5192 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5193 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5194 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5195 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5196 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5197 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5198 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5199 *mvndiff pwell,space/w error l=l w=w
5200 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5201 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5202
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5203 device resistor sky130_fd_pr__res_generic_po rmp *poly
5204 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5205
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5206 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5207 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5208 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
5209 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5210 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5211 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5212 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5213 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5214
5215 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
5216 pwell,space/w a=area
5217 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
5218 pwell,space/w a=area
5219 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
5220 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5221 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5222 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5223
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5224
5225#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5226 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5227 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5228#endif (MIM)
5229
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5230 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5231
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5232 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5233 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5234 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5235 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5236 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5237 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5238 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5239 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5240 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5241 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5242 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5243 pwell,space/w
5244
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5245 # Note that corenvar, corepvar are not considered devices, and extract as
5246 # parasitic capacitance instead (but cap values need to be added).
5247
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5248 # Extended drain devices (must appear before the regular devices)
5249 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5250 dnwell pwell,space/w error
5251 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5252 dnwell pwell,space/w error
5253 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5254 pwell,space/w nwell error
5255
5256 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5257 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5258 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5259 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5260 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5261
5262 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5263 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5264 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5265 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5266
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5267 device resistor sky130_fd_pr__res_generic_po rmp *poly
5268 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5269 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5270 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5271 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5272#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5273 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5274 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5275#endif (METAL5)
5276
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5277 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5278 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5279 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5280 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5281 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5282 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5283 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5284 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5285 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5286 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5287 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5288 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5289 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5290 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5291 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5292 device resistor mrdn_hv mvndiffres *mvndiff
5293 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5294 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5295
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5296 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5297 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5298 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5299 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5300
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5301 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5302 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5303 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5304 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5305
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]5306 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
5307 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5308 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5309
5310#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5311 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5312 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5313#endif (MIM)
5314
5315end
5316
5317#-----------------------------------------------------
5318# Wiring tool definitions
5319#-----------------------------------------------------
5320
5321wiring
5322 # All wiring values are in nanometers
5323 scalefactor 10
5324
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5325 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5326 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5327 contact v2 280 m2 0 45 m3 25 0
5328#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5329 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5330 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5331#endif (METAL5)
5332
5333 contact pc 170 poly 50 80 li 0 80
5334 contact pdc 170 pdiff 40 60 li 0 80
5335 contact ndc 170 ndiff 40 60 li 0 80
5336 contact psc 170 psd 40 60 li 0 80
5337 contact nsc 170 nsd 40 60 li 0 80
5338
5339end
5340
5341#-----------------------------------------------------
5342# Plain old router. . .
5343#-----------------------------------------------------
5344
5345router
5346end
5347
5348#------------------------------------------------------------
5349# Plowing (restored in magic 8.2, need to fill this section)
5350#------------------------------------------------------------
5351
5352plowing
5353end
5354
5355#-----------------------------------------------------------------
5356# No special plot layers defined (use default PNM color choices)
5357#-----------------------------------------------------------------
5358
5359plot
5360 style pnm
5361 default
5362 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5363 draw fillblock4 no_color_at_all
5364 draw fomfill no_color_at_all
5365 draw polyfill no_color_at_all
5366 draw m1fill no_color_at_all
5367 draw m2fill no_color_at_all
5368 draw m3fill no_color_at_all
5369 draw m4fill no_color_at_all
5370 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5371 draw nwell cwell
5372end
5373