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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / b71e5f8de37db3682a983d362a3de648dcb20e33 / . / sky130 / magic / sky130.tech
blob: 67047b25b1c50f8d088d2e064a43a2238cad073a [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]25 description "SkyWater SKY130: BETA Vendor Open Source rules and DRC"
26 requires magic-8.3.99
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
34#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]35
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
39# device name magic ID layer description
40#------------------------------------------------------------------------
41# sky130_fd_pr__nfet_01v8 nfet standard nFET
42# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]43# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
44# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]45# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]46# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__pfet_01v8 pfet standard pFET
48# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]49# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]50# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
51# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
52# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
53# sky130_fd_pr__nfet_03v3_nvt --- native nFET
54# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
55# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
56# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]57# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
59# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]60# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
61# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]62# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
63# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]64# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]65# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]66# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]68# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
69# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
70# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]71# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]72# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]74# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
75# sky130_fd_pr__res_generic_po npres n+ poly resistor
76# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
77# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
78# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
79# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
80# sky130_fd_pr__cap_var mvvaractor thickox varactor
81# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]82# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
83# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__special_nfet_pass_flash flash nFET device
100# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
101# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
102# sky130_fd_pr__cap_vpp_* Vpp cap
103# sky130_fd_pr__ind_* inductor
104# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]105#--------------------------------------------------------------
106
107#-----------------------------------------------------
108# Tile planes
109#-----------------------------------------------------
110
111planes
112 dwell,dw
113 well,w
114 active,a
115 locali,li1,li
116 metal1,m1
117 metal2,m2
118 metal3,m3
119#ifdef METAL5
120#ifdef MIM
121 cap1,c1
122#endif (MIM)
123 metal4,m4
124#ifdef MIM
125 cap2,c2
126#endif (MIM)
127 metal5,m5
128#endif (METAL5)
129#ifdef REDISTRIBUTION
130 metali,mi
131#endif
132 block,b
133 comment,c
134end
135
136#-----------------------------------------------------
137# Tile types
138#-----------------------------------------------------
139
140types
141# Deep nwell
142 dwell dnwell,dnw
143
144# Wells
145 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]146 well pwell,pw
147 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]148 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]149 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]151
152# Transistors
153 active nmos,ntransistor,nfet
154 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]155 -active npd,npdfet,sramnfet
156 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]157 active pmos,ptransistor,pfet
158 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]159 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]160 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]161 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]162 active mvnmos,mvntransistor,mvnfet
163 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]164 active mvnnmos,mvnntransistor,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]165 -active mvnmosesd,mvntransistoresd,mvnfetesd
166 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]167 active varactor,varact,var
168 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]169
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]170 active pmoslvt,pfetlvt
171 active pmosmvt,pfetmvt
172 active pmoshvt,pfethvt
173 active nmoslvt,nfetlvt
174 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]175 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]176 -active sramnvar,corenvar,corenvaractor
177 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]178
179# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]180 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]181 active ndiff,ndiffusion,ndif
182 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]183 active mvndiff,mvndiffusion,mvndif
184 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]185 active ndiffc,ndcontact,ndc
186 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]187 active mvndiffc,mvndcontact,mvndc
188 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]189 active psubdiff,psubstratepdiff,ppdiff,ppd,psd
190 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]191 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
192 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]193 active psubdiffcont,psubstratepcontact,psc
194 active nsubdiffcont,nsubstratencontact,nsc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]195 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
196 active mvnsubdiffcont,mvnsubstratencontact,mvnsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]197 -active obsactive
198 -active mvobsactive
199
200# Poly
201 active poly,p,polysilicon
202 active polycont,pc,pcontact,polycut,polyc
203 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]204 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]205
206# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]207 active npolyres,npres,mrp1
208 active ppolyres,ppres,xhrpoly
209 active xpolyres,xpres,xres,uhrpoly
210 active ndiffres,rnd,rdn,rndiff
211 active pdiffres,rpd,rdp,rpdiff
212 active mvndiffres,mvrnd,mvrdn,mvrndiff
213 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
214 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]215
216# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]217 active pdiode,pdi
218 active ndiode,ndi
219 active nndiode,nndi
220 active pdiodec,pdic
221 active ndiodec,ndic
222 active nndiodec,nndic
223 active mvpdiode,mvpdi
224 active mvndiode,mvndi
225 active mvpdiodec,mvpdic
226 active mvndiodec,mvndic
227 active pdiodelvt,pdilvt
228 active pdiodehvt,pdihvt
229 active ndiodelvt,ndilvt
230 active pdiodelvtc,pdilvtc
231 active pdiodehvtc,pdihvtc
232 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]233
234# Local Interconnect
235 locali locali,li1,li
236 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]237 locali rlocali,rli1,rli
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]238 locali viali,vial,mcon,lic,licon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]239 -locali obsli1,obsli
240 -locali obsli1c,obslic,obslicon
241
242# Metal 1
243 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]244 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245 metal1 via1,m2contact,m2cut,m2c,via,v,v1
246 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]248 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]249
250# Metal 2
251 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]252 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]253 metal2 via2,m3contact,m3cut,m3c,v2
254 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]255 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256
257# Metal 3
258 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]259 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260 -metal3 obsm3
261#ifdef METAL5
262 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]263 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]264
265#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]266 cap1 mimcap,mim,capm
267 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]268#endif
269
270# Metal 4
271 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]272 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]273 -metal4 obsm4
274 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]275 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276
277#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]278 cap2 mimcap2,mim2,capm2
279 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]280#endif
281
282# Metal 5
283 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]284 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]285 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]286 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]287#endif (METAL5)
288
289#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]290 metal5 mrdlcontact,mrdlc
291 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]292 -metali obsmrdl
293#endif (REDISTRIBUTION)
294
295# Miscellaneous
296 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]297 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]298 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]299 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]300# fixed resistor width identifiers
301 -comment res0p35
302 -comment res0p69
303 -comment res1p41
304 -comment res2p85
305 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]306
307end
308
309#-----------------------------------------------------
310# Magic contact types
311#-----------------------------------------------------
312
313contact
314 pc poly locali
315 ndc ndiff locali
316 pdc pdiff locali
317 nsc nsd locali
318 psc psd locali
319 ndic ndiode locali
320 ndilvtc ndiodelvt locali
321 nndic nndiode locali
322 pdic pdiode locali
323 pdilvtc pdiodelvt locali
324 pdihvtc pdiodehvt locali
325 xpc xpc locali
326
327 mvndc mvndiff locali
328 mvpdc mvpdiff locali
329 mvnsc mvnsd locali
330 mvpsc mvpsd locali
331 mvndic mvndiode locali
332 mvpdic mvpdiode locali
333
334 lic locali metal1
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]335 obslic obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]336
337 via1 metal1 metal2
338 via2 metal2 metal3
339#ifdef METAL5
340 via3 metal3 metal4
341 via4 metal4 metal5
342#endif (METAL5)
343 stackable
344
345#ifdef METAL5
346#ifdef MIM
347 # MiM cap contacts are not stackable!
348 mimcc mimcap metal4
349 mim2cc mimcap2 metal5
350#endif (MIM)
351
352 padl m1 m2 m3 m4 m5 glass
353#else
354 padl m1 m2 m3 glass
355#endif (!METAL5)
356
357#ifdef REDISTRIBUTION
358 mrdlc metal5 mrdl
359#endif (REDISTRIBUTION)
360end
361
362#-----------------------------------------------------
363# Layer aliases
364#-----------------------------------------------------
365
366aliases
367
368 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]369 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]370
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]371 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,nsonos
372 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]373 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]374 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]375 allfetsspecial scnfet,scpfet,scpfethvt
376 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]377 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]378
379 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
380 allnactive allnactivenonfet,allnfets
381 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]382 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]383
384 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
385 allpactive allpactivenonfet,allpfets
386 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388
389 allactivenonfet allnactivenonfet,allpactivenonfet
390 allactive allactivenonfet,allfets
391
392 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
393
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]394 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]395 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]396 alldifflv allndifflv,allpdifflv
397 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
398 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
399 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
400
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]401 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
402 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]403 alldiffmv allndiffmv,allpdiffmv
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]404 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
405 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]406 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
407 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
408 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
409 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
410
411 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]412 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]413
414 allpolyres mrp1,xhrpoly,uhrpoly,rmp
415 allpolynonfet *poly,allpolyres,xpc
416 allpolynonres *poly,allfets,xpc
417
418 allpoly allpolynonfet,allfets
419 allpolynoncap *poly,xpc,allfets,allpolyres
420
421 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
422 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
423 allndiffcontmv mvndc,mvnsc,mvndic
424 allpdiffcontmv mvpdc,mvpsc,mvpdic
425 allndiffcont allndiffcontlv,allndiffcontmv
426 allpdiffcont allpdiffcontlv,allpdiffcontmv
427 alldiffcontlv allndiffcontlv,allpdiffcontlv
428 alldiffcontmv allndiffcontmv,allpdiffcontmv
429 alldiffcont alldiffcontlv,alldiffcontmv
430
431 allcont alldiffcont,pc
432
433 allres allpolyres,allactiveres
434
435 allli *locali,coreli,rli
436 allm1 *m1,rm1
437 allm2 *m2,rm2
438 allm3 *m3,rm3
439#ifdef METAL5
440 allm4 *m4,rm4
441 allm5 *m5,rm5
442#endif (METAL5)
443
444 allpad padl
445
446 psub pwell
447
448end
449
450#-----------------------------------------------------
451# Layer drawing styles
452#-----------------------------------------------------
453
454styles
455 styletype mos
456 dnwell cwell
457 nwell nwell
458 pwell pwell
459 rpwell pwell ptransistor_stripes
460 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]461 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]462 pdiff pdiffusion
463 nsd ndiff_in_nwell
464 psd pdiff_in_pwell
465 nfet ntransistor ntransistor_stripes
466 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]467 npass ntransistor ntransistor_stripes
468 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]469 pfet ptransistor ptransistor_stripes
470 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]471 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]472 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473 var polysilicon ndiff_in_nwell
474 ndc ndiffusion metal1 contact_X'es
475 pdc pdiffusion metal1 contact_X'es
476 nsc ndiff_in_nwell metal1 contact_X'es
477 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]478 corenvar polysilicon ndiff_in_nwell
479 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]480
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]481 pnp nwell ntransistor_stripes
482 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]483
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]484 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]485 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 pfethvt ptransistor ptransistor_stripes implant2
487 nfetlvt ntransistor ntransistor_stripes implant1
488 nsonos ntransistor implant3
489 varhvt polysilicon ndiff_in_nwell implant2
490
491 mvndiff ndiffusion hvndiff_mask
492 mvpdiff pdiffusion hvpdiff_mask
493 mvnsd ndiff_in_nwell hvndiff_mask
494 mvpsd pdiff_in_pwell hvpdiff_mask
495 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]496 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
498 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]499 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]500 mvvar polysilicon ndiff_in_nwell hvndiff_mask
501 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
502 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
503 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
504 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
505
506 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]507 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508 pc polysilicon metal1 contact_X'es
509 npolyres polysilicon silicide_block nselect2
510 ppolyres polysilicon silicide_block pselect2
511 xpc polysilicon pselect2 metal1 contact_X'es
512 rmp polysilicon poly_resist_stripes
513
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]514 res0p35 implant1
515 res0p69 implant1
516 res1p41 implant1
517 res2p85 implant1
518 res5p73 implant1
519
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]520 pdiode pdiffusion pselect2
521 ndiode ndiffusion nselect2
522 pdiodec pdiffusion pselect2 metal1 contact_X'es
523 ndiodec ndiffusion nselect2 metal1 contact_X'es
524
525 nndiode ndiffusion nselect2 implant3
526 ndiodelvt ndiffusion nselect2 implant1
527 pdiodelvt pdiffusion pselect2 implant1
528 pdiodehvt pdiffusion pselect2 implant2
529 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
530 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
531 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
532
533 mvpdiode pdiffusion pselect2 hvpdiff_mask
534 mvndiode ndiffusion nselect2 hvndiff_mask
535 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
536 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
537 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
538
539 locali metal1
540 coreli metal1
541 rli metal1 poly_resist_stripes
542 lic metal1 metal2 via1arrow
543 obsli metal1
544 obslic metal1 metal2 via1arrow
545
546 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]547 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]548 rm1 metal2 poly_resist_stripes
549 obsm1 metal2
550 m2c metal2 metal3 via2arrow
551 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]552 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]553 rm2 metal3 poly_resist_stripes
554 obsm2 metal3
555 m3c metal3 metal4 via3alt
556 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]557 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]558 rm3 metal4 poly_resist_stripes
559 obsm3 metal4
560#ifdef METAL5
561#ifdef MIM
562 mimcap metal3 mems
563 mimcc metal3 contact_X'es mems
564 mimcap2 metal4 mems
565 mim2cc metal4 contact_X'es mems
566#endif (MIM)
567 via3 metal4 metal5 via4
568 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]569 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]570 rm4 metal5 poly_resist_stripes
571 obsm4 metal5
572 via4 metal5 metal6 via5
573 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]574 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]575 rm5 metal6 poly_resist_stripes
576 obsm5 metal6
577#endif (METAL5)
578#ifdef REDISTRIBUTION
579 mrdlc metal6 metal7 via6
580 metalrdl metal7
581 obsmrdl metal7
582#endif (REDISTRIBUTION)
583
584 glass overglass
585 mrp1 poly_resist poly_resist_stripes
586 xhrpoly poly_resist silicide_block
587 uhrpoly poly_resist
588 ndiffres ndiffusion ndop_stripes
589 pdiffres pdiffusion pdop_stripes
590 mvndiffres ndiffusion hvndiff_mask ndop_stripes
591 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
592 comment comment
593 error_p error_waffle
594 error_s error_waffle
595 error_ps error_waffle
596 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]597 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]598
599 obswell cwell
600 obsactive implant4
601
602#ifndef METAL5
603 padl metal4 via4 overglass
604#else
605 padl metal6 via6 overglass
606#endif
607
608 magnet substrate_field_implant
609 rotate via3alt
610 fence via5
611end
612
613#-----------------------------------------------------
614# Special paint/erase rules
615#-----------------------------------------------------
616
617compose
618 compose nfet poly ndiff
619 compose pfet poly pdiff
620 compose var poly nsd
621
622 compose mvnfet poly mvndiff
623 compose mvpfet poly mvpdiff
624 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]625
626 paint obslic locali via1
Tim Edwardsd44d18d2020-09-22 15:29:11 -0400[diff] [blame]627 paint obslic obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]628
629 paint ndc nwell pdc
630 paint nfet nwell pfet
631 paint scnfet nwell scpfet
632 paint ndiff nwell pdiff
633 paint psd nwell nsd
634 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]635 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]636
637 paint pdc pwell ndc
638 paint pfet pwell nfet
639 paint scpfet pwell scnfet
640 paint pdiff pwell ndiff
641 paint nsd pwell psd
642 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]643 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]644
645 paint pdc coreli pdc
646 paint ndc coreli ndc
647 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]648 paint nsc coreli nsc
649 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]650 paint viali coreli viali
651
652 paint coreli pdc pdc
653 paint coreli ndc ndc
654 paint coreli pc pc
655 paint coreli nsc nsc
656 paint coreli psc psc
657 paint coreli viali viali
658
659#ifdef METAL5
660 paint m4 obsm4 m4
661 paint m5 obsm5 m5
662#endif (METAL5)
663end
664
665#-----------------------------------------------------
666# Electrical connectivity
667#-----------------------------------------------------
668
669connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]670 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
671 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]672 *li,coreli *li,coreli
Tim Edwards48db3e12020-09-22 15:41:41 -0400[diff] [blame]673 *m1,m1fill,obslic *m1,m1fill,obslic
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]674 *m2,m2fill *m2,m2fill
675 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]676#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]677 *m4,m4fill *m4,m4fill
678 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]679#ifdef MIM
680 *mimcap *mimcap
681 *mimcap2 *mimcap2
682#endif (MIM)
683#endif (METAL5)
684 allnactivenonfet allnactivenonfet
685 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]686 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]687#ifdef REDISTRIBUTION
688 # RDL connects to m5 (i.e., padl) through glass cut
689 *mrdl *mrdl
690 glass metrdl
691#endif (REDISTRIBUTION)
692end
693
694#-----------------------------------------------------
695# CIF/GDS output layer definitions
696#-----------------------------------------------------
697# NOTE: All values in this section MUST be multiples of 25
698# or else magic will scale below the allowed layout grid size
699
700cifoutput
701
702#----------------------------------------------------------------
703style gdsii
704# NOTE: This section is used for actual GDS output
705#----------------------------------------------------------------
706 scalefactor 10 nanometers
707 options calma-permissive-labels
708 gridlimit 5
709
710#----------------------------------------------------------------
711# Create a temp layer from the cell bounding box for use in
712# generating ID layers. Note that "boundary", unlike "bbox",
713# requires the FIXED_BBOX property (abutment box) in the cell.
714#----------------------------------------------------------------
715 templayer CELLBOUND
716 boundary
717
718#----------------------------------------------------------------
719# BOUND
720#----------------------------------------------------------------
721 layer BOUND CELLBOUND
722 calma 235 4
723
724# Create a boundary outside of an abutment box, so that layers
725# can be made to stretch to the abutment box edges. First strink
726# so that any box that would be so small as to interact with
727# itself will be removed.
728
729 templayer CELLRING CELLBOUND
730 shrink 345
731 grow 545
732 and-not CELLBOUND
733
734#----------------------------------------------------------------
735# DNWELL
736#----------------------------------------------------------------
737
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]738 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]739 calma 64 18
740
741 layer PWRES rpw
742 and dnwell
743 calma 64 13
744
745#----------------------------------------------------------------
746# NWELL
747#----------------------------------------------------------------
748
749 layer NWELL allnwell
750 bloat-all rpw dnwell
751 and-not rpw,pwell
752 calma 64 20
753
754 layer WELLTXT
755 labels allnwell noport
756 calma 64 16
757
758 layer WELLPIN
759 labels allnwell port
760 calma 64 5
761
762#----------------------------------------------------------------
763# SUB (text/port only)
764#----------------------------------------------------------------
765
766 layer SUBTXT
767 labels pwell noport
768 calma 122 16
769
770 layer SUBPIN
771 labels pwell port
772 calma 64 59
773
774#----------------------------------------------------------------
775# DIFF
776#----------------------------------------------------------------
777
778 layer DIFF allnactivenontap,allpactivenontap,allactiveres
779 labels allnactivenontap,allpactivenontap
780 calma 65 20
781
782#----------------------------------------------------------------
783# TAP
784#----------------------------------------------------------------
785
786 layer TAP allnactivetap,allpactivetap
787 labels allnactivetap,allpactivetap
788 calma 65 44
789
790#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]791# FOM
792#----------------------------------------------------------------
793
794 layer FOMFILL fomfill
795 labels fomfill
796 calma 65 28
797
798#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]799# PPLUS, NPLUS (PSDM, NSDM)
800#----------------------------------------------------------------
801
802 templayer basePPLUS pdiffres,mvpdiffres
803 grow 15
804 or xhrpoly,uhrpoly,xpc
805 grow 110
806 bloat-or allpactivetap * 125 allnactivenontap 0
807 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]808
809 templayer baseNPLUS ndiffres,mvndiffres
810 grow 125
811 bloat-or allnactivetap * 125 allpactivenontap 0
812 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]813
814 templayer extendPPLUS basePPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]815 bridge 380 380
816 and-not baseNPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]817 and-not CELLRING
818
819 layer PPLUS basePPLUS,extendPPLUS
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]820 grow 185
821 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]822 close 265000
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]823 mask-hints PPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]824 calma 94 20
825
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]826 templayer extendNPLUS baseNPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]827 bridge 380 380
828 and-not basePPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]829 and-not CELLRING
830
831 layer NPLUS baseNPLUS,extendNPLUS
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]832 grow 185
833 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]834 close 265000
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]835 mask-hints NPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]836 calma 93 44
837
838#----------------------------------------------------------------
839# LVTN
840#----------------------------------------------------------------
841
842 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
843 grow 180
844 bridge 380 380
845 grow 185
846 shrink 185
847 close 265000
848 calma 125 44
849
850#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]851# HVTR
852#----------------------------------------------------------------
853
854 layer HVTR pfetmvt
855 grow 180
856 bridge 380 380
857 grow 185
858 shrink 185
859 close 265000
860 calma 18 20
861
862#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]863# HVTP
864#----------------------------------------------------------------
865
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]866 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]867 grow 180
868 bridge 380 380
869 grow 185
870 shrink 185
871 close 265000
872 calma 78 44
873
874#----------------------------------------------------------------
875# SONOS
876#----------------------------------------------------------------
877
878 layer SONOS nsonos
879 grow 100
880 grow-min 410
881 bridge 500 410
882 grow 250
883 shrink 250
884 calma 80 20
885
886#----------------------------------------------------------------
887# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]888# coreli layer indicates a cell needing COREID. Also, devices
889# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]890#----------------------------------------------------------------
891
892 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]893 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]894 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]895 calma 81 2
896
897#----------------------------------------------------------------
898# STDCELL applies to all cells containing scnfet or scpfet.
899#----------------------------------------------------------------
900
901 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]902 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]903 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]904 calma 81 4
905
906#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]907# ESDID is a marker layer for ESD devices in the padframe I/O.
908#----------------------------------------------------------------
909
910 layer ESDID
911 bloat-all mvnfetesd *mvndiff,*poly
912 bloat-all mvpfetesd *mvpdiff,*poly
913 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]914 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]915 calma 81 19
916
917#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]918# NPNID and PNPID apply to bipolar transistors
919#----------------------------------------------------------------
920
921 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]922 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]923 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]924 calma 82 20
925
926 templayer pnparea pnp
927 grow 400
928
929 layer PNPID
930 bloat-all pnparea *psd
931 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]932 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]933 calma 82 44
934
935#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]936# RPM
937#----------------------------------------------------------------
938
939 layer RPM
940 bloat-all xhrpoly xpc
941 grow 200
942 grow-min 1270
943 grow 420
944 shrink 420
945 calma 86 20
946
947#----------------------------------------------------------------
948# URPM (2kOhms/sq. poly implant)
949#----------------------------------------------------------------
950
951 layer URPM
952 bloat-all uhrpoly xpc
953 grow 200
954 grow-min 1270
955 grow 420
956 shrink 420
957 calma 79 20
958
959#----------------------------------------------------------------
960# LDNTM (Tip implant for SONOS FETs)
961#----------------------------------------------------------------
962
963 layer LDNTM
964 bloat-all nsonos *ndiff
965 grow 185
966 grow 345
967 shrink 345
968 calma 11 44
969
970#----------------------------------------------------------------
971# HVNTM (Tip implant for MV ndiff devices)
972#----------------------------------------------------------------
973
974 templayer hvntm_block *mvpsd
975 grow 185
976
977 layer HVNTM
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]978 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]979 bloat-all mvvaractor *mvnsd
980 and-not hvntm_block
981 grow 185
982 grow 345
983 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]984 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]985 calma 125 20
986
987#----------------------------------------------------------------
988# POLY
989#----------------------------------------------------------------
990
991 layer POLY allpoly
992 calma 66 20
993
994 layer POLYTXT
995 labels allpoly noport
996 calma 66 16
997
998 layer POLYPIN
999 labels allpoly port
1000 calma 66 5
1001
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1002 layer POLYFILL polyfill
1003 labels polyfill
1004 calma 66 28
1005
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1006#----------------------------------------------------------------
1007# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
1008#----------------------------------------------------------------
1009
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1010 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1011 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1012 bloat-all alldiffmv nwell
1013 grow 345
1014 shrink 345
1015
1016 templayer large_ptap_mv thkox_area
1017 shrink 420
1018 grow 420
1019
1020 templayer small_ptap_mv thkox_area
1021 and-not large_ptap_mv
1022 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1023 grow-min 840
1024
1025 templayer baseTHKOX thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1026 bridge 700 600
1027 grow 345
1028 shrink 345
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1029
1030 templayer extendTHKOX baseTHKOX,CELLRING
1031 grow 345
1032 shrink 345
1033 and-not CELLRING
1034
1035 layer THKOX baseTHKOX,extendTHKOX
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1036 mask-hints THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1037 calma 75 20
1038
1039#----------------------------------------------------------------
1040# CONT (LICON)
1041#----------------------------------------------------------------
1042
1043 layer CONT allcont
1044 squares-grid 0 170 170
1045 calma 66 44
1046
1047 # Contact for pres is different than other LICON contacts
1048 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1049 templayer xpc_horiz xpc
1050 shrink 1007
1051 grow 1007
1052
1053 layer CONT xpc
1054 and-not xpc_horiz
1055 # Force long edge vertical for contacts narrower than 2um
1056 # Minimum space is 350 but 520 satisfies no. of contacts rule
1057 slots 80 190 520 80 2000 350
1058 calma 66 44
1059
1060 layer CONT xpc
1061 and xpc_horiz
1062 # Force long edge vertical for contacts wider than 2um
1063 # Minimum space is 350 but 520 satisfies no. of contacts rule
1064 slots 80 2000 350 80 190 520
1065 calma 66 44
1066
1067#----------------------------------------------------------------
1068# NPC (Nitride poly cut)
1069# surrounds CONT (LICON) on poly only (i.e., pc)
1070#----------------------------------------------------------------
1071
1072 layer NPC pc
1073 squares-grid 0 170 170
1074 grow 100
1075 bridge 270 270
1076 grow 130
1077 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1078 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1079 calma 95 20
1080
1081 # NPC is also generated on xhrpoly and uhrpoly resistors
1082
1083 layer NPC xpc,xhrpoly,uhrpoly
1084 # xpc surrounds precision_resistor by 0.095um
1085 grow 95
1086 grow 130
1087 shrink 130
1088 calma 95 20
1089
1090#----------------------------------------------------------------
1091# Device markers
1092#----------------------------------------------------------------
1093
1094 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1095 calma 65 13
1096
1097 layer POLYRES mrp1
1098 calma 66 13
1099
1100 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1101 layer POLYSHORT rmp
1102 calma 66 15
1103
1104 # POLYRES extends to edge of contact cut
1105 layer POLYRES xhrpoly,uhrpoly
1106 grow 60
1107 and xpc
1108 or xhrpoly,uhrpoly
1109 calma 66 13
1110
1111 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1112 # To be done: Expand to include anode, cathode, and guard ring
1113 calma 81 23
1114
1115#----------------------------------------------------------------
1116# LI
1117#----------------------------------------------------------------
1118 layer LI allli
1119 calma 67 20
1120
1121 layer LITXT
1122 labels *locali,coreli noport
1123 calma 67 16
1124
1125 layer LIPIN
1126 labels *locali,coreli port
1127 calma 67 5
1128
1129 layer LIRES rli
1130 labels rli
1131 calma 67 13
1132
1133#----------------------------------------------------------------
1134# MCON
1135#----------------------------------------------------------------
1136 layer MCON lic
1137 squares-grid 0 170 190
1138 calma 67 44
1139
1140#----------------------------------------------------------------
1141# MET1
1142#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1143 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1144 calma 68 20
1145
1146 layer MET1TXT
1147 labels allm1 noport
1148 calma 68 16
1149
1150 layer MET1PIN
1151 labels allm1 port
1152 calma 68 5
1153
1154 layer MET1RES rm1
1155 labels rm1
1156 calma 68 13
1157
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1158 layer MET1FILL m1fill
1159 labels m1fill
1160 calma 68 28
1161
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1162#----------------------------------------------------------------
1163# VIA1
1164#----------------------------------------------------------------
1165 layer VIA1 via1
1166 squares-grid 55 150 170
1167 calma 68 44
1168
1169#----------------------------------------------------------------
1170# MET2
1171#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1172 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1173 calma 69 20
1174
1175 layer MET2TXT
1176 labels allm2 noport
1177 calma 69 16
1178
1179 layer MET2PIN
1180 labels allm2 port
1181 calma 69 5
1182
1183 layer MET2RES rm2
1184 labels rm2
1185 calma 69 13
1186
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1187 layer MET2FILL m2fill
1188 labels m2fill
1189 calma 69 28
1190
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1191#----------------------------------------------------------------
1192# VIA2
1193#----------------------------------------------------------------
1194 layer VIA2 via2
1195 squares-grid 40 200 200
1196 calma 69 44
1197
1198#----------------------------------------------------------------
1199# MET3
1200#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1201 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1202 calma 70 20
1203
1204 layer MET3TXT
1205 labels allm3 noport
1206 calma 70 16
1207
1208 layer MET3PIN
1209 labels allm3 port
1210 calma 70 5
1211
1212 layer MET3RES rm3
1213 labels rm3
1214 calma 70 13
1215
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1216 layer MET3FILL m3fill
1217 labels m3fill
1218 calma 70 28
1219
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1220#ifdef METAL5
1221#----------------------------------------------------------------
1222# VIA3
1223#----------------------------------------------------------------
1224 layer VIA3 via3
1225#ifdef MIM
1226 or mimcc
1227#endif (MIM)
1228 squares-grid 60 200 200
1229 calma 70 44
1230
1231#----------------------------------------------------------------
1232# MET4
1233#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1234 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1235 calma 71 20
1236
1237 layer MET4TXT
1238 labels allm4 noport
1239 calma 71 16
1240
1241 layer MET4PIN
1242 labels allm4 port
1243 calma 71 5
1244
1245 layer MET4RES rm4
1246 labels rm4
1247 calma 71 13
1248
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1249 layer MET4FILL m4fill
1250 labels m4fill
1251 calma 71 28
1252
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1253#----------------------------------------------------------------
1254# VIA4
1255#----------------------------------------------------------------
1256 layer VIA4 via4
1257#ifdef MIM
1258 or mim2cc
1259#endif (MIM)
1260 squares-grid 190 800 800
1261 calma 71 44
1262
1263#----------------------------------------------------------------
1264# MET5
1265#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1266 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1267 calma 72 20
1268
1269 layer MET5TXT
1270 labels allm5 noport
1271 calma 72 16
1272
1273 layer MET5PIN
1274 labels allm5 port
1275 calma 72 5
1276
1277 layer MET5RES rm5
1278 labels rm5
1279 calma 72 13
1280
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1281 layer MET5FILL m5fill
1282 labels m5fill
1283 calma 72 28
1284
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1285#endif (METAL5)
1286
1287#ifdef REDISTRIBUTION
1288#----------------------------------------------------------------
1289# RDL
1290#----------------------------------------------------------------
1291 layer RDL *metrdl
1292 calma 74 20
1293
1294 layer RDLTXT
1295 labels *metrdl noport
1296 calma 74 16
1297
1298 layer RDLPIN
1299 labels *metrdl port
1300 calma 74 5
1301
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1302 layer PI1 *metrdl
1303 and padl,glass
1304 # Test only---needs GDS layer number
1305
1306 layer UBM *metrdl
1307 shrink 50000
1308 grow 40000
1309 # Test only---needs GDS layer number
1310
1311 layer PI2 *metrdl
1312 shrink 50000
1313 grow 25000
1314 # Test only---needs GDS layer number
1315
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1316#endif REDISTRIBUTION
1317
1318#----------------------------------------------------------------
1319# GLASS
1320#----------------------------------------------------------------
1321 layer GLASS glass
1322 calma 76 20
1323
1324#ifdef MIM
1325#----------------------------------------------------------------
1326# CAPM
1327#----------------------------------------------------------------
1328 layer CAPM *mimcap
1329 labels mimcap
1330 calma 89 44
1331
1332 layer CAPM2 *mimcap2
1333 labels mimcap2
1334 calma 97 44
1335#endif (MIM)
1336
1337#----------------------------------------------------------------
1338# Chip top level marker for DRC latchup rules to check 15um
1339# distance to taps (otherwise 6um is used)
1340#----------------------------------------------------------------
1341
1342 layer LOWTAPDENSITY
1343 bbox top
1344 # Clear 200um for pads + 50um for required high tap density
1345 # in critical area.
1346 shrink 250000
1347 calma 81 14
1348
1349#----------------------------------------------------------------
1350# FILLBLOCK
1351#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1352 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1353 calma 62 24
1354
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1355 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1356 calma 105 52
1357
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1358 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1359 calma 107 24
1360
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1361 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1362 calma 112 4
1363
1364 render DNWELL cwell -0.1 0.1
1365 render NWELL nwell 0.0 0.2062
1366 render DIFF ndiffusion 0.2062 0.12
1367 render TAP pdiffusion 0.2062 0.12
1368 render POLY polysilicon 0.3262 0.18
1369 render CONT via 0.5062 0.43
1370 render LI metal1 0.9361 0.10
1371 render MCON via 1.0361 0.34
1372 render MET1 metal2 1.3761 0.36
1373 render VIA1 via 1.7361 0.27
1374 render MET2 metal3 2.0061 0.36
1375 render VIA2 via 2.3661 0.42
1376 render MET3 metal4 2.7861 0.845
1377#ifdef METAL5
1378 render VIA3 via 3.6311 0.39
1379 render MET4 metal5 4.0211 0.845
1380 render VIA4 via 4.8661 0.505
1381 render MET5 metal6 5.3711 1.26
1382 render CAPM metal8 2.4661 0.2
1383 render CAPM2 metal9 3.7311 0.2
1384#ifdef REDISTRIBUTION
1385 render RDL metal7 11.8834 4.0
1386#endif (!REDISTRIBUTION)
1387#endif (!METAL5)
1388
1389#----------------------------------------------------------------
1390style drc
1391#----------------------------------------------------------------
1392# NOTE: This style is used for DRC only, not for GDS output
1393#----------------------------------------------------------------
1394 scalefactor 10 nanometers
1395 options calma-permissive-labels
1396
1397 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1398 templayer dnwell_shrink dnwell
1399 shrink 1030
1400
1401 templayer nwell_missing dnwell
1402 grow 400
1403 and-not dnwell_shrink
1404 and-not nwell
1405
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1406 templayer pwell_in_dnwell dnwell
1407 and-not nwell
1408
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1409 # SONOS nFET devices must be in deep nwell
1410 templayer dnwell_missing nsonos
1411 and-not dnwell
1412
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1413 # SONOS nFET devices must be in cell with abutment box
1414 templayer abutment_box
1415 boundary
1416
1417 templayer bbox_missing nsonos
1418 and-not abutment_box
1419
1420 # Make sure nwell covers varactor poly
1421 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1422 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1423 grow 150
1424 and-not nwell
1425
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1426 # Define MiM cap bottom plate for spacing rule
1427 templayer mim_bottom
1428 bloat-all *mimcap *metal3
1429
1430 # Define MiM2 cap bottom plate for spacing rule
1431 templayer mim2_bottom
1432 bloat-all *mimcap2 *metal4
1433
1434 # Note that metal fill is performed by the foundry and so is not
1435 # an option for a cifoutput style.
1436
1437 # Check latchup rule (15um minimum from tap LICON center to any
1438 # non-tap diffusion. Note that to count as a tap, the diffusion
1439 # must be contacted to LI
1440
1441 templayer ptap_reach psc,mvpsc
1442 and-not dnwell
1443 # grow total is 15um. grow in 0.84um increments to ensure that
1444 # no nwell ring is crossed
1445 grow 840
1446 and-not nwell,dnwell
1447 grow 840
1448 and-not nwell,dnwell
1449 grow 840
1450 and-not nwell,dnwell
1451 grow 840
1452 and-not nwell,dnwell
1453 grow 840
1454 and-not nwell,dnwell
1455 grow 840
1456 and-not nwell,dnwell
1457 grow 840
1458 and-not nwell,dnwell
1459 grow 840
1460 and-not nwell,dnwell
1461 grow 840
1462 and-not nwell,dnwell
1463 grow 840
1464 and-not nwell,dnwell
1465 grow 840
1466 and-not nwell,dnwell
1467 grow 840
1468 and-not nwell,dnwell
1469 grow 840
1470 and-not nwell,dnwell
1471 grow 840
1472 and-not nwell,dnwell
1473 grow 840
1474 and-not nwell,dnwell
1475 grow 840
1476 and-not nwell,dnwell
1477 grow 840
1478 and-not nwell,dnwell
1479 grow 635
1480 and-not nwell,dnwell
1481
1482 templayer ptap_missing *ndiff,*mvndiff
1483 and-not dnwell
1484 and-not ptap_reach
1485
1486 templayer ntap_reach nsc,mvnsc
1487 # grow total is 15um. grow in 1.27um increments to ensure that
1488 # no nwell ring is crossed. There is no difference between
1489 # ntaps in and out of deep nwell.
1490 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1491 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1492 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1493 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1494 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1495 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1496 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1497 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1498 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1499 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1500 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1501 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1502 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1503 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1504 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1505 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1506 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1507 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1508 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1509 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1510 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1511 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1512 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1513 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1514
1515 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1516 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1517 and-not ntap_reach
1518
1519 templayer dptap_reach psc,mvpsc
1520 and dnwell
1521 grow 840
1522 and-not nwell
1523 and dnwell
1524 grow 840
1525 and-not nwell
1526 and dnwell
1527 grow 840
1528 and-not nwell
1529 and dnwell
1530 grow 840
1531 and-not nwell
1532 and dnwell
1533 grow 840
1534 and-not nwell
1535 and dnwell
1536 grow 840
1537 and-not nwell
1538 and dnwell
1539 grow 840
1540 and-not nwell
1541 and dnwell
1542 grow 840
1543 and-not nwell
1544 and dnwell
1545 grow 840
1546 and-not nwell
1547 and dnwell
1548 grow 840
1549 and-not nwell
1550 and dnwell
1551 grow 840
1552 and-not nwell
1553 and dnwell
1554 grow 840
1555 and-not nwell
1556 and dnwell
1557 grow 840
1558 and-not nwell
1559 and dnwell
1560 grow 840
1561 and-not nwell
1562 and dnwell
1563 grow 840
1564 and-not nwell
1565 and dnwell
1566 grow 840
1567 and-not nwell
1568 and dnwell
1569 grow 840
1570 and-not nwell
1571 and dnwell
1572 grow 635
1573 and-not nwell
1574 and dnwell
1575
1576 templayer dptap_missing *ndiff,*mvndiff
1577 and dnwell
1578 and-not dptap_reach
1579
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1580 templayer pdiff_crosses_dnwell dnwell
1581 grow 20
1582 and-not dnwell
1583 and allpdifflv,allpdiffmv
1584
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1585 # MV nwell must be 2um from any other nwell
1586 templayer mvnwell
1587 bloat-all alldiffmv nwell
1588 grow-min 840
1589 bridge 700 600
1590
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1591 # Simple spacing checks to lvnwell must use CIF-DRC rule
1592 templayer allmvdiffnowell *mvndiff,*mvpsd
1593
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1594 templayer lvnwell nwell
1595 and-not mvnwell
1596
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1597 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1598 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1599
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1600 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1601 and-not nwell_with_tap
1602
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1603 templayer tap_with_licon
1604 bloat-all psc,mvpsc psd,mvpsd
1605 bloat-all nsc,mvnsc nsd,mvnsd
1606
1607 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1608 and-not tap_with_licon
1609
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1610 # Make sure varactor nwell contains no P diffusion
1611 templayer pdiff_in_varactor_well
1612 bloat-all varactor,mvvaractor nwell
1613 and allpactive
1614
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1615 # HVNTM spacing requires recreating HVNTM
1616 templayer hvntm_block *mvpsd
1617 grow 185
1618
1619 templayer hvntm_generate
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]1620 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1621 bloat-all mvvaractor *mvnsd
1622 and-not hvntm_block
1623 grow 185
1624 grow 345
1625 shrink 345
1626 and-not hvntm_block
1627
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1628 templayer m1_small_hole allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1629 close 140000
1630
1631 templayer m1_hole_empty m1_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1632 and-not allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1633
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1634 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1635 close 140000
1636
1637 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1638 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1639
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1640 templayer m1_huge allm1
1641 shrink 1500
1642 grow 1500
1643
1644 templayer m1_large_halo m1_huge
1645 grow 280
1646 and-not m1_huge
1647 and allm1
1648
1649 templayer m2_huge allm2
1650 shrink 1500
1651 grow 1500
1652
1653 templayer m2_large_halo m2_huge
1654 grow 280
1655 and-not m2_huge
1656 and allm2
1657
1658 templayer m3_huge allm3
1659 shrink 1500
1660 grow 1500
1661
1662 templayer m3_large_halo m3_huge
1663 grow 400
1664 and-not m3_huge
1665 and allm3
1666
1667 templayer m4_huge allm4
1668 shrink 1500
1669 grow 1500
1670
1671 templayer m4_large_halo m4_huge
1672 grow 400
1673 and-not m4_huge
1674 and allm4
1675
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1676#ifdef EXPERIMENTAL
1677#----------------------------------------------------------------
1678style paint
1679#----------------------------------------------------------------
1680# NOTE: This style is used for database manipulations only via
1681# the "cif paint" command.
1682#----------------------------------------------------------------
1683
1684 scalefactor 10 nanometers
1685
1686 templayer m1grow *m1
1687 grow 290
1688
1689 # layer listrap: Use the following set of commands to strap local
1690 # interconnect wires with metal1 (inside the cursor box) to satisfy
1691 # the maximum aspect ratio rule for local interconnect:
1692 #
1693 # tech unlock *
1694 # cif ostyle paint
1695 # cif paint m1strap comment
1696 # cif paint m1strap m1
1697 # cif paint listrap licon
1698 # erase comment
1699
1700 templayer m1strap *li
1701 and-not m1grow
1702 grow 30
1703
1704 templayer listrap comment
1705 slots 30 170 170 60
1706
1707#endif (EXPERIMENTAL)
1708
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1709#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1710style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1711#----------------------------------------------------------------
1712# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1713# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1714#----------------------------------------------------------------
1715 scalefactor 10 nanometers
1716 options calma-permissive-labels
1717 gridlimit 5
1718
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1719#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1720# Generate and retain a layer representing the bounding box.
1721#
1722# For variant ():
1723# The bounding box is the full extent of geometry on the top level
1724# cell.
1725#
1726# For variant (tiled):
1727# Use with a script that breaks layout into flattened tiles and runs
1728# fill individually on each. The tiles should be larger than the
1729# step size, and each should draw a layer "comment" the size of the
1730# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1731#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1732
1733 variants ()
1734 templayer topbox
1735 bbox top
1736
1737 variants (tiled)
1738 templayer topbox comment
1739 # Each tile imposes the full keepout distance rule of
1740 # 3um on all sides.
1741 shrink 1500
1742
1743 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1744
1745#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1746# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1747# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1748# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1749# Enclosure by nwell = Diff/Tap 8 = 0.18um
1750#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1751
1752 templayer mvnwell
1753 bloat-all alldiffmv nwell
1754
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1755 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1756 and-not mvnwell
1757
1758 templayer well_shrink mvnwell
1759 shrink 250
1760 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1761 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1762 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1763 grow 340
1764 and-not well_shrink
1765
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1766#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1767# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1768#---------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1769 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obspoly,obsactive
1770 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1771 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1772 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1773
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]1774 templayer obstruct_poly alldiff,allpolyfomfill,polyfill,obspoly,obsactive
1775 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1776 grow 1000
1777
1778#---------------------------------------------------
1779# FOM and POLY fill
1780#---------------------------------------------------
1781 templayer fomfill_pass1 topbox
1782 slots 0 4080 1320 0 4080 1320 1360 0
1783 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1784 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1785 shrink 2035
1786 grow 2035
1787
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1788#---------------------------------------------------
1789
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1790 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1791 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1792 or obstruct_poly
1793 templayer polyfill_pass1 topbox
1794 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1795 and-not obstruct_poly_pass1
1796 and topbox
1797 shrink 355
1798 grow 355
1799
1800#---------------------------------------------------
1801
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1802 templayer obstruct_fom_pass2 fomfill_pass1
1803 grow 1290
1804 or polyfill_pass1
1805 grow 300
1806 or obstruct_fom
1807 templayer fomfill_pass2 topbox
1808 slots 0 2500 1320 0 2500 1320 1360 0
1809 and-not obstruct_fom_pass2
1810 and topbox
1811 shrink 1245
1812 grow 1245
1813
1814#---------------------------------------------------
1815
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1816 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1817 grow 60
1818 or fomfill_pass1,fomfill_pass2
1819 grow 300
1820 or obstruct_poly
1821 templayer polyfill_coarse topbox
1822 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1823 and-not obstruct_poly_coarse
1824 and topbox
1825 shrink 355
1826 grow 355
1827
1828#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1829 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1830 grow 60
1831 or fomfill_pass1,fomfill_pass2
1832 grow 300
1833 or obstruct_poly
1834 templayer polyfill_medium topbox
1835 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1836 and-not obstruct_poly_medium
1837 and topbox
1838 shrink 265
1839 grow 265
1840
1841#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1842 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1843 grow 60
1844 or fomfill_pass1,fomfill_pass2
1845 grow 300
1846 or obstruct_poly
1847 templayer polyfill_fine topbox
1848 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1849 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1850 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1851 shrink 235
1852 grow 235
1853
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1854#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1855
1856 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1857 grow 1290
1858 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1859 grow 300
1860 or obstruct_fom
1861 templayer fomfill_coarse topbox
1862 slots 0 1500 1320 0 1500 1320 1360 0
1863 and-not obstruct_fom_coarse
1864 and topbox
1865 shrink 745
1866 grow 745
1867
1868#---------------------------------------------------
1869
1870 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1871 grow 1290
1872 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1873 grow 300
1874 or obstruct_fom
1875 templayer fomfill_fine topbox
1876 slots 0 500 400 0 500 400 160 0
1877 and-not obstruct_fom_fine
1878 and topbox
1879 shrink 245
1880 grow 245
1881
1882#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1883 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1884 or fomfill_pass2
1885 or fomfill_coarse
1886 or fomfill_fine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1887 calma 65 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1888
1889 layer POLYFILL polyfill_pass1
1890 or polyfill_coarse
1891 or polyfill_medium
1892 or polyfill_fine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1893 calma 66 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1894
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1895#---------------------------------------------------
1896# MET1 fill
1897#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1898
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1899 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1900 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1901 templayer met1fill_coarse topbox
1902 slots 0 2000 200 0 2000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1903 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1904 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1905 shrink 995
1906 grow 995
1907
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1908 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1909 grow 2800
1910 or met1fill_coarse
1911 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1912 templayer met1fill_medium topbox
1913 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1914 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1915 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1916 shrink 495
1917 grow 495
1918
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1919 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1920 grow 300
1921 or met1fill_coarse,met1fill_medium
1922 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1923 templayer met1fill_fine topbox
1924 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1925 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1926 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1927 shrink 285
1928 grow 285
1929
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1930 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1931 grow 100
1932 or met1fill_coarse,met1fill_medium,met1fill_fine
1933 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1934 templayer met1fill_veryfine topbox
1935 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1936 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1937 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1938 shrink 145
1939 grow 145
1940
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1941 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1942 or met1fill_medium
1943 or met1fill_fine
1944 or met1fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1945 calma 68 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1946
1947#---------------------------------------------------
1948# MET2 fill
1949#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1950 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1951 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1952 templayer met2fill_coarse topbox
1953 slots 0 2000 200 0 2000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1954 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1955 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1956 shrink 995
1957 grow 995
1958
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1959 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1960 grow 2800
1961 or met2fill_coarse
1962 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1963 templayer met2fill_medium topbox
1964 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1965 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1966 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1967 shrink 495
1968 grow 495
1969
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1970 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1971 grow 300
1972 or met2fill_coarse,met2fill_medium
1973 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1974 templayer met2fill_fine topbox
1975 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1976 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1977 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1978 shrink 285
1979 grow 285
1980
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1981 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1982 grow 100
1983 or met2fill_coarse,met2fill_medium,met2fill_fine
1984 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1985 templayer met2fill_veryfine topbox
1986 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1987 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1988 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1989 shrink 145
1990 grow 145
1991
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1992 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1993 or met2fill_medium
1994 or met2fill_fine
1995 or met2fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1996 calma 69 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1997
1998#---------------------------------------------------
1999# MET3 fill
2000#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2001 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2002 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2003 templayer met3fill_coarse topbox
2004 slots 0 2000 300 0 2000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2005 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2006 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2007 shrink 995
2008 grow 995
2009
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2010 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2011 grow 2700
2012 or met3fill_coarse
2013 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2014 templayer met3fill_medium topbox
2015 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2016 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2017 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2018 shrink 495
2019 grow 495
2020
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2021 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2022 grow 200
2023 or met3fill_coarse,met3fill_medium
2024 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2025 templayer met3fill_fine topbox
2026 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2027 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2028 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2029 shrink 285
2030 grow 285
2031
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2032 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2033 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2034 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2035 or met3fill_coarse,met3fill_medium,met3fill_fine
2036 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2037 templayer met3fill_veryfine topbox
2038 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2039 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2040 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2041 shrink 195
2042 grow 195
2043
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2044 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2045 or met3fill_medium
2046 or met3fill_fine
2047 or met3fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2048 calma 70 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2049
2050#ifdef METAL5
2051#---------------------------------------------------
2052# MET4 fill
2053#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2054 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2055 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2056 templayer met4fill_coarse topbox
2057 slots 0 2000 300 0 2000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2058 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2059 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2060 shrink 995
2061 grow 995
2062
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2063 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2064 grow 2700
2065 or met4fill_coarse
2066 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2067 templayer met4fill_medium topbox
2068 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2069 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame^]2070 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2071 shrink 495
2072 grow 495
2073
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2074 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2075 grow 200
2076 or met4fill_coarse,met4fill_medium
2077 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2078 templayer met4fill_fine topbox
2079 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2080 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2081 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2082 shrink 285
2083 grow 285
2084
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2085 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2086 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2087 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2088 or met4fill_coarse,met4fill_medium,met4fill_fine
2089 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2090 templayer met4fill_veryfine topbox
2091 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2092 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2093 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2094 shrink 195
2095 grow 195
2096
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2097 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2098 or met4fill_medium
2099 or met4fill_fine
2100 or met4fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2101 calma 71 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2102
2103#---------------------------------------------------
2104# MET5 fill
2105#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2106 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2107 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2108 templayer met5fill_gen topbox
2109 slots 0 3000 1600 0 3000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2110 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2111 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2112 shrink 1495
2113 grow 1495
2114
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2115 layer MET5FILL met5fill_gen
2116 calma 72 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2117#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2118
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2119end
2120
2121#-----------------------------------------------------------------------
2122cifinput
2123#-----------------------------------------------------------------------
2124# NOTE: All values in this section MUST be multiples of 25
2125# or else magic will scale below the allowed layout grid size
2126#-----------------------------------------------------------------------
2127
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2128style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2129 scalefactor 10 nanometers
2130 gridlimit 5
2131
2132 options ignore-unknown-layer-labels no-reconnect-labels
2133
2134#ifndef MIM
2135 ignore CAPM
2136 ignore CAPM2
2137#endif (!MIM)
2138#ifndef METAL5
2139 ignore MET4,VIA3
2140 ignore MET5,VIA4
2141#endif
2142 ignore NPC
2143 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2144 ignore CAPID
2145 ignore LDNTM
2146 ignore HVNTM
2147 ignore POLYMOD
2148 ignore LOWTAPDENSITY
2149
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2150 layer pnp NWELL,WELLTXT,WELLPIN
2151 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2152 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2153 variants (vendor)
2154 labels WELLTXT port
2155 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2156 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2157 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2158 labels WELLPIN port
2159
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2160 layer nwell NWELL,WELLTXT,WELLPIN
2161 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2162 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2163 variants (vendor)
2164 labels WELLTXT port
2165 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2166 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2167 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2168 labels WELLPIN port
2169
2170 layer pwell SUBTXT,SUBPIN
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2171 variants (vendor)
2172 labels SUBTXT port
2173 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2174 labels SUBTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2175 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2176 labels SUBPIN port
2177
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2178 # Always draw pwell under p-tap
2179 layer pwell TAP
2180 and-not NWELL
2181
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2182 layer dnwell DNWELL
2183 labels DNWELL
2184
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2185 layer npn DNWELL
2186 and-not NWELL
2187 and NPNID
2188
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2189 layer rpw PWRES
2190 and DNWELL
2191 labels PWRES
2192
2193 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2194 and-not POLY
2195 and-not NWELL
2196 and-not PPLUS
2197 and-not DIODE
2198 and-not DIFFRES
2199 and-not THKOX
2200 and NPLUS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2201 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2202 copyup ndifcheck
2203 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2204 variants (vendor)
2205 labels DIFFTXT port
2206 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2207 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2208 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2209 labels DIFFPIN port
2210 labels TAPPIN port
2211
2212 layer ndiff ndiffarea
2213
2214 # Copy ndiff areas up for contact checks
2215 templayer xndifcheck ndifcheck
2216 copyup ndifcheck
2217
2218 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2219 and-not POLY
2220 and-not NWELL
2221 and-not PPLUS
2222 and-not DIODE
2223 and-not DIFFRES
2224 and THKOX
2225 and NPLUS
2226 copyup ndifcheck
2227 labels DIFF
2228 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2229 variants (vendor)
2230 labels DIFFTXT port
2231 variants ()
2232 labels DIFFTXT text
2233 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2234 labels DIFFPIN port
2235
2236 layer mvndiff mvndiffarea
2237
2238 # Copy ndiff areas up for contact checks
2239 templayer mvxndifcheck mvndifcheck
2240 copyup mvndifcheck
2241
2242 layer ndiode DIFF
2243 and NPLUS
2244 and DIODE
2245 and-not NWELL
2246 and-not POLY
2247 and-not PPLUS
2248 and-not THKOX
2249 and-not LVTN
2250 labels DIFF
2251
2252 layer ndiodelvt DIFF
2253 and NPLUS
2254 and DIODE
2255 and-not NWELL
2256 and-not POLY
2257 and-not PPLUS
2258 and-not THKOX
2259 and LVTN
2260 labels DIFF
2261
2262 templayer ndiodearea DIODE
2263 and NPLUS
2264 and-not THKOX
2265 and-not NWELL
2266 copyup DIODE,NPLUS
2267
2268 layer ndiffres DIFFRES
2269 and NPLUS
2270 and-not THKOX
2271 labels DIFF
2272
2273 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2274 and-not POLY
2275 and NWELL
2276 and-not NPLUS
2277 and-not DIODE
2278 and-not THKOX
2279 and PPLUS
2280 copyup pdifcheck
2281 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2282 variants (vendor)
2283 labels DIFFTXT port
2284 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2285 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2286 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2287 labels DIFFPIN port
2288
2289 layer pdiff pdiffarea
2290
2291 layer mvndiode DIFF
2292 and NPLUS
2293 and DIODE
2294 and THKOX
2295 and-not POLY
2296 and-not PPLUS
2297 and-not LVTN
2298 labels DIFF
2299
2300 layer nndiode DIFF
2301 and NPLUS
2302 and DIODE
2303 and THKOX
2304 and-not POLY
2305 and-not PPLUS
2306 and LVTN
2307 labels DIFF
2308
2309 templayer mvndiodearea DIODE
2310 and NPLUS
2311 and THKOX
2312 and-not NWELL
2313 copyup DIODE,NPLUS
2314
2315 layer mvndiffres DIFFRES
2316 and NPLUS
2317 and THKOX
2318 labels DIFF
2319
2320 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2321 and-not POLY
2322 and NWELL
2323 and-not NPLUS
2324 and THKOX
2325 and-not DIODE
2326 and-not DIFFRES
2327 and PPLUS
2328 copyup mvpdifcheck
2329 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2330 variants (vendor)
2331 labels DIFFTXT port
2332 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2333 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2334 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2335 labels DIFFPIN port
2336
2337 layer mvpdiff mvpdiffarea
2338
2339 # Copy pdiff areas up for contact checks
2340 templayer xpdifcheck pdifcheck
2341 copyup pdifcheck
2342
2343 layer pdiode DIFF
2344 and PPLUS
2345 and-not POLY
2346 and-not NPLUS
2347 and-not THKOX
2348 and-not LVTN
2349 and-not HVTP
2350 and DIODE
2351 labels DIFF
2352
2353 layer pdiodelvt DIFF
2354 and PPLUS
2355 and-not POLY
2356 and-not NPLUS
2357 and-not THKOX
2358 and LVTN
2359 and-not HVTP
2360 and DIODE
2361 labels DIFF
2362
2363 layer pdiodehvt DIFF
2364 and PPLUS
2365 and-not POLY
2366 and-not NPLUS
2367 and-not THKOX
2368 and-not LVTN
2369 and HVTP
2370 and DIODE
2371 labels DIFF
2372
2373 templayer pdiodearea DIODE
2374 and PPLUS
2375 and-not THKOX
2376 copyup DIODE,PPLUS
2377
2378 # Define pfet areas as known pdiff, regardless of the presence of a well.
2379
2380 templayer pfetarea DIFF
2381 and-not NPLUS
2382 and-not THKOX
2383 and POLY
2384
2385 layer pfet pfetarea
2386 and-not LVTN
2387 and-not HVTP
2388 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2389 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2390 labels DIFF
2391
2392 layer scpfet pfetarea
2393 and-not LVTN
2394 and-not HVTP
2395 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2396 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2397 labels DIFF
2398
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2399 layer scpfethvt pfetarea
2400 and-not LVTN
2401 and HVTP
2402 and STDCELL
2403 labels DIFF
2404
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2405 layer ppu pfetarea
2406 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2407 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2408 and COREID
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2409 # Shrink-grow operation eliminates the smaller ppass device
2410 shrink 70
2411 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2412 labels DIFF
2413
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2414 layer pfetlvt pfetarea
2415 and LVTN
2416 labels DIFF
2417
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2418 layer pfetmvt pfetarea
2419 and HVTR
2420 labels DIFF
2421
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2422 layer pfethvt pfetarea
2423 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2424 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2425 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2426 labels DIFF
2427
2428 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2429 layer nwell pfetarea
2430 grow 180
2431
2432 # Copy mvpdiff areas up for contact checks
2433 templayer mvxpdifcheck mvpdifcheck
2434 copyup mvpdifcheck
2435
2436 layer mvpdiode DIFF
2437 and PPLUS
2438 and-not POLY
2439 and-not NPLUS
2440 and THKOX
2441 and DIODE
2442 labels DIFF
2443
2444 templayer mvpdiodearea DIODE
2445 and PPLUS
2446 and THKOX
2447 copyup DIODE,PPLUS
2448
2449 # Define pfet areas as known pdiff,
2450 # regardless of the presence of a
2451 # well.
2452
2453 templayer mvpfetarea DIFF
2454 and-not NPLUS
2455 and THKOX
2456 and POLY
2457
2458 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2459 and-not ESDID
2460 labels DIFF
2461
2462 layer mvpfetesd mvpfetarea
2463 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2464 labels DIFF
2465
2466 layer pdiff DIFF,DIFFTXT,DIFFPIN
2467 and-not NPLUS
2468 and-not POLY
2469 and-not THKOX
2470 and-not DIODE
2471 and-not DIFFRES
2472 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2473 variants (vendor)
2474 labels DIFFTXT port
2475 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2476 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2477 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2478 labels DIFFPIN port
2479
2480 layer pdiffres DIFFRES
2481 and PPLUS
2482 and NWELL
2483 and-not THKOX
2484 labels DIFF
2485
2486 layer nfet DIFF
2487 and POLY
2488 and-not PPLUS
2489 and NPLUS
2490 and-not THKOX
2491 and-not LVTN
2492 and-not SONOS
2493 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2494 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2495 labels DIFF
2496
2497 layer scnfet DIFF
2498 and POLY
2499 and-not PPLUS
2500 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2501 and-not NWELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2502 and-not THKOX
2503 and-not LVTN
2504 and-not SONOS
2505 and STDCELL
2506 labels DIFF
2507
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2508 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2509 and POLY
2510 and-not PPLUS
2511 and NPLUS
2512 and-not NWELL
2513 and COREID
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2514 # Shrink-grow operation eliminates the smaller npass device
2515 shrink 70
2516 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2517 labels DIFF
2518
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2519 layer npd DIFF
2520 and POLY
2521 and-not PPLUS
2522 and NPLUS
2523 and-not NWELL
2524 and COREID
2525 # Shrink-grow operation eliminates the smaller npass device
2526 shrink 70
2527 grow 70
2528 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2529
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2530 layer nfetlvt DIFF
2531 and POLY
2532 and-not PPLUS
2533 and NPLUS
2534 and-not THKOX
2535 and LVTN
2536 and-not SONOS
2537 labels DIFF
2538
2539 layer nsonos DIFF
2540 and POLY
2541 and-not PPLUS
2542 and NPLUS
2543 and-not THKOX
2544 and LVTN
2545 and SONOS
2546 labels DIFF
2547
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2548 templayer nsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2549 and NPLUS
2550 and NWELL
2551 and-not POLY
2552 and-not PPLUS
2553 and-not THKOX
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2554 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2555 copyup nsubcheck
2556
2557 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2558 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2559
2560 layer nsd TAP,TAPPIN
2561 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2562 and-not POLY
2563 and-not THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2564 labels TAP
2565 labels TAPPIN port
2566
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2567 layer corenvar TAP
2568 and NPLUS
2569 and POLY
2570 and COREID
2571 labels TAP
2572
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2573 templayer nsdexpand nsdarea
2574 grow 500
2575
2576 # Copy nsub areas up for contact checks
2577 templayer xnsubcheck nsubcheck
2578 copyup nsubcheck
2579
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2580 templayer psdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2581 and PPLUS
2582 and-not NWELL
2583 and-not POLY
2584 and-not NPLUS
2585 and-not THKOX
2586 and-not pfetexpand
2587 copyup psubcheck
2588
2589 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2590 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2591
2592 layer psd TAP,TAPPIN
2593 and PPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2594 and-not POLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2595 and-not THKOX
2596 labels TAP
2597 labels TAPPIN port
2598
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2599 layer corepvar TAP
2600 and PPLUS
2601 and POLY
2602 and COREID
2603 labels TAP
2604
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2605 templayer psdexpand psdarea
2606 grow 500
2607
2608 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
2609 and-not NPLUS
2610 and-not POLY
2611 and THKOX
2612 and mvpfetexpand
2613 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2614 variants (vendor)
2615 labels DIFFTXT port
2616 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2617 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2618 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2619 labels DIFFPIN port
2620
2621 layer mvpdiffres DIFFRES
2622 and PPLUS
2623 and NWELL
2624 and THKOX
2625 and-not mvrdpioedge
2626 labels DIFF
2627
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2628 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2629 and POLY
2630 and-not PPLUS
2631 and NPLUS
2632 and-not LVTN
2633 and THKOX
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2634 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2635
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2636 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2637 and POLY
2638 and-not PPLUS
2639 and NPLUS
2640 and LVTN
2641 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2642 and-not mvnfetarea
2643
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2644 layer mvnfetesd DIFF
2645 and POLY
2646 and-not PPLUS
2647 and NPLUS
2648 and THKOX
2649 and ESDID
2650 and-not mvnnfetarea
2651 labels DIFF
2652
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2653 layer mvnfet DIFF
2654 and POLY
2655 and-not PPLUS
2656 and NPLUS
2657 and THKOX
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2658 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2659 and-not mvnnfetarea
2660 labels DIFF
2661
2662 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2663 labels DIFF
2664
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2665 templayer mvnsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2666 and NPLUS
2667 and NWELL
2668 and-not POLY
2669 and-not PPLUS
2670 and THKOX
2671 copyup mvnsubcheck
2672
2673 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2674 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2675
2676 layer mvnsd TAP,TAPPIN
2677 and NPLUS
2678 and THKOX
2679 labels TAP
2680 labels TAPPIN port
2681
2682 templayer mvnsdexpand mvnsdarea
2683 grow 500
2684
2685 # Copy nsub areas up for contact checks
2686 templayer mvxnsubcheck mvnsubcheck
2687 copyup mvnsubcheck
2688
2689 templayer mvpsdarea DIFF
2690 and PPLUS
2691 and-not NWELL
2692 and-not POLY
2693 and-not NPLUS
2694 and THKOX
2695 and-not mvpfetexpand
2696 copyup mvpsubcheck
2697
2698 layer mvpsd mvpsdarea
2699 labels DIFF
2700
2701 layer mvpsd TAP,TAPPIN
2702 and PPLUS
2703 and THKOX
2704 labels TAP
2705 labels TAPPIN port
2706
2707 templayer mvpsdexpand mvpsdarea
2708 grow 500
2709
2710 # Copy psub areas up for contact checks
2711 templayer xpsubcheck psubcheck
2712 copyup psubcheck
2713
2714 templayer mvxpsubcheck mvpsubcheck
2715 copyup mvpsubcheck
2716
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2717 layer psd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2718 and-not PPLUS
2719 and-not NPLUS
2720 and-not POLY
2721 and-not THKOX
2722 and-not pfetexpand
2723 and psdexpand
2724
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2725 layer nsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2726 and-not PPLUS
2727 and-not NPLUS
2728 and-not POLY
2729 and-not THKOX
2730 and nsdexpand
2731
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2732 layer mvpsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2733 and-not PPLUS
2734 and-not NPLUS
2735 and-not POLY
2736 and THKOX
2737 and-not mvpfetexpand
2738 and mvpsdexpand
2739
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2740 layer mvnsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2741 and-not PPLUS
2742 and-not NPLUS
2743 and-not POLY
2744 and THKOX
2745 and mvnsdexpand
2746
2747 templayer hresarea POLY
2748 and RPM
2749 grow 3000
2750
2751 templayer uresarea POLY
2752 and URPM
2753 grow 3000
2754
2755 templayer diffresarea DIFFRES
2756 and-not THKOX
2757 grow 3000
2758
2759 templayer mvdiffresarea DIFFRES
2760 and THKOX
2761 grow 3000
2762
2763 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2764
2765 layer pfet POLY
2766 and DIFF
2767 and diffresarea
2768 and-not NPLUS
2769 and-not STDCELL
2770
2771 layer scpfet POLY
2772 and DIFF
2773 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2774 and-not HVTP
2775 and-not NPLUS
2776 and STDCELL
2777
2778 layer scpfethvt POLY
2779 and DIFF
2780 and diffresarea
2781 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2782 and-not NPLUS
2783 and STDCELL
2784
2785 templayer xpolyterm RPM,URPM
2786 and POLY
2787 and-not POLYRES
2788 # add back the 0.06um contact surround in the direction of the resistor
2789 grow 60
2790 and POLY
2791
2792 layer xpc xpolyterm
2793
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2794 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2795 and-not POLYRES
2796 and-not POLYSHORT
2797 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2798 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2799 and-not RPM
2800 and-not URPM
2801 copyup polycheck
2802
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2803 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2804 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2805 variants (vendor)
2806 labels POLYTXT port
2807 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2809 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2810 labels POLYPIN port
2811
2812 # Copy (non-resistor) poly areas up for contact checks
2813 templayer xpolycheck polycheck
2814 copyup polycheck
2815
2816 layer mrp1 POLY
2817 and POLYRES
2818 and-not RPM
2819 and-not URPM
2820 labels POLY
2821
2822 layer rmp POLY
2823 and POLYSHORT
2824 labels POLY
2825
2826 layer xhrpoly POLY
2827 and POLYRES
2828 and RPM
2829 and-not URPM
2830 and PPLUS
2831 and NPC
2832 and-not xpolyterm
2833 labels POLY
2834
2835 layer uhrpoly POLY
2836 and POLYRES
2837 and URPM
2838 and-not RPM
2839 and NPC
2840 and-not xpolyterm
2841 labels POLY
2842
2843 templayer ndcbase CONT
2844 and DIFF
2845 and NPLUS
2846 and-not NWELL
2847 and LI
2848 and-not THKOX
2849
2850 layer ndc ndcbase
2851 grow 85
2852 shrink 85
2853 shrink 85
2854 grow 85
2855 or ndcbase
2856 labels CONT
2857
2858 templayer nscbase CONT
2859 and DIFF,TAP
2860 and NPLUS
2861 and NWELL
2862 and LI
2863 and-not THKOX
2864
2865 layer nsc nscbase
2866 grow 85
2867 shrink 85
2868 shrink 85
2869 grow 85
2870 or nscbase
2871 labels CONT
2872
2873 templayer pdcbase CONT
2874 and DIFF
2875 and PPLUS
2876 and NWELL
2877 and LI
2878 and-not THKOX
2879
2880 layer pdc pdcbase
2881 grow 85
2882 shrink 85
2883 shrink 85
2884 grow 85
2885 or pdcbase
2886 labels CONT
2887
2888 templayer pdcnowell CONT
2889 and DIFF
2890 and PPLUS
2891 and pfetexpand
2892 and LI
2893 and-not THKOX
2894
2895 layer pdc pdcnowell
2896 grow 85
2897 shrink 85
2898 shrink 85
2899 grow 85
2900 or pdcnowell
2901 labels CONT
2902
2903 templayer pscbase CONT
2904 and DIFF,TAP
2905 and PPLUS
2906 and-not NWELL
2907 and-not pfetexpand
2908 and LI
2909 and-not THKOX
2910
2911 layer psc pscbase
2912 grow 85
2913 shrink 85
2914 shrink 85
2915 grow 85
2916 or pscbase
2917 labels CONT
2918
2919 templayer pcbase CONT
2920 and POLY
2921 and-not DIFF
2922 and-not RPM,URPM
2923 and LI
2924
2925 layer pc pcbase
2926 grow 85
2927 shrink 85
2928 shrink 85
2929 grow 85
2930 or pcbase
2931 labels CONT
2932
2933 templayer ndicbase CONT
2934 and DIFF
2935 and NPLUS
2936 and DIODE
2937 and-not POLY
2938 and-not PPLUS
2939 and-not THKOX
2940 and-not LVTN
2941
2942 layer ndic ndicbase
2943 grow 85
2944 shrink 85
2945 shrink 85
2946 grow 85
2947 or ndicbase
2948 labels CONT
2949
2950 templayer ndilvtcbase CONT
2951 and DIFF
2952 and NPLUS
2953 and DIODE
2954 and-not POLY
2955 and-not PPLUS
2956 and-not THKOX
2957 and LVTN
2958
2959 layer ndilvtc ndilvtcbase
2960 grow 85
2961 shrink 85
2962 shrink 85
2963 grow 85
2964 or ndilvtcbase
2965 labels CONT
2966
2967 templayer pdicbase CONT
2968 and DIFF
2969 and PPLUS
2970 and DIODE
2971 and-not POLY
2972 and-not NPLUS
2973 and-not THKOX
2974 and-not LVTN
2975 and-not HVTP
2976
2977 layer pdic pdicbase
2978 grow 85
2979 shrink 85
2980 shrink 85
2981 grow 85
2982 or pdicbase
2983 labels CONT
2984
2985 templayer pdilvtcbase CONT
2986 and DIFF
2987 and PPLUS
2988 and DIODE
2989 and-not POLY
2990 and-not NPLUS
2991 and-not THKOX
2992 and LVTN
2993 and-not HVTP
2994
2995 layer pdilvtc pdilvtcbase
2996 grow 85
2997 shrink 85
2998 shrink 85
2999 grow 85
3000 or pdilvtcbase
3001 labels CONT
3002
3003 templayer pdihvtcbase CONT
3004 and DIFF
3005 and PPLUS
3006 and DIODE
3007 and-not POLY
3008 and-not NPLUS
3009 and-not THKOX
3010 and-not LVTN
3011 and HVTP
3012
3013 layer pdihvtc pdihvtcbase
3014 grow 85
3015 shrink 85
3016 shrink 85
3017 grow 85
3018 or pdihvtcbase
3019 labels CONT
3020
3021 templayer mvndcbase CONT
3022 and DIFF
3023 and NPLUS
3024 and-not NWELL
3025 and LI
3026 and THKOX
3027
3028 layer mvndc mvndcbase
3029 grow 85
3030 shrink 85
3031 shrink 85
3032 grow 85
3033 or mvndcbase
3034 labels CONT
3035
3036 templayer mvnscbase CONT
3037 and DIFF,TAP
3038 and NPLUS
3039 and NWELL
3040 and LI
3041 and THKOX
3042
3043 layer mvnsc mvnscbase
3044 grow 85
3045 shrink 85
3046 shrink 85
3047 grow 85
3048 or mvnscbase
3049 labels CONT
3050
3051 templayer mvpdcbase CONT
3052 and DIFF
3053 and PPLUS
3054 and NWELL
3055 and LI
3056 and THKOX
3057
3058 layer mvpdc mvpdcbase
3059 grow 85
3060 shrink 85
3061 shrink 85
3062 grow 85
3063 or mvpdcbase
3064 labels CONT
3065
3066 templayer mvpdcnowell CONT
3067 and DIFF
3068 and PPLUS
3069 and mvpfetexpand
3070 and MET1
3071 and THKOX
3072
3073 layer mvpdc mvpdcnowell
3074 grow 85
3075 shrink 85
3076 shrink 85
3077 grow 85
3078 or mvpdcnowell
3079 labels CONT
3080
3081 templayer mvpscbase CONT
3082 and DIFF,TAP
3083 and PPLUS
3084 and-not NWELL
3085 and-not mvpfetexpand
3086 and LI
3087 and THKOX
3088
3089 layer mvpsc mvpscbase
3090 grow 85
3091 shrink 85
3092 shrink 85
3093 grow 85
3094 or mvpscbase
3095 labels CONT
3096
3097 templayer mvndicbase CONT
3098 and DIFF
3099 and NPLUS
3100 and DIODE
3101 and-not POLY
3102 and-not PPLUS
3103 and-not LVTN
3104 and THKOX
3105
3106 layer mvndic mvndicbase
3107 grow 85
3108 shrink 85
3109 shrink 85
3110 grow 85
3111 or mvndicbase
3112 labels CONT
3113
3114 templayer nndicbase CONT
3115 and DIFF
3116 and NPLUS
3117 and DIODE
3118 and-not POLY
3119 and-not PPLUS
3120 and LVTN
3121 and THKOX
3122
3123 layer nndic nndicbase
3124 grow 85
3125 shrink 85
3126 shrink 85
3127 grow 85
3128 or nndicbase
3129 labels CONT
3130
3131 templayer mvpdicbase CONT
3132 and DIFF
3133 and PPLUS
3134 and DIODE
3135 and-not POLY
3136 and-not NPLUS
3137 and THKOX
3138
3139 layer mvpdic mvpdicbase
3140 grow 85
3141 shrink 85
3142 shrink 85
3143 grow 85
3144 or mvpdicbase
3145 labels CONT
3146
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3147 layer fomfill FOMFILL
3148 labels FOMFILL
3149
3150 layer polyfill POLYFILL
3151 labels POLYFILL
3152
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3153 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3154 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3155 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3156 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3157 variants (vendor)
3158 labels LITXT port
3159 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3160 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3161 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3162 labels LIPIN port
3163
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3164 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3165 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3166 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3167 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3168 variants (vendor)
3169 labels LITXT port
3170 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3171 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3172 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3173 labels LIPIN port
3174
3175 layer rli LI
3176 and LIRES,LISHORT
3177 labels LIRES,LISHORT
3178
3179 layer lic MCON
3180 grow 95
3181 shrink 95
3182 shrink 85
3183 grow 85
3184 or MCON
3185 labels MCON
3186
3187 layer m1 MET1,MET1TXT,MET1PIN
3188 and-not MET1RES,MET1SHORT
3189 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3190 variants (vendor)
3191 labels MET1TXT port
3192 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3193 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3194 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3195 labels MET1PIN port
3196
3197 layer rm1 MET1
3198 and MET1RES,MET1SHORT
3199 labels MET1RES,MET1SHORT
3200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3201 layer m1fill MET1FILL
3202 labels MET1FILL
3203
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3204#ifdef MIM
3205 layer mimcap MET3
3206 and CAPM
3207 labels CAPM
3208
3209 layer mimcc VIA3
3210 and CAPM
3211 grow 60
3212 grow 40
3213 shrink 40
3214 labels CAPM
3215
3216 layer mimcap2 MET4
3217 and CAPM2
3218 labels CAPM2
3219
3220 layer mim2cc VIA4
3221 and CAPM2
3222 grow 190
3223 grow 210
3224 shrink 210
3225 labels CAPM2
3226
3227#endif (MIM)
3228
3229 templayer m2cbase VIA1
3230 grow 55
3231
3232 layer m2c m2cbase
3233 grow 30
3234 shrink 30
3235 shrink 130
3236 grow 130
3237 or m2cbase
3238
3239 layer m2 MET2,MET2TXT,MET2PIN
3240 and-not MET2RES,MET2SHORT
3241 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3242 variants (vendor)
3243 labels MET2TXT port
3244 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3245 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3246 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3247 labels MET2PIN port
3248
3249 layer rm2 MET2
3250 and MET2RES,MET2SHORT
3251 labels MET2RES,MET2SHORT
3252
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3253 layer m2fill MET2FILL
3254 labels MET2FILL
3255
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3256 templayer m3cbase VIA2
3257 grow 40
3258
3259 layer m3c m3cbase
3260 grow 60
3261 shrink 60
3262 shrink 140
3263 grow 140
3264 or m3cbase
3265
3266 layer m3 MET3,MET3TXT,MET3PIN
3267 and-not MET3RES,MET3SHORT
3268#ifdef MIM
3269 and-not CAPM
3270#endif (MIM)
3271 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3272 variants (vendor)
3273 labels MET3TXT port
3274 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3275 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3276 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3277 labels MET3PIN port
3278
3279 layer rm3 MET3
3280 and MET3RES,MET3SHORT
3281 labels MET3RES,MET3SHORT
3282
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3283 layer m3fill MET3FILL
3284 labels MET3FILL
3285
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3286#ifdef (METAL5)
3287
3288 templayer via3base VIA3
3289#ifdef MIM
3290 and-not CAPM
3291#endif (MIM)
3292 grow 60
3293
3294 layer via3 via3base
3295 grow 40
3296 shrink 40
3297 shrink 160
3298 grow 160
3299 or via3base
3300
3301 layer m4 MET4,MET4TXT,MET4PIN
3302 and-not MET4RES,MET4SHORT
3303#ifdef MIM
3304 and-not CAPM2
3305#endif (MIM)
3306 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3307 variants (vendor)
3308 labels MET4TXT port
3309 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3310 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3311 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3312 labels MET4PIN port
3313
3314 layer rm4 MET4
3315 and MET4RES,MET4SHORT
3316 labels MET4RES,MET4SHORT
3317
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3318 layer m4fill MET4FILL
3319 labels MET4FILL
3320
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3321 layer m5 MET5,MET5TXT,MET5PIN
3322 and-not MET5RES,MET5SHORT
3323 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3324 variants (vendor)
3325 labels MET5TXT port
3326 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3327 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3328 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3329 labels MET5PIN port
3330
3331 layer rm5 MET5
3332 and MET5RES,MET5SHORT
3333 labels MET5RES,MET5SHORT
3334
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3335 layer m5fill MET5FILL
3336 labels MET5FILL
3337
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3338 templayer via4base VIA4
3339#ifdef MIM
3340 and-not CAPM2
3341#endif (MIM)
3342 grow 190
3343
3344 layer via4 via4base
3345 grow 210
3346 shrink 210
3347 shrink 590
3348 grow 590
3349 or via4base
3350#endif (METAL5)
3351
3352#ifdef REDISTRIBUTION
3353 layer metrdl RDL,RDLTXT,RDLPIN
3354 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3355 variants (vendor)
3356 labels RDLTXT port
3357 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3358 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3359 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3360 labels RDLPIN port
3361#endif
3362
3363 # Find diffusion not covered in
3364 # NPLUS or PPLUS and pull it into
3365 # the next layer up
3366
3367 templayer gentrans DIFF
3368 and-not PPLUS
3369 and-not NPLUS
3370 and POLY
3371 copyup DIFF,POLY
3372
3373 templayer gendiff DIFF,TAP
3374 and-not PPLUS
3375 and-not NPLUS
3376 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3377 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3378 copyup DIFF
3379
3380 # Handle contacts found by copyup
3381
3382 templayer ndiccopy CONT
3383 and LI
3384 and DIODE
3385 and NPLUS
3386 and-not THKOX
3387
3388 layer ndic ndiccopy
3389 grow 85
3390 shrink 85
3391 shrink 85
3392 grow 85
3393 or ndiccopy
3394 labels CONT
3395
3396 templayer mvndiccopy CONT
3397 and LI
3398 and DIODE
3399 and NPLUS
3400 and THKOX
3401
3402 layer mvndic mvndiccopy
3403 grow 85
3404 shrink 85
3405 shrink 85
3406 grow 85
3407 or mvndiccopy
3408 labels CONT
3409
3410 templayer pdiccopy CONT
3411 and LI
3412 and DIODE
3413 and PPLUS
3414 and-not THKOX
3415
3416 layer pdic pdiccopy
3417 grow 85
3418 shrink 85
3419 shrink 85
3420 grow 85
3421 or pdiccopy
3422 labels CONT
3423
3424 templayer mvpdiccopy CONT
3425 and LI
3426 and DIODE
3427 and PPLUS
3428 and THKOX
3429
3430 layer mvpdic mvpdiccopy
3431 grow 85
3432 shrink 85
3433 shrink 85
3434 grow 85
3435 or mvpdiccopy
3436 labels CONT
3437
3438 templayer ndccopy CONT
3439 and ndifcheck
3440
3441 layer ndc ndccopy
3442 grow 85
3443 shrink 85
3444 shrink 85
3445 grow 85
3446 or ndccopy
3447 labels CONT
3448
3449 templayer mvndccopy CONT
3450 and mvndifcheck
3451
3452 layer mvndc mvndccopy
3453 grow 85
3454 shrink 85
3455 shrink 85
3456 grow 85
3457 or mvndccopy
3458 labels CONT
3459
3460 templayer pdccopy CONT
3461 and pdifcheck
3462
3463 layer pdc pdccopy
3464 grow 85
3465 shrink 85
3466 shrink 85
3467 grow 85
3468 or pdccopy
3469 labels CONT
3470
3471 templayer mvpdccopy CONT
3472 and mvpdifcheck
3473
3474 layer mvpdc mvpdccopy
3475 grow 85
3476 shrink 85
3477 shrink 85
3478 grow 85
3479 or mvpdccopy
3480 labels CONT
3481
3482 templayer pccopy CONT
3483 and polycheck
3484
3485 layer pc pccopy
3486 grow 85
3487 shrink 85
3488 shrink 85
3489 grow 85
3490 or pccopy
3491 labels CONT
3492
3493 templayer nsccopy CONT
3494 and nsubcheck
3495
3496 layer nsc nsccopy
3497 grow 85
3498 shrink 85
3499 shrink 85
3500 grow 85
3501 or nsccopy
3502 labels CONT
3503
3504 templayer mvnsccopy CONT
3505 and mvnsubcheck
3506
3507 layer mvnsc mvnsccopy
3508 grow 85
3509 shrink 85
3510 shrink 85
3511 grow 85
3512 or mvnsccopy
3513 labels CONT
3514
3515 templayer psccopy CONT
3516 and psubcheck
3517
3518 layer psc psccopy
3519 grow 85
3520 shrink 85
3521 shrink 85
3522 grow 85
3523 or psccopy
3524 labels CONT
3525
3526 templayer mvpsccopy CONT
3527 and mvpsubcheck
3528
3529 layer mvpsc mvpsccopy
3530 grow 85
3531 shrink 85
3532 shrink 85
3533 grow 85
3534 or mvpsccopy
3535 labels CONT
3536
3537 # Find contacts not covered in
3538 # metal and pull them into the
3539 # next layer up
3540
3541 templayer gencont CONT
3542 and LI
3543 and-not DIFF,TAP
3544 and-not POLY
3545 and-not DIODE
3546 and-not nsubcheck
3547 and-not psubcheck
3548 and-not mvnsubcheck
3549 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3550 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3551 copyup CONT,LI
3552
3553 templayer barecont CONT
3554 and-not LI
3555 and-not nsubcheck
3556 and-not psubcheck
3557 and-not mvnsubcheck
3558 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3559 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3560 copyup CONT
3561
3562 layer glass GLASS,PADTXT,PADPIN
3563 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3564 variants (vendor)
3565 labels PADTXT port
3566 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3567 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3568 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3569 labels PADPIN port
3570
3571 templayer boundary BOUND,STDCELL,PADCELL
3572 boundary
3573
3574 layer comment LVSTEXT
3575 labels LVSTEXT text
3576
3577 layer comment TTEXT
3578 labels TTEXT text
3579
3580 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3581 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3582
3583# MOS Varactor
3584
3585 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3586 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3587 and NPLUS
3588 and NWELL
3589 and-not THKOX
3590 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3591 # NOTE: Else forms a varactor that is not in the vendor netlist.
3592 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3593 labels POLY
3594
3595 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3596 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3597 and NPLUS
3598 and NWELL
3599 and-not THKOX
3600 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3601 labels POLY
3602
3603 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3604 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3605 and NPLUS
3606 and NWELL
3607 and THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3608 labels POLY
3609
3610 calma NWELL 64 20
3611 calma DIFF 65 20
3612 calma DNWELL 64 18
3613 calma PWRES 64 13
3614 calma TAP 65 44
3615 # LVTN
3616 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3617 # HVTR
3618 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3619 # HVTP
3620 calma HVTP 78 44
3621 # SONOS (TUNM)
3622 calma SONOS 80 20
3623 # NPLUS = NSDM
3624 calma NPLUS 93 44
3625 # PPLUS = PSDM
3626 calma PPLUS 94 20
3627 # HVI
3628 calma THKOX 75 20
3629 # NPC
3630 calma NPC 95 20
3631 # P+ POLY MASK
3632 calma RPM 86 20
3633 calma URPM 79 20
3634 calma LDNTM 11 44
3635 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3636 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3637 calma POLYRES 66 13
3638 # Diffusion resistor ID mark
3639 calma DIFFRES 65 13
3640 calma POLY 66 20
3641 calma POLYMOD 66 83
3642 # Diode ID mark
3643 calma DIODE 81 23
3644 # Bipolar NPN mark
3645 calma NPNID 82 20
3646 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3647 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3648 # Capacitor ID
3649 calma CAPID 82 64
3650 # Core area ID mark
3651 calma COREID 81 2
3652 # Standard cell ID mark
3653 calma STDCELL 81 4
3654 # Padframe cell ID mark
3655 calma PADCELL 81 3
3656 # Seal ring ID mark
3657 calma SEALID 81 1
3658 # Low tap density ID mark
3659 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3660 # ESD area ID
3661 calma ESDID 81 19
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3662
3663 # LICON
3664 calma CONT 66 44
3665 calma LI 67 20
3666 calma MCON 67 44
3667
3668 calma MET1 68 20
3669 calma VIA1 68 44
3670 calma MET2 69 20
3671 calma VIA2 69 44
3672 calma MET3 70 20
3673#ifdef METAL5
3674 calma VIA3 70 44
3675 calma MET4 71 20
3676 calma VIA4 71 44
3677 calma MET5 72 20
3678#endif
3679#ifdef REDISTRIBUTION
3680 calma RDL 74 20
3681#endif
3682 calma GLASS 76 20
3683
3684 calma SUBPIN 64 59
3685 calma PADPIN 76 5
3686 calma DIFFPIN 65 6
3687 calma TAPPIN 65 5
3688 calma WELLPIN 64 5
3689 calma LIPIN 67 5
3690 calma POLYPIN 66 5
3691 calma MET1PIN 68 5
3692 calma MET2PIN 69 5
3693 calma MET3PIN 70 5
3694#ifdef METAL5
3695 calma MET4PIN 71 5
3696 calma MET5PIN 72 5
3697#endif
3698#ifdef REDISTRIBUTION
3699 calma RDLPIN 74 5
3700#endif
3701
3702 calma LIRES 67 13
3703 calma MET1RES 68 13
3704 calma MET2RES 69 13
3705 calma MET3RES 70 13
3706#ifdef METAL5
3707 calma MET4RES 71 13
3708 calma MET5RES 72 13
3709#endif
3710
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3711 calma MET1FILL 68 28
3712 calma MET2FILL 69 28
3713 calma MET3FILL 70 28
3714#ifdef METAL5
3715 calma MET4FILL 71 28
3716 calma MET5FILL 72 28
3717#endif
3718
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3719 calma POLYSHORT 66 15
3720 calma LISHORT 67 15
3721 calma MET1SHORT 68 15
3722 calma MET2SHORT 69 15
3723 calma MET3SHORT 70 15
3724#ifdef METAL5
3725 calma MET4SHORT 71 15
3726 calma MET5SHORT 72 15
3727#endif
3728
3729 calma SUBTXT 122 16
3730 calma PADTXT 76 16
3731 calma DIFFTXT 65 16
3732 calma POLYTXT 66 16
3733 calma WELLTXT 64 16
3734 calma LITXT 67 16
3735 calma MET1TXT 68 16
3736 calma MET2TXT 69 16
3737 calma MET3TXT 70 16
3738#ifdef METAL5
3739 calma MET4TXT 71 16
3740 calma MET5TXT 72 16
3741#endif
3742#ifdef REDISTRIBUTION
3743 calma RDLPIN 74 16
3744#endif
3745
3746 calma BOUND 235 4
3747
3748 calma LVSTEXT 83 44
3749
3750#ifdef (MIM)
3751 calma CAPM 89 44
3752 calma CAPM2 97 44
3753#endif (MIM)
3754
3755 calma FILLOBSM1 62 24
3756 calma FILLOBSM2 105 52
3757 calma FILLOBSM3 107 24
3758 calma FILLOBSM4 112 4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3759 calma FOMFILL 65 28
3760 calma POLYFILL 66 28
3761 calma MET1FILL 68 28
3762 calma MET2FILL 69 28
3763 calma MET3FILL 70 28
3764 calma MET4FILL 71 28
3765 calma MET5FILL 72 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3766
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3767#-----------------------------------------------------------------------
3768
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3769style rdlimport
3770 # This style is for reading shapes generated with the RDL layers
3771
3772 scalefactor 10 nanometers
3773 gridlimit 5
3774
3775 options ignore-unknown-layer-labels no-reconnect-labels
3776
3777 layer mrdl RDL
3778 layer mrdlc RDLC
3779
3780 calma RDL 10 0
3781 calma RDLC 20 0
3782
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3783end
3784
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3785#-----------------------------------------------------
3786# Digital flow maze router cost parameters
3787#-----------------------------------------------------
3788
3789mzrouter
3790end
3791
3792#-----------------------------------------------------
3793# Vendor DRC rules
3794#-----------------------------------------------------
3795
3796drc
3797
3798 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3799 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3800 cifstyle drc
3801
3802 variants (fast),(full)
3803
3804#-----------------------------
3805# DNWELL
3806#-----------------------------
3807
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3808 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
3809 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3810 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3811 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3812
3813 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3814 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3815 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3816 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3817 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3818
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3819 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
3820 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3821 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3822
3823#-----------------------------
3824# NWELL
3825#-----------------------------
3826
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3827 width allnwell 840 "N-well width < %d (nwell.1)"
3828 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3829
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3830 variants (full)
3831 cifmaxwidth nwell_missing_tap 0 bend_illegal \
3832 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3833
3834 cifspacing mvnwell lvnwell 2000 touching_illegal \
3835 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
3836 cifspacing mvnwell mvnwell 2000 touching_ok \
3837 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3838 variants (fast),(full)
3839
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3840#-----------------------------
3841# DIFF
3842#-----------------------------
3843
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3844 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3845 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3846 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3847 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3848
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3849 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
3850 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
3851 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
3852 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
3853 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
3854 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3855 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3856 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3857 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3858 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3859 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3860 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3861 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3862 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3863 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3864 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3865 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3866 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3867 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3868 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3869 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3870 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3871 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3872 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3873 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3874 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3875 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3876 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3877 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3878 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3879 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3880 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3881 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3882 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3883 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3884 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]3885
3886variants (full)
3887 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
3888 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
3889variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3890
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3891 spacing allnfets allpactivenonfet 270 touching_illegal \
3892 "nFET cannot abut P-diffusion (diff/tap.3)"
3893 spacing allpfets allnactivenonfet 270 touching_illegal \
3894 "pFET cannot abut N-diffusion (diff/tap.3)"
3895
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3896 # Butting junction rules
3897 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3898 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3899 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3900 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3901 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3902 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3903 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3904 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3905
3906 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3907 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3908 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3909 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3910 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3911 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3912 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3913 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
3914
3915 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3916 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
3917 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
3918
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3919 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
3920 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
3921
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3922 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3923
3924 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3925 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3926
3927 # Latchup rules
3928 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3929 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3930 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3931 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3932 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3933 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3934
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3935 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3936
3937#-----------------------------
3938# POLY
3939#-----------------------------
3940
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3941 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
3942 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3943
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3944 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]3945 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3946 75 corner_ok allfets \
3947 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3948 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3949 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3950 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3951 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3952 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3953 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3954 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3955 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
3956 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3957 rect_only allfets "No bends in transistors (poly.11)"
3958 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3959 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3960 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3961 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3962 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3963
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3964 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
3965 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
3966 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
3967 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
3968 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
3969 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
3970
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3971 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3972
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3973#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3974# HVTP
3975#--------------------------------------------------------------------
3976
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3977 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3978 360 touching_illegal \
3979 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
3980
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3981 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3982 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
3983
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3984#--------------------------------------------------------------------
3985# LVTN
3986#--------------------------------------------------------------------
3987
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3988 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
3989 allfetsnolvt 360 touching_illegal \
3990 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3991
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3992 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3993 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3994 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3995
3996 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3997 edge4way allfetsnolvt allactivenonfet 415 \
3998 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
3999 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4000
4001#--------------------------------------------------------------------
4002# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4003#--------------------------------------------------------------------
4004
4005# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4006
4007#--------------------------------------------------------------------
4008# CONT (LICON, contact between poly/diff and LI)
4009#--------------------------------------------------------------------
4010
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4011 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4012 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4013 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4014 width psc/li 170 "P-tap contact width < %d (licon.1)"
4015 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4016 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4017 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4018
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4019 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4020 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4021 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4022
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4023 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4024 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4025 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4026 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4027 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4028 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4029
4030 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4031 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4032 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4033 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4034 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4035 "Diffusion contact spacing < %d (licon.2)"
4036 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4037
4038 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4039 "poly contact spacing to diffusion < %d (licon.14)"
4040 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4041 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4042
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4043 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4044 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4045 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4046 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4047 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4048 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4049 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4050 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4051 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4052 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4053 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4054 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4055
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4056 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4057 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4058 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4059 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4060 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4061 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4062 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4063 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4064 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4065
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4066 spacing psc/a allnactivenontap 60 touching_illegal \
4067 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4068 spacing nsc/a allpactivenontap 60 touching_illegal \
4069 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4070
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4071 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4072 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4073 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4074 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4075 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4076 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4077 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4078 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4079 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4080
4081 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4082 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4083 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4084 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4085
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4086 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4087 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4088 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4089 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4090 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4091 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4092 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4093 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4094
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4095 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4096 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4097 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4098 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4099
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4100 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4101 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4102 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4103 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4104 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4105 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4106 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4107 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4108
4109 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4110 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4111 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4112 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4113
4114 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4115 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4116 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4117 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4118
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4119 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4120
4121#-------------------------------------------------------------
4122# LI - Local interconnect layer
4123#-------------------------------------------------------------
4124
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4125variants *
4126
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4127 width *li 170 "Local interconnect width < %d (li.1)"
4128 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4129
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4130 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4131 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4132
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4133 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4134 # no special layers for the contacts in core cells, so they must be included
4135 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4136 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4137 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4138
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4139 spacing coreli,pc,ndc,nsc,pdc,psc,lic allli,*obsli 140 touching_ok \
4140 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4141
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4142 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4143 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4144
4145 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4146 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4147 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4148
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4149 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4150
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4151 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4152 angles coreli 45 \
4153 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4154
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4155#-------------------------------------------------------------
4156# MCON - Contact between local interconnect and metal1
4157#-------------------------------------------------------------
4158
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4159 width lic/m1 170 "mcon.width < %d (mcon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4160 spacing lic/m1 lic/m1,obslic/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4161
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4162 exact_overlap lic/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4163
4164#-------------------------------------------------------------
4165# METAL1 -
4166#-------------------------------------------------------------
4167
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4168 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4169 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4170 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4171
4172 surround lic/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4173 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4174 surround lic/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4175 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4176
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4177 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4178
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4179variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4180 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4181 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4182 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4183 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4184
4185variants (full)
4186 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4187 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4188
4189 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4190 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4191variants *
4192
4193#--------------------------------------------------
4194# VIA1
4195#--------------------------------------------------
4196
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4197 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4198 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4199 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4200 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4201 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4202 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4203
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4204 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4205
4206#--------------------------------------------------
4207# METAL2 -
4208#--------------------------------------------------
4209
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4210 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4211 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4212 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4213
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4214 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4215
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4216variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4217 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4218 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4219 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4220 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4221
4222variants (full)
4223 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4224 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4225
4226 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4227 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4228variants *
4229
4230#--------------------------------------------------
4231# VIA2
4232#--------------------------------------------------
4233
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4234 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4235
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4236 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4237
4238 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4239 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4240 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4241
4242 exact_overlap v2/m2
4243
4244#--------------------------------------------------
4245# METAL3 -
4246#--------------------------------------------------
4247
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4248 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4249 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4250 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4251
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4252 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4253
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4254variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4255 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4256 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4257 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4258 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4259variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4260 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4261 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4262variants *
4263
4264
4265#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4266#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4267#--------------------------------------------------
4268# VIA3 - Requires METAL5 Module
4269#--------------------------------------------------
4270
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4271 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4272 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4273 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4274 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4275 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4276 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4277
4278 exact_overlap v3/m3
4279
4280#-----------------------------
4281# METAL4 - METAL4 Module
4282#-----------------------------
4283
4284variants *
4285
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4286 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4287 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4288 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4289
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4290 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4291
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4292variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4293 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4294 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4295 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4296 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4297variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4298 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4299 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4300variants *
4301
4302#--------------------------------------------------
4303# VIA4 - Requires METAL5 Module
4304#--------------------------------------------------
4305
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4306 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4307 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4308 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4309 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4310
4311 exact_overlap v4/m4
4312
4313#-----------------------------
4314# METAL5 - METAL5 Module
4315#-----------------------------
4316
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4317 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4318 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4319 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4320
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4321 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4322
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4323#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4324#endif (METAL5)
4325
4326#ifdef REDISTRIBUTION
4327
4328variants (full)
4329
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4330 width metrdl 10000 "RDL width < %d (rdl.1)"
4331 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4332 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4333 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4334
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4335variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4336
4337#endif (REDISTRIBUTION)
4338
4339#--------------------------------------------------
4340# NMOS, PMOS
4341#--------------------------------------------------
4342
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4343 edge4way *poly allfetsstd 420 allfets 0 0 \
4344 "Transistor width < %d (diff/tap.2)"
4345 edge4way *poly allfetsspecial 360 allfets 0 0 \
4346 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4347 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4348 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4349 edge4way *poly ppu 140 allfets 0 0 \
4350 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4351
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4352 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4353 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4354
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4355 spacing allpolynonfet,polyfill *nsd 55 corner_ok varactor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4356 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4357 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvaractor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4358 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4359
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4360 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4361 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4362 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4363 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4364 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4365 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4366 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4367 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4368
4369 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4370 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4371 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4372
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4373 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4374 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4375
4376 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4377 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4378 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4379
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4380 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4381 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4382
4383 # Minimum length of MV FETs. Note that this is larger than the minimum
4384 # width (0.29um), so an edge rule is required
4385
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4386 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4387 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4388
4389 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4390 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4391
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4392 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4393 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4394
4395#--------------------------------------------------
4396# mrp1 (N+ poly resistor)
4397#--------------------------------------------------
4398
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4399 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4400
4401#--------------------------------------------------
4402# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4403# uhrpoly (P+ poly resistor, 2kOhm/sq)
4404#--------------------------------------------------
4405
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4406 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4407 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4408 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4409
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4410 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4411 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4412
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4413 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4414 "Poly resistor spacing to poly < %d (poly.9)"
4415
4416 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4417 "Poly resistor spacing to poly < %d (poly.9)"
4418
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4419 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4420 "Poly resistor spacing to poly < %d (poly.9)"
4421
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4422 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4423 "Poly resistor spacing to diffusion < %d (poly.9)"
4424
4425#------------------------------------
4426# nsonos
4427#------------------------------------
4428
4429variants (full)
4430 cifmaxwidth bbox_missing 0 bend_illegal \
4431 "SONOS transistor must be in cell with abutment box (tunm.8)"
4432variants (fast),(full)
4433
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4434#------------------------------------
4435# MOS Varactor device rules
4436#------------------------------------
4437
4438 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4439 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4440
4441 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4442 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4443
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4444 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4445 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4446
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4447variants (full)
4448 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4449 "N-well overlap of varactor poly < 0.15um (varac.5)"
4450
4451 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4452 "Varactor N-well must not contain P+ diffusion (varac.7)"
4453variants (fast),(full)
4454
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4455#ifdef MIM
4456#-----------------------------------------------------------
4457# MiM CAP (CAPM) -
4458#-----------------------------------------------------------
4459
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4460 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4461 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4462 spacing *mimcap via3/m3 80 touching_illegal \
4463 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4464 surround *mimcc *mimcap 80 absence_illegal \
4465 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4466 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4467
4468 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4469 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4470 spacing via2 *mimcap 100 touching_illegal \
4471 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4472 spacing *mimcap *metal3/m3 500 surround_ok \
4473 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4474
4475variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4476 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4477 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4478variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4479
4480 # MiM cap contact rules (VIA3)
4481
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4482 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4483 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4484 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4485 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4486 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4487
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4488 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4489 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4490 spacing *mimcap2 via4/m4 10 touching_illegal \
4491 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4492 surround *mim2cc *mimcap2 10 absence_illegal \
4493 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4494 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4495
4496 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4497 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4498 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4499 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4500 spacing *mimcap2 *metal4/m4 500 surround_ok \
4501 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4502
4503variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4504 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4505 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4506variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4507
4508 # MiM cap contact rules (VIA4)
4509
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4510 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4511 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4512 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4513 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4514 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4515 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4516
4517#endif (MIM)
4518
4519#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4520# HVNTM
4521#----------------------------
4522variants (full)
4523 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4524 "HVNTM spacing < %d (hvntm.2)"
4525variants (fast),(full)
4526
4527#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4528# End DRC style
4529#----------------------------
4530
4531end
4532
4533#----------------------------
4534# LEF format definitions
4535#----------------------------
4536
4537lef
4538
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4539 masterslice pwell pwell PWELL substrate
4540 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4541
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4542 routing li li1 LI1 LI li
4543
4544 routing m1 met1 MET1 m1
4545 routing m2 met2 MET2 m2
4546 routing m3 met3 MET3 m3
4547#ifdef METAL5
4548 routing m4 met4 MET4 m4
4549 routing m5 met5 MET5 m5
4550#endif (METAL5)
4551#ifdef REDISTRIBUTION
4552 routing mrdl met6 MET6 m6 MRDL METRDL
4553#endif
4554
4555 cut lic mcon MCON Mcon
4556 cut m2c via via1 VIA VIA1 cont2 via12
4557 cut m3c via2 VIA2 cont3 via23
4558#ifdef METAL5
4559 cut via3 via3 VIA3 cont4 via34
4560 cut via4 via4 VIA4 cont5 via45
4561#endif (METAL5)
4562
4563 obs obsli li1
4564 obs obsm1 met1
4565 obs obsm2 met2
4566 obs obsm3 met3
4567
4568#ifdef METAL5
4569 obs obsm4 met4
4570 obs obsm5 met5
4571#endif (METAL5)
4572#ifdef REDISTRIBUTION
4573 obs obsmrdl met6
4574#endif
4575
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]4576 # NOTE: obslic only used with li1, not obsli.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4577 obs obslic mcon
4578
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4579 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4580 obs obsm1 via
4581 obs obsm2 via2
4582#ifdef METAL5
4583 obs obsm3 via3
4584 obs obsm4 via4
4585#endif (METAL5)
4586
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4587end
4588
4589#-----------------------------------------------------
4590# Device and Parasitic extraction
4591#-----------------------------------------------------
4592
4593
4594extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4595 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4596 cscale 1
4597 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4598 # dimensions must be in units of microns in the extract file.
4599 # Use extract style "ngspice(si)" to override this and produce
4600 # a file with SI units for length/area.
4601
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4602 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4603 lambda 1E6
4604 variants (si)
4605 lambda 1.0
4606 variants *
4607
4608 units microns
4609 step 7
4610 sidehalo 2
4611
4612 # NOTE: MiM cap layers have been purposely put out of order,
4613 # may want to reconsider.
4614
4615 planeorder dwell 0
4616 planeorder well 1
4617 planeorder active 2
4618 planeorder locali 3
4619 planeorder metal1 4
4620 planeorder metal2 5
4621 planeorder metal3 6
4622#ifdef METAL5
4623 planeorder metal4 7
4624 planeorder metal5 8
4625#ifdef REDISTRIBUTION
4626 planeorder metali 9
4627 planeorder block 10
4628 planeorder comment 11
4629 planeorder cap1 12
4630 planeorder cap2 13
4631#else (!REDISTRIBUTION)
4632 planeorder block 9
4633 planeorder comment 10
4634 planeorder cap1 11
4635 planeorder cap2 12
4636#endif (!REDISTRIBUTION)
4637#else (!METAL5)
4638#ifdef REDISTRIBUTION
4639 planeorder metali 7
4640 planeorder block 8
4641 planeorder comment 9
4642 planeorder cap1 10
4643 planeorder cap2 11
4644#else (!REDISTRIBUTION)
4645 planeorder block 7
4646 planeorder comment 8
4647 planeorder cap1 9
4648 planeorder cap2 10
4649#endif (!REDISTRIBUTION)
4650#endif (!METAL5)
4651
4652 height dnwell -0.1 0.1
4653 height nwell,pwell 0.0 0.2062
4654 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4655 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4656 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4657 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4658 height alldiffcont 0.3262 0.61
4659 height pc 0.5062 0.43
4660 height allli 0.9361 0.10
4661 height lic 1.0361 0.34
4662 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4663 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4664 height v1 1.7361 0.27
4665 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4666 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4667 height v2 2.3661 0.42
4668 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4669 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4670#ifdef METAL5
4671 height v3 3.6311 0.39
4672 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4673 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4674 height v4 4.8661 0.505
4675 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4676 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4677 height mimcap 2.4661 0.2
4678 height mimcap2 3.7311 0.2
4679 height mimcc 2.6661 0.12
4680 height mim2cc 3.9311 0.09
4681#ifdef REDISTRIBUTION
4682 height mrdlc 6.6311 5.2523
4683 height mrdl 11.8834 4.0
4684#endif (!REDISTRIBUTION)
4685#endif (!METAL5)
4686
4687 # Antenna check parameters
4688 # Note that checks w/diode diffusion are not modeled
4689 model partial
4690 antenna poly sidewall 50 none
4691 antenna allcont surface 3 none
4692 antenna li sidewall 75 0 450
4693 antenna lic surface 3 0 18
4694 antenna m1,m2,m3 sidewall 400 2600 400
4695 antenna v1 surface 3 0 18
4696 antenna v2 surface 6 0 36
4697#ifdef METAL5
4698 antenna m4,m5 sidewall 400 2600 400
4699 antenna v3,v4 surface 6 0 36
4700#endif (METAL5)
4701
4702 tiedown alldiffnonfet
4703
4704 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
4705
4706# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4707
4708# Resistances are in milliohms per square
4709# Optional 3rd argument is the corner adjustment fraction
4710# Device values come from trtc.cor (typical corner)
4711 resist (dnwell)/dwell 2200000
4712 resist (pwell)/well 3050000
4713 resist (nwell)/well 1700000
4714 resist (rpw)/well 3050000 0.5
4715 resist (*ndiff,nsd)/active 120000
4716 resist (*pdiff,*psd)/active 197000
4717 resist (*mvndiff,mvnsd)/active 114000
4718 resist (*mvpdiff,*mvpsd)/active 191000
4719
4720 resist ndiffres/active 120000 0.5
4721 resist pdiffres/active 197000 0.5
4722 resist mvndiffres/active 114000 0.5
4723 resist mvpdiffres/active 191000 0.5
4724 resist mrp1/active 48200 0.5
4725 resist xhrpoly/active 319800 0.5
4726 resist uhrpoly/active 2000000 0.5
4727
4728 resist (allpolynonres)/active 48200
4729 resist rmp/active 48200
4730
4731 resist (allli)/locali 12200
4732 resist (allm1)/metal1 125
4733 resist (allm2)/metal2 125
4734 resist (allm3)/metal3 47
4735#ifdef METAL5
4736 resist (allm4)/metal4 47
4737 resist (allm5)/metal5 29
4738#endif (METAL5)
4739#ifdef REDISTRIBUTION
4740 resist mrdl/metali 5
4741#endif (REDISTRIBUTION)
4742
4743 contact ndc,nsc 15000
4744 contact pdc,psc 15000
4745 contact mvndc,mvnsc 15000
4746 contact mvpdc,mvpsc 15000
4747 contact pc 15000
4748 contact lic 152000
4749 contact m2c 4500
4750 contact m3c 3410
4751#ifdef METAL5
4752#ifdef MIM
4753 contact mimcc 4500
4754 contact mim2cc 3410
4755#endif (MIM)
4756 contact via3 3410
4757 contact via4 380
4758#endif (METAL5)
4759#ifdef REDISTRIBUTION
4760 contact mrdlc 6
4761#endif (REDISTRIBUTION)
4762
4763#-------------------------------------------------------------------------
4764# Parasitic capacitance values: Use document (...)
4765#-------------------------------------------------------------------------
4766# This uses the new "default" definitions that determine the intervening
4767# planes from the planeorder stack, take care of the reflexive sideoverlap
4768# definitions, and generally clean up the section and make it more readable.
4769#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4770# Also uses "units microns" statement. All values are taken from the
4771# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
4772# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4773#-------------------------------------------------------------------------
4774# Remember that device capacitances to substrate are taken care of by the
4775# models. Thus, active and poly definitions ignore all "fet" types.
4776# fet types are excluded when computing parasitic capacitance to
4777# active from layers above them because poly is a shield; fet types are
4778# included for parasitics from layers above to poly. Resistor types
4779# should be removed from all parasitic capacitance calculations, or else
4780# they just create floating caps. Technically, the capacitance probably
4781# should be split between the two terminals. Unsure of the correct model.
4782#-------------------------------------------------------------------------
4783
4784#n-well
4785# NOTE: This value not found in PEX files
4786defaultareacap nwell well 120
4787
4788#n-active
4789# Rely on device models to capture *ndiff area cap
4790# Do not extract parasitics from resistors
4791# defaultareacap allnactivenonfet active 790
4792# defaultperimeter allnactivenonfet active 280
4793
4794#p-active
4795# Rely on device models to capture *pdiff area cap
4796# Do not extract parasitics from resistors
4797# defaultareacap allpactivenonfet active 810
4798# defaultperimeter allpactivenonfet active 300
4799
4800#poly
4801# Do not extract parasitics from resistors
4802# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4803# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4804# defaultperimeter allpolynonfet active 57
4805
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4806 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4807 defaultareacap *poly active nwell,obswell,pwell well 106
4808 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4809
4810#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4811 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4812 defaultareacap allli locali nwell,obswell,pwell well 37
4813 defaultperimeter allli locali nwell,obswell,pwell well 55
4814 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4815
4816#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4817 defaultoverlap allli locali allactivenonfet active 37
4818 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4819
4820#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4821 defaultoverlap allli locali allpolynonres active 94
4822 defaultsideoverlap allli locali allpolynonres active 52
4823 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824
4825#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4826 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4827 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
4828 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4829 defaultoverlap allm1 metal1 nwell well 26
4830
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4831#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4832 defaultoverlap allm1 metal1 allactivenonfet active 26
4833 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4834
4835#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4836 defaultoverlap allm1 metal1 allpolynonres active 45
4837 defaultsideoverlap allm1 metal1 allpolynonres active 47
4838 defaultsideoverlap *poly active allm1 metal1 17
4839
4840#metal1->locali
4841 defaultoverlap allm1 metal1 allli locali 114
4842 defaultsideoverlap allm1 metal1 allli locali 59
4843 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4844
4845#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4846 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4847 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
4848 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
4849 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4850
4851#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4852 defaultoverlap allm2 metal2 allactivenonfet active 17
4853 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4854
4855#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4856 defaultoverlap allm2 metal2 allpolynonres active 24
4857 defaultsideoverlap allm2 metal2 allpolynonres active 41
4858 defaultsideoverlap *poly active allm2 metal2 11
4859
4860#metal2->locali
4861 defaultoverlap allm2 metal2 allli locali 38
4862 defaultsideoverlap allm2 metal2 allli locali 46
4863 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4864
4865#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4866 defaultoverlap allm2 metal2 allm1 metal1 134
4867 defaultsideoverlap allm2 metal2 allm1 metal1 67
4868 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4869
4870#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4871 defaultsidewall allm3 metal3 63
4872 defaultoverlap allm3 metal3 nwell well 12
4873 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
4874 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4875
4876#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4877 defaultoverlap allm3 metal3 allactive active 12
4878 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4879
4880#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4881 defaultoverlap allm3 metal3 allpolynonres active 16
4882 defaultsideoverlap allm3 metal3 allpolynonres active 44
4883 defaultsideoverlap *poly active allm3 metal3 9
4884
4885#metal3->locali
4886 defaultoverlap allm3 metal3 allli locali 21
4887 defaultsideoverlap allm3 metal3 allli locali 47
4888 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4889
4890#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4891 defaultoverlap allm3 metal3 allm1 metal1 35
4892 defaultsideoverlap allm3 metal3 allm1 metal1 55
4893 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4894
4895#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4896 defaultoverlap allm3 metal3 allm2 metal2 86
4897 defaultsideoverlap allm3 metal3 allm2 metal2 70
4898 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4899
4900#ifdef METAL5
4901#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4902 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4903# defaultareacap alltopm metal4 well 6
4904 areacap allm4/m4 8
4905 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4906 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4907
4908#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4909 defaultoverlap allm4 metal4 allactivenonfet active 8
4910 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4911
4912#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4913 defaultoverlap allm4 metal4 allpolynonres active 10
4914 defaultsideoverlap allm4 metal4 allpolynonres active 38
4915 defaultsideoverlap *poly active allm4 metal4 6
4916
4917#metal4->locali
4918 defaultoverlap allm4 metal4 allli locali 12
4919 defaultsideoverlap allm4 metal4 allli locali 40
4920 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4921
4922#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4923 defaultoverlap allm4 metal4 allm1 metal1 15
4924 defaultsideoverlap allm4 metal4 allm1 metal1 43
4925 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4926
4927#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4928 defaultoverlap allm4 metal4 allm2 metal2 20
4929 defaultsideoverlap allm4 metal4 allm2 metal2 46
4930 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4931
4932#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4933 defaultoverlap allm4 metal4 allm3 metal3 84
4934 defaultsideoverlap allm4 metal4 allm3 metal3 71
4935 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4936
4937#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4938 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4939# defaultareacap allm5 metal5 well 6
4940 areacap allm5/m5 6
4941 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4942 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4943
4944#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4945 defaultoverlap allm5 metal5 allactivenonfet active 6
4946 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4947
4948#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4949 defaultoverlap allm5 metal5 allpolynonres active 7
4950 defaultsideoverlap allm5 metal5 allpolynonres active 40
4951 defaultsideoverlap *poly active allm5 metal5 6
4952
4953#metal5->locali
4954 defaultoverlap allm5 metal5 allli locali 8
4955 defaultsideoverlap allm5 metal5 allli locali 41
4956 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4957
4958#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4959 defaultoverlap allm5 metal5 allm1 metal1 9
4960 defaultsideoverlap allm5 metal5 allm1 metal1 43
4961 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4962
4963#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4964 defaultoverlap allm5 metal5 allm2 metal2 11
4965 defaultsideoverlap allm5 metal5 allm2 metal2 46
4966 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4967
4968#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4969 defaultoverlap allm5 metal5 allm3 metal3 20
4970 defaultsideoverlap allm5 metal5 allm3 metal3 54
4971 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4972
4973#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4974 defaultoverlap allm5 metal5 allm4 metal4 68
4975 defaultsideoverlap allm5 metal5 allm4 metal4 83
4976 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4977#endif (METAL5)
4978
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]4979#ifdef REDISTRIBUTION
4980#endif (REDISTRIBUTION)
4981
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4982# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4983
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4984variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4985
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4986 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
4987 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]4988 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4989 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
4990 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
4991 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
4992 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
4993 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4994 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4995 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4996
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]4997 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4998 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]4999 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5000 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5001 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
5002 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5003 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
5004 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5005 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5006 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5007 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5008 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5009 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5010 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5011 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5012 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5013
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5014 # Bipolars
5015 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
5016 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
5017 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
5018
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5019 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5020 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5021 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5022 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5023
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5024 # Extended drain devices (must appear before the regular devices)
5025 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5026 dnwell pwell,space/w error l=l w=w
5027 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5028 dnwell pwell,space/w error l=l w=w
5029 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5030 pwell,space/w nwell error l=l w=w
5031
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5032 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
5033 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
5034 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
5035 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5036 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
5037 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5038 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
5039 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5040 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
5041 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5042
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5043 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5044 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5045 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5046 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5047#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5048 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5049 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5050#endif (METAL5)
5051
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5052 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5053 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5054 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5055 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5056 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5057 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5058 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5059 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5060 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5061 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5062 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5063 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5064 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5065 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5066 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5067 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5068 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5069 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5070 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5071 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5072 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5073 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5074 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5075 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5076
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5077 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5078 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5079 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5080 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5081 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5082 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5083 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5084 *mvndiff pwell,space/w error l=l w=w
5085 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5086 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5087
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5088 device resistor sky130_fd_pr__res_generic_po rmp *poly
5089 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5090
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5091 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5092 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5093 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
5094 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5095 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5096 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5097 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5098 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5099
5100 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
5101 pwell,space/w a=area
5102 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
5103 pwell,space/w a=area
5104 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
5105 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5106 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5107 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5108
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5109
5110#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5111 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5112 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5113#endif (MIM)
5114
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5115 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5116
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5117 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5118 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5119 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5120 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5121 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5122 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5123 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5124 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5125 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5126 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5127 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5128 pwell,space/w
5129
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5130 # Note that corenvar, corepvar are not considered devices, and extract as
5131 # parasitic capacitance instead (but cap values need to be added).
5132
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5133 # Extended drain devices (must appear before the regular devices)
5134 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5135 dnwell pwell,space/w error
5136 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5137 dnwell pwell,space/w error
5138 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5139 pwell,space/w nwell error
5140
5141 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5142 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5143 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5144 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5145 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5146
5147 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5148 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5149 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5150 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5151
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5152 device resistor sky130_fd_pr__res_generic_po rmp *poly
5153 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5154 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5155 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5156 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5157#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5158 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5159 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5160#endif (METAL5)
5161
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5162 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5163 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5164 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5165 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5166 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5167 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5168 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5169 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5170 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5171 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5172 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5173 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5174 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5175 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5176 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5177 device resistor mrdn_hv mvndiffres *mvndiff
5178 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5179 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5180
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5181 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5182 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5183 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5184 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5185
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5186 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5187 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5188 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5189 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5190
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]5191 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
5192 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5193 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5194
5195#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5196 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5197 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5198#endif (MIM)
5199
5200end
5201
5202#-----------------------------------------------------
5203# Wiring tool definitions
5204#-----------------------------------------------------
5205
5206wiring
5207 # All wiring values are in nanometers
5208 scalefactor 10
5209
5210 contact lic 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5211 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5212 contact v2 280 m2 0 45 m3 25 0
5213#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5214 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5215 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5216#endif (METAL5)
5217
5218 contact pc 170 poly 50 80 li 0 80
5219 contact pdc 170 pdiff 40 60 li 0 80
5220 contact ndc 170 ndiff 40 60 li 0 80
5221 contact psc 170 psd 40 60 li 0 80
5222 contact nsc 170 nsd 40 60 li 0 80
5223
5224end
5225
5226#-----------------------------------------------------
5227# Plain old router. . .
5228#-----------------------------------------------------
5229
5230router
5231end
5232
5233#------------------------------------------------------------
5234# Plowing (restored in magic 8.2, need to fill this section)
5235#------------------------------------------------------------
5236
5237plowing
5238end
5239
5240#-----------------------------------------------------------------
5241# No special plot layers defined (use default PNM color choices)
5242#-----------------------------------------------------------------
5243
5244plot
5245 style pnm
5246 default
5247 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5248 draw fillblock4 no_color_at_all
5249 draw fomfill no_color_at_all
5250 draw polyfill no_color_at_all
5251 draw m1fill no_color_at_all
5252 draw m2fill no_color_at_all
5253 draw m3fill no_color_at_all
5254 draw m4fill no_color_at_all
5255 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5256 draw nwell cwell
5257end
5258