| commit | a12a941772e6267fc62b81dd27e95d34c83783ba | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Wed May 05 14:38:30 2021 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Wed May 05 14:38:30 2021 -0400 |
| tree | da839df9d49d6be642f37ffe1da1061d506faf25 | |
| parent | 7e29496eecf3ee8e1766f1b7f9441f97204d4735 [diff] [blame] |
Modified the techfile to not add nwell under pfetarea in cifinput when in the SRAM core cell (modification requested by Jesse Cirimelli-Low).
diff --git a/sky130/magic/sky130.tech b/sky130/magic/sky130.tech index 9e288ad..bfc9635 100644 --- a/sky130/magic/sky130.tech +++ b/sky130/magic/sky130.tech
@@ -2586,6 +2586,7 @@ # Always force nwell under pfet (nwell encloses pdiff by 0.18) layer nwell pfetarea + and-not COREID grow 180 # Copy mvpdiff areas up for contact checks