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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / daad1066de1e1cc5a8b4eb0d3c3526cb4e29da09 / . / sky130 / magic / sky130.tech
blob: 225663a299596ffba326c4c77e933be76e939847 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]66# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v5 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]144 dwell isosubstrate,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]163 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]167 -active mvnmosesd,mvntransistoresd,mvnfetesd
168 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]169 active varactor,varact,var
170 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]171
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]172 active pmoslvt,pfetlvt
173 active pmosmvt,pfetmvt
174 active pmoshvt,pfethvt
175 active nmoslvt,nfetlvt
176 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]177 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]178 -active sramnvar,corenvar,corenvaractor
179 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]180
181# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]182 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]183 active ndiff,ndiffusion,ndif
184 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]185 active mvndiff,mvndiffusion,mvndif
186 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]187 active ndiffc,ndcontact,ndc
188 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]189 active mvndiffc,mvndcontact,mvndc
190 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]191 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
192 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
193 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
194 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
195 active psubdiffcont,psubstratepcontact,psc,ptapc
196 active nsubdiffcont,nsubstratencontact,nsc,ntapc
197 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
198 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]199 -active obsactive
200 -active mvobsactive
201
202# Poly
203 active poly,p,polysilicon
204 active polycont,pc,pcontact,polycut,polyc
205 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]206 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]207
208# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]209 active npolyres,npres,mrp1
210 active ppolyres,ppres,xhrpoly
211 active xpolyres,xpres,xres,uhrpoly
212 active ndiffres,rnd,rdn,rndiff
213 active pdiffres,rpd,rdp,rpdiff
214 active mvndiffres,mvrnd,mvrdn,mvrndiff
215 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
216 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]217
218# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]219 active pdiode,pdi
220 active ndiode,ndi
221 active nndiode,nndi
222 active pdiodec,pdic
223 active ndiodec,ndic
224 active nndiodec,nndic
225 active mvpdiode,mvpdi
226 active mvndiode,mvndi
227 active mvpdiodec,mvpdic
228 active mvndiodec,mvndic
229 active pdiodelvt,pdilvt
230 active pdiodehvt,pdihvt
231 active ndiodelvt,ndilvt
232 active pdiodelvtc,pdilvtc
233 active pdiodehvtc,pdihvtc
234 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235
236# Local Interconnect
237 locali locali,li1,li
238 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]239 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]240 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]243 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]244
245# Metal 1
246 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]248 metal1 via1,m2contact,m2cut,m2c,via,v,v1
249 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]250 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 2
254 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 metal2 via2,m3contact,m3cut,m3c,v2
257 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]258 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259
260# Metal 3
261 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]263 -metal3 obsm3
264#ifdef METAL5
265 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]266 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]267
268#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]269 cap1 mimcap,mim,capm
270 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]271#endif
272
273# Metal 4
274 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276 -metal4 obsm4
277 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]278 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]279
280#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 cap2 mimcap2,mim2,capm2
282 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif
284
285# Metal 5
286 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]289 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]290#endif (METAL5)
291
292#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]293 metal5 mrdlcontact,mrdlc,pi1
294 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]296 metali pi2
297 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]298#endif (REDISTRIBUTION)
299
300# Miscellaneous
301 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]302 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]303 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]305# fixed resistor width identifiers
306 -comment res0p35
307 -comment res0p69
308 -comment res1p41
309 -comment res2p85
310 -comment res5p73
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]311# fixed bipolar area identifiers
312 -comment pnp0p68
313 -comment pnp3p40
314 -comment npn1p00
315 -comment npn2p00
316 -comment npn11p0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]317
318end
319
320#-----------------------------------------------------
321# Magic contact types
322#-----------------------------------------------------
323
324contact
325 pc poly locali
326 ndc ndiff locali
327 pdc pdiff locali
328 nsc nsd locali
329 psc psd locali
330 ndic ndiode locali
331 ndilvtc ndiodelvt locali
332 nndic nndiode locali
333 pdic pdiode locali
334 pdilvtc pdiodelvt locali
335 pdihvtc pdiodehvt locali
336 xpc xpc locali
337
338 mvndc mvndiff locali
339 mvpdc mvpdiff locali
340 mvnsc mvnsd locali
341 mvpsc mvpsd locali
342 mvndic mvndiode locali
343 mvpdic mvpdiode locali
344
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]345 mcon locali metal1
346 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]347
348 via1 metal1 metal2
349 via2 metal2 metal3
350#ifdef METAL5
351 via3 metal3 metal4
352 via4 metal4 metal5
353#endif (METAL5)
354 stackable
355
356#ifdef METAL5
357#ifdef MIM
358 # MiM cap contacts are not stackable!
359 mimcc mimcap metal4
360 mim2cc mimcap2 metal5
361#endif (MIM)
362
363 padl m1 m2 m3 m4 m5 glass
364#else
365 padl m1 m2 m3 glass
366#endif (!METAL5)
367
368#ifdef REDISTRIBUTION
369 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]370 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]371#endif (REDISTRIBUTION)
372end
373
374#-----------------------------------------------------
375# Layer aliases
376#-----------------------------------------------------
377
378aliases
379
380 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]381 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]382
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]383 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]384 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]385 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]386 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allfetsspecial scnfet,scpfet,scpfethvt
388 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]389 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]390
391 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
392 allnactive allnactivenonfet,allnfets
393 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]394 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]395
396 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
397 allpactive allpactivenonfet,allpfets
398 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]399 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]400
401 allactivenonfet allnactivenonfet,allpactivenonfet
402 allactive allactivenonfet,allfets
403
404 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
405
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]406 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]407 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]408 alldifflv allndifflv,allpdifflv
409 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
410 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
411 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
412
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]413 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]414 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]415 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]416 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]417 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]418 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
419 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
420 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
421 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
422
423 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]424 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]425
426 allpolyres mrp1,xhrpoly,uhrpoly,rmp
427 allpolynonfet *poly,allpolyres,xpc
428 allpolynonres *poly,allfets,xpc
429
430 allpoly allpolynonfet,allfets
431 allpolynoncap *poly,xpc,allfets,allpolyres
432
433 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
434 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
435 allndiffcontmv mvndc,mvnsc,mvndic
436 allpdiffcontmv mvpdc,mvpsc,mvpdic
437 allndiffcont allndiffcontlv,allndiffcontmv
438 allpdiffcont allpdiffcontlv,allpdiffcontmv
439 alldiffcontlv allndiffcontlv,allpdiffcontlv
440 alldiffcontmv allndiffcontmv,allpdiffcontmv
441 alldiffcont alldiffcontlv,alldiffcontmv
442
443 allcont alldiffcont,pc
444
445 allres allpolyres,allactiveres
446
447 allli *locali,coreli,rli
448 allm1 *m1,rm1
449 allm2 *m2,rm2
450 allm3 *m3,rm3
451#ifdef METAL5
452 allm4 *m4,rm4
453 allm5 *m5,rm5
454#endif (METAL5)
455
456 allpad padl
457
458 psub pwell
459
460end
461
462#-----------------------------------------------------
463# Layer drawing styles
464#-----------------------------------------------------
465
466styles
467 styletype mos
468 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]469 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]470 nwell nwell
471 pwell pwell
472 rpwell pwell ptransistor_stripes
473 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]474 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]475 pdiff pdiffusion
476 nsd ndiff_in_nwell
477 psd pdiff_in_pwell
478 nfet ntransistor ntransistor_stripes
479 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]480 npass ntransistor ntransistor_stripes
481 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]482 pfet ptransistor ptransistor_stripes
483 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]484 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]485 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 var polysilicon ndiff_in_nwell
487 ndc ndiffusion metal1 contact_X'es
488 pdc pdiffusion metal1 contact_X'es
489 nsc ndiff_in_nwell metal1 contact_X'es
490 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]491 corenvar polysilicon ndiff_in_nwell
492 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]493
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]494 pnp nwell ntransistor_stripes
495 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]496
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]498 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]499 pfethvt ptransistor ptransistor_stripes implant2
500 nfetlvt ntransistor ntransistor_stripes implant1
501 nsonos ntransistor implant3
502 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]503 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]504
505 mvndiff ndiffusion hvndiff_mask
506 mvpdiff pdiffusion hvpdiff_mask
507 mvnsd ndiff_in_nwell hvndiff_mask
508 mvpsd pdiff_in_pwell hvpdiff_mask
509 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]510 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]511 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
512 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]513 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]514 mvvar polysilicon ndiff_in_nwell hvndiff_mask
515 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
516 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
517 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
518 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
519
520 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]521 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]522 pc polysilicon metal1 contact_X'es
523 npolyres polysilicon silicide_block nselect2
524 ppolyres polysilicon silicide_block pselect2
525 xpc polysilicon pselect2 metal1 contact_X'es
526 rmp polysilicon poly_resist_stripes
527
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]528 res0p35 implant1
529 res0p69 implant1
530 res1p41 implant1
531 res2p85 implant1
532 res5p73 implant1
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]533 pnp0p68 implant1
534 pnp3p40 implant1
535 npn1p00 implant1
536 npn2p00 implant1
537 npn11p0 implant1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]538
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]539 pdiode pdiffusion pselect2
540 ndiode ndiffusion nselect2
541 pdiodec pdiffusion pselect2 metal1 contact_X'es
542 ndiodec ndiffusion nselect2 metal1 contact_X'es
543
544 nndiode ndiffusion nselect2 implant3
545 ndiodelvt ndiffusion nselect2 implant1
546 pdiodelvt pdiffusion pselect2 implant1
547 pdiodehvt pdiffusion pselect2 implant2
548 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
549 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
550 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
551
552 mvpdiode pdiffusion pselect2 hvpdiff_mask
553 mvndiode ndiffusion nselect2 hvndiff_mask
554 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
555 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
556 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
557
558 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]559 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]560 coreli metal1
561 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]562 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]563 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]564 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]565
566 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]567 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]568 rm1 metal2 poly_resist_stripes
569 obsm1 metal2
570 m2c metal2 metal3 via2arrow
571 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]572 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]573 rm2 metal3 poly_resist_stripes
574 obsm2 metal3
575 m3c metal3 metal4 via3alt
576 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]577 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]578 rm3 metal4 poly_resist_stripes
579 obsm3 metal4
580#ifdef METAL5
581#ifdef MIM
582 mimcap metal3 mems
583 mimcc metal3 contact_X'es mems
584 mimcap2 metal4 mems
585 mim2cc metal4 contact_X'es mems
586#endif (MIM)
587 via3 metal4 metal5 via4
588 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]589 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]590 rm4 metal5 poly_resist_stripes
591 obsm4 metal5
592 via4 metal5 metal6 via5
593 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]594 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]595 rm5 metal6 poly_resist_stripes
596 obsm5 metal6
597#endif (METAL5)
598#ifdef REDISTRIBUTION
599 mrdlc metal6 metal7 via6
600 metalrdl metal7
601 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]602 ubm metal8
603 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]604#endif (REDISTRIBUTION)
605
606 glass overglass
607 mrp1 poly_resist poly_resist_stripes
608 xhrpoly poly_resist silicide_block
609 uhrpoly poly_resist
610 ndiffres ndiffusion ndop_stripes
611 pdiffres pdiffusion pdop_stripes
612 mvndiffres ndiffusion hvndiff_mask ndop_stripes
613 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
614 comment comment
615 error_p error_waffle
616 error_s error_waffle
617 error_ps error_waffle
618 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]619 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]620
621 obswell cwell
622 obsactive implant4
623
624#ifndef METAL5
625 padl metal4 via4 overglass
626#else
627 padl metal6 via6 overglass
628#endif
629
630 magnet substrate_field_implant
631 rotate via3alt
632 fence via5
633end
634
635#-----------------------------------------------------
636# Special paint/erase rules
637#-----------------------------------------------------
638
639compose
640 compose nfet poly ndiff
641 compose pfet poly pdiff
642 compose var poly nsd
643
644 compose mvnfet poly mvndiff
645 compose mvpfet poly mvpdiff
646 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]647
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]648 paint obsmcon locali via1
649 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]650
651 paint ndc nwell pdc
652 paint nfet nwell pfet
653 paint scnfet nwell scpfet
654 paint ndiff nwell pdiff
655 paint psd nwell nsd
656 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]657 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]658
659 paint pdc pwell ndc
660 paint pfet pwell nfet
661 paint scpfet pwell scnfet
662 paint pdiff pwell ndiff
663 paint nsd pwell psd
664 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]665 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]666
667 paint pdc coreli pdc
668 paint ndc coreli ndc
669 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]670 paint nsc coreli nsc
671 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]672 paint viali coreli viali
673
674 paint coreli pdc pdc
675 paint coreli ndc ndc
676 paint coreli pc pc
677 paint coreli nsc nsc
678 paint coreli psc psc
679 paint coreli viali viali
680
681#ifdef METAL5
682 paint m4 obsm4 m4
683 paint m5 obsm5 m5
684#endif (METAL5)
685end
686
687#-----------------------------------------------------
688# Electrical connectivity
689#-----------------------------------------------------
690
691connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]692 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
693 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]694 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]695 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]696 *m2,m2fill *m2,m2fill
697 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]698#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]699 *m4,m4fill *m4,m4fill
700 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]701#ifdef MIM
702 *mimcap *mimcap
703 *mimcap2 *mimcap2
704#endif (MIM)
705#endif (METAL5)
706 allnactivenonfet allnactivenonfet
707 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]708 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]709#ifdef REDISTRIBUTION
710 # RDL connects to m5 (i.e., padl) through glass cut
711 *mrdl *mrdl
712 glass metrdl
713#endif (REDISTRIBUTION)
714end
715
716#-----------------------------------------------------
717# CIF/GDS output layer definitions
718#-----------------------------------------------------
719# NOTE: All values in this section MUST be multiples of 25
720# or else magic will scale below the allowed layout grid size
721
722cifoutput
723
724#----------------------------------------------------------------
725style gdsii
726# NOTE: This section is used for actual GDS output
727#----------------------------------------------------------------
728 scalefactor 10 nanometers
729 options calma-permissive-labels
730 gridlimit 5
731
732#----------------------------------------------------------------
733# Create a temp layer from the cell bounding box for use in
734# generating ID layers. Note that "boundary", unlike "bbox",
735# requires the FIXED_BBOX property (abutment box) in the cell.
736#----------------------------------------------------------------
737 templayer CELLBOUND
738 boundary
739
740#----------------------------------------------------------------
741# BOUND
742#----------------------------------------------------------------
743 layer BOUND CELLBOUND
744 calma 235 4
745
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]746#----------------------------------------------------------------
747# DNWELL
748#----------------------------------------------------------------
749
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]750 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]751 calma 64 18
752
753 layer PWRES rpw
754 and dnwell
755 calma 64 13
756
757#----------------------------------------------------------------
758# NWELL
759#----------------------------------------------------------------
760
761 layer NWELL allnwell
762 bloat-all rpw dnwell
763 and-not rpw,pwell
764 calma 64 20
765
766 layer WELLTXT
767 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]768 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]769
770 layer WELLPIN
771 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]772 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]773
774#----------------------------------------------------------------
775# SUB (text/port only)
776#----------------------------------------------------------------
777
778 layer SUBTXT
779 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]780 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]781
782 layer SUBPIN
783 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]784 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]785
786#----------------------------------------------------------------
787# DIFF
788#----------------------------------------------------------------
789
790 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]791 calma 65 20
792
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]793 layer DIFFTXT
794 labels allnactivenontap,allpactivenontap noport
795 calma 65 6
796
797 layer DIFFPIN
798 labels allnactivenontap,allpactivenontap port
799 calma 65 16
800
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]801#----------------------------------------------------------------
802# TAP
803#----------------------------------------------------------------
804
805 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]806 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]807 calma 65 44
808
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]809 layer TAPTXT
810 labels allnactivetap,allpactivetap noport
811 calma 65 5
812
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]813#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]814# FOM
815#----------------------------------------------------------------
816
817 layer FOMFILL fomfill
818 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]819 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]820
821#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]822# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]823#----------------------------------------------------------------
824
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]825 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]826 grow 15
827 or xhrpoly,uhrpoly,xpc
828 grow 110
829 bloat-or allpactivetap * 125 allnactivenontap 0
830 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]831
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]832 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]833 grow 125
834 bloat-or allnactivetap * 125 allpactivenontap 0
835 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]836
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]837 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]838 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]839 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]840
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]841 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]842 grow 185
843 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]844 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]845 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]846 calma 94 20
847
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]848 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]849 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]850 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]851
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]852 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]853 grow 185
854 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]855 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]856 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]857 calma 93 44
858
859#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]860# LVID
861#----------------------------------------------------------------
862
863 layer LVID nnfet
864 grow 100
865 calma 81 60
866
867#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]868# LVTN
869#----------------------------------------------------------------
870
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]871 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]872 grow 180
873 bridge 380 380
874 grow 185
875 shrink 185
876 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]877 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]878 calma 125 44
879
880#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]881# HVTR
882#----------------------------------------------------------------
883
884 layer HVTR pfetmvt
885 grow 180
886 bridge 380 380
887 grow 185
888 shrink 185
889 close 265000
890 calma 18 20
891
892#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]893# HVTP
894#----------------------------------------------------------------
895
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]896 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]897 grow 180
898 bridge 380 380
899 grow 185
900 shrink 185
901 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]902 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]903 calma 78 44
904
905#----------------------------------------------------------------
906# SONOS
907#----------------------------------------------------------------
908
909 layer SONOS nsonos
910 grow 100
911 grow-min 410
912 bridge 500 410
913 grow 250
914 shrink 250
915 calma 80 20
916
917#----------------------------------------------------------------
918# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]919# coreli layer indicates a cell needing COREID. Also, devices
920# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]921#----------------------------------------------------------------
922
923 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]924 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]925 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]926 calma 81 2
927
928#----------------------------------------------------------------
929# STDCELL applies to all cells containing scnfet or scpfet.
930#----------------------------------------------------------------
931
932 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]933 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]934 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]935 calma 81 4
936
937#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]938# ESDID is a marker layer for ESD devices in the padframe I/O.
939#----------------------------------------------------------------
940
941 layer ESDID
942 bloat-all mvnfetesd *mvndiff,*poly
943 bloat-all mvpfetesd *mvpdiff,*poly
944 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]945 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]946 calma 81 19
947
948#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]949# NPNID and PNPID apply to bipolar transistors
950#----------------------------------------------------------------
951
952 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]953 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]954 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]955 calma 82 20
956
957 templayer pnparea pnp
958 grow 400
959
960 layer PNPID
961 bloat-all pnparea *psd
962 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]963 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]964 calma 82 44
965
966#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]967# RPM
968#----------------------------------------------------------------
969
970 layer RPM
971 bloat-all xhrpoly xpc
972 grow 200
973 grow-min 1270
974 grow 420
975 shrink 420
976 calma 86 20
977
978#----------------------------------------------------------------
979# URPM (2kOhms/sq. poly implant)
980#----------------------------------------------------------------
981
982 layer URPM
983 bloat-all uhrpoly xpc
984 grow 200
985 grow-min 1270
986 grow 420
987 shrink 420
988 calma 79 20
989
990#----------------------------------------------------------------
991# LDNTM (Tip implant for SONOS FETs)
992#----------------------------------------------------------------
993
994 layer LDNTM
995 bloat-all nsonos *ndiff
996 grow 185
997 grow 345
998 shrink 345
999 calma 11 44
1000
1001#----------------------------------------------------------------
1002# HVNTM (Tip implant for MV ndiff devices)
1003#----------------------------------------------------------------
1004
1005 templayer hvntm_block *mvpsd
1006 grow 185
1007
1008 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1009 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1010 bloat-all mvvaractor *mvnsd
1011 and-not hvntm_block
1012 grow 185
1013 grow 345
1014 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1015 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1016 calma 125 20
1017
1018#----------------------------------------------------------------
1019# POLY
1020#----------------------------------------------------------------
1021
1022 layer POLY allpoly
1023 calma 66 20
1024
1025 layer POLYTXT
1026 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1027 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1028
1029 layer POLYPIN
1030 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1031 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1032
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1033 layer POLYFILL polyfill
1034 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1035 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1036
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1037#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1038# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1039#----------------------------------------------------------------
1040
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1041 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1042 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1043 bloat-all alldiffmv nwell
1044 grow 345
1045 shrink 345
1046
1047 templayer large_ptap_mv thkox_area
1048 shrink 420
1049 grow 420
1050
1051 templayer small_ptap_mv thkox_area
1052 and-not large_ptap_mv
1053 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1054 grow-min 840
1055
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1056 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1057 bridge 700 600
1058 grow 345
1059 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1060 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1061 calma 75 20
1062
1063#----------------------------------------------------------------
1064# CONT (LICON)
1065#----------------------------------------------------------------
1066
1067 layer CONT allcont
1068 squares-grid 0 170 170
1069 calma 66 44
1070
1071 # Contact for pres is different than other LICON contacts
1072 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1073 templayer xpc_horiz xpc
1074 shrink 1007
1075 grow 1007
1076
1077 layer CONT xpc
1078 and-not xpc_horiz
1079 # Force long edge vertical for contacts narrower than 2um
1080 # Minimum space is 350 but 520 satisfies no. of contacts rule
1081 slots 80 190 520 80 2000 350
1082 calma 66 44
1083
1084 layer CONT xpc
1085 and xpc_horiz
1086 # Force long edge vertical for contacts wider than 2um
1087 # Minimum space is 350 but 520 satisfies no. of contacts rule
1088 slots 80 2000 350 80 190 520
1089 calma 66 44
1090
1091#----------------------------------------------------------------
1092# NPC (Nitride poly cut)
1093# surrounds CONT (LICON) on poly only (i.e., pc)
1094#----------------------------------------------------------------
1095
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1096 # Avoids a common case of NPC bridges too close to other LICON shapes.
1097 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1098 grow 90
1099
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1100 layer NPC pc
1101 squares-grid 0 170 170
1102 grow 100
1103 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1104 and-not diffcutarea
1105 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1106 grow 130
1107 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1108 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1109 calma 95 20
1110
1111 # NPC is also generated on xhrpoly and uhrpoly resistors
1112
1113 layer NPC xpc,xhrpoly,uhrpoly
1114 # xpc surrounds precision_resistor by 0.095um
1115 grow 95
1116 grow 130
1117 shrink 130
1118 calma 95 20
1119
1120#----------------------------------------------------------------
1121# Device markers
1122#----------------------------------------------------------------
1123
1124 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1125 calma 65 13
1126
1127 layer POLYRES mrp1
1128 calma 66 13
1129
1130 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1131 layer POLYSHORT rmp
1132 calma 66 15
1133
1134 # POLYRES extends to edge of contact cut
1135 layer POLYRES xhrpoly,uhrpoly
1136 grow 60
1137 and xpc
1138 or xhrpoly,uhrpoly
1139 calma 66 13
1140
1141 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1142 # To be done: Expand to include anode, cathode, and guard ring
1143 calma 81 23
1144
1145#----------------------------------------------------------------
1146# LI
1147#----------------------------------------------------------------
1148 layer LI allli
1149 calma 67 20
1150
1151 layer LITXT
1152 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1153 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1154
1155 layer LIPIN
1156 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1157 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1158
1159 layer LIRES rli
1160 labels rli
1161 calma 67 13
1162
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1163 layer LIFILL lifill
1164 labels lifill
1165 calma 56 28
1166
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1167#----------------------------------------------------------------
1168# MCON
1169#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1170 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1171 squares-grid 0 170 190
1172 calma 67 44
1173
1174#----------------------------------------------------------------
1175# MET1
1176#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1177 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1178 calma 68 20
1179
1180 layer MET1TXT
1181 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1182 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1183
1184 layer MET1PIN
1185 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1186 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1187
1188 layer MET1RES rm1
1189 labels rm1
1190 calma 68 13
1191
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1192 layer MET1FILL m1fill
1193 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1194 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1195
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1196#----------------------------------------------------------------
1197# VIA1
1198#----------------------------------------------------------------
1199 layer VIA1 via1
1200 squares-grid 55 150 170
1201 calma 68 44
1202
1203#----------------------------------------------------------------
1204# MET2
1205#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1206 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1207 calma 69 20
1208
1209 layer MET2TXT
1210 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1211 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1212
1213 layer MET2PIN
1214 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1215 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1216
1217 layer MET2RES rm2
1218 labels rm2
1219 calma 69 13
1220
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1221 layer MET2FILL m2fill
1222 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1223 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1224
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1225#----------------------------------------------------------------
1226# VIA2
1227#----------------------------------------------------------------
1228 layer VIA2 via2
1229 squares-grid 40 200 200
1230 calma 69 44
1231
1232#----------------------------------------------------------------
1233# MET3
1234#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1235 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1236 calma 70 20
1237
1238 layer MET3TXT
1239 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1240 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1241
1242 layer MET3PIN
1243 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1244 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1245
1246 layer MET3RES rm3
1247 labels rm3
1248 calma 70 13
1249
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1250 layer MET3FILL m3fill
1251 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1252 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1253
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1254#ifdef METAL5
1255#----------------------------------------------------------------
1256# VIA3
1257#----------------------------------------------------------------
1258 layer VIA3 via3
1259#ifdef MIM
1260 or mimcc
1261#endif (MIM)
1262 squares-grid 60 200 200
1263 calma 70 44
1264
1265#----------------------------------------------------------------
1266# MET4
1267#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1268 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1269 calma 71 20
1270
1271 layer MET4TXT
1272 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1273 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1274
1275 layer MET4PIN
1276 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1277 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1278
1279 layer MET4RES rm4
1280 labels rm4
1281 calma 71 13
1282
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1283 layer MET4FILL m4fill
1284 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1285 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1286
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1287#----------------------------------------------------------------
1288# VIA4
1289#----------------------------------------------------------------
1290 layer VIA4 via4
1291#ifdef MIM
1292 or mim2cc
1293#endif (MIM)
1294 squares-grid 190 800 800
1295 calma 71 44
1296
1297#----------------------------------------------------------------
1298# MET5
1299#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1300 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1301 calma 72 20
1302
1303 layer MET5TXT
1304 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1305 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1306
1307 layer MET5PIN
1308 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1309 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1310
1311 layer MET5RES rm5
1312 labels rm5
1313 calma 72 13
1314
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1315 layer MET5FILL m5fill
1316 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1317 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1318
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1319#endif (METAL5)
1320
1321#ifdef REDISTRIBUTION
1322#----------------------------------------------------------------
1323# RDL
1324#----------------------------------------------------------------
1325 layer RDL *metrdl
1326 calma 74 20
1327
1328 layer RDLTXT
1329 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1330 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1331
1332 layer RDLPIN
1333 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1334 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1335
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1336 layer PI1 *metrdl
1337 and padl,glass
1338 # Test only---needs GDS layer number
1339
1340 layer UBM *metrdl
1341 shrink 50000
1342 grow 40000
1343 # Test only---needs GDS layer number
1344
1345 layer PI2 *metrdl
1346 shrink 50000
1347 grow 25000
1348 # Test only---needs GDS layer number
1349
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1350#endif REDISTRIBUTION
1351
1352#----------------------------------------------------------------
1353# GLASS
1354#----------------------------------------------------------------
1355 layer GLASS glass
1356 calma 76 20
1357
1358#ifdef MIM
1359#----------------------------------------------------------------
1360# CAPM
1361#----------------------------------------------------------------
1362 layer CAPM *mimcap
1363 labels mimcap
1364 calma 89 44
1365
1366 layer CAPM2 *mimcap2
1367 labels mimcap2
1368 calma 97 44
1369#endif (MIM)
1370
1371#----------------------------------------------------------------
1372# Chip top level marker for DRC latchup rules to check 15um
1373# distance to taps (otherwise 6um is used)
1374#----------------------------------------------------------------
1375
1376 layer LOWTAPDENSITY
1377 bbox top
1378 # Clear 200um for pads + 50um for required high tap density
1379 # in critical area.
1380 shrink 250000
1381 calma 81 14
1382
1383#----------------------------------------------------------------
1384# FILLBLOCK
1385#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1386 layer FILLOBSFOM obsactive
1387 calma 22 24
1388
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1389 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1390 calma 62 24
1391
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1392 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1393 calma 105 52
1394
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1395 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1396 calma 107 24
1397
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1398 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1399 calma 112 4
1400
1401 render DNWELL cwell -0.1 0.1
1402 render NWELL nwell 0.0 0.2062
1403 render DIFF ndiffusion 0.2062 0.12
1404 render TAP pdiffusion 0.2062 0.12
1405 render POLY polysilicon 0.3262 0.18
1406 render CONT via 0.5062 0.43
1407 render LI metal1 0.9361 0.10
1408 render MCON via 1.0361 0.34
1409 render MET1 metal2 1.3761 0.36
1410 render VIA1 via 1.7361 0.27
1411 render MET2 metal3 2.0061 0.36
1412 render VIA2 via 2.3661 0.42
1413 render MET3 metal4 2.7861 0.845
1414#ifdef METAL5
1415 render VIA3 via 3.6311 0.39
1416 render MET4 metal5 4.0211 0.845
1417 render VIA4 via 4.8661 0.505
1418 render MET5 metal6 5.3711 1.26
1419 render CAPM metal8 2.4661 0.2
1420 render CAPM2 metal9 3.7311 0.2
1421#ifdef REDISTRIBUTION
1422 render RDL metal7 11.8834 4.0
1423#endif (!REDISTRIBUTION)
1424#endif (!METAL5)
1425
1426#----------------------------------------------------------------
1427style drc
1428#----------------------------------------------------------------
1429# NOTE: This style is used for DRC only, not for GDS output
1430#----------------------------------------------------------------
1431 scalefactor 10 nanometers
1432 options calma-permissive-labels
1433
1434 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1435 templayer dnwell_shrink dnwell
1436 shrink 1030
1437
1438 templayer nwell_missing dnwell
1439 grow 400
1440 and-not dnwell_shrink
1441 and-not nwell
1442
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1443 templayer pwell_in_dnwell dnwell
1444 and-not nwell
1445
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1446 # SONOS nFET devices must be in deep nwell
1447 templayer dnwell_missing nsonos
1448 and-not dnwell
1449
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1450 # SONOS nFET devices must be in cell with abutment box
1451 templayer abutment_box
1452 boundary
1453
1454 templayer bbox_missing nsonos
1455 and-not abutment_box
1456
1457 # Make sure nwell covers varactor poly
1458 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1459 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1460 grow 150
1461 and-not nwell
1462
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1463 # Define MiM cap bottom plate for spacing rule
1464 templayer mim_bottom
1465 bloat-all *mimcap *metal3
1466
1467 # Define MiM2 cap bottom plate for spacing rule
1468 templayer mim2_bottom
1469 bloat-all *mimcap2 *metal4
1470
1471 # Note that metal fill is performed by the foundry and so is not
1472 # an option for a cifoutput style.
1473
1474 # Check latchup rule (15um minimum from tap LICON center to any
1475 # non-tap diffusion. Note that to count as a tap, the diffusion
1476 # must be contacted to LI
1477
1478 templayer ptap_reach psc,mvpsc
1479 and-not dnwell
1480 # grow total is 15um. grow in 0.84um increments to ensure that
1481 # no nwell ring is crossed
1482 grow 840
1483 and-not nwell,dnwell
1484 grow 840
1485 and-not nwell,dnwell
1486 grow 840
1487 and-not nwell,dnwell
1488 grow 840
1489 and-not nwell,dnwell
1490 grow 840
1491 and-not nwell,dnwell
1492 grow 840
1493 and-not nwell,dnwell
1494 grow 840
1495 and-not nwell,dnwell
1496 grow 840
1497 and-not nwell,dnwell
1498 grow 840
1499 and-not nwell,dnwell
1500 grow 840
1501 and-not nwell,dnwell
1502 grow 840
1503 and-not nwell,dnwell
1504 grow 840
1505 and-not nwell,dnwell
1506 grow 840
1507 and-not nwell,dnwell
1508 grow 840
1509 and-not nwell,dnwell
1510 grow 840
1511 and-not nwell,dnwell
1512 grow 840
1513 and-not nwell,dnwell
1514 grow 840
1515 and-not nwell,dnwell
1516 grow 635
1517 and-not nwell,dnwell
1518
1519 templayer ptap_missing *ndiff,*mvndiff
1520 and-not dnwell
1521 and-not ptap_reach
1522
1523 templayer ntap_reach nsc,mvnsc
1524 # grow total is 15um. grow in 1.27um increments to ensure that
1525 # no nwell ring is crossed. There is no difference between
1526 # ntaps in and out of deep nwell.
1527 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1528 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1529 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1530 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1531 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1532 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1533 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1534 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1535 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1536 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1537 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1538 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1539 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1540 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1541 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1542 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1543 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1544 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1545 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1546 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1547 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1548 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1549 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1550 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1551
1552 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1553 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1554 and-not ntap_reach
1555
1556 templayer dptap_reach psc,mvpsc
1557 and dnwell
1558 grow 840
1559 and-not nwell
1560 and dnwell
1561 grow 840
1562 and-not nwell
1563 and dnwell
1564 grow 840
1565 and-not nwell
1566 and dnwell
1567 grow 840
1568 and-not nwell
1569 and dnwell
1570 grow 840
1571 and-not nwell
1572 and dnwell
1573 grow 840
1574 and-not nwell
1575 and dnwell
1576 grow 840
1577 and-not nwell
1578 and dnwell
1579 grow 840
1580 and-not nwell
1581 and dnwell
1582 grow 840
1583 and-not nwell
1584 and dnwell
1585 grow 840
1586 and-not nwell
1587 and dnwell
1588 grow 840
1589 and-not nwell
1590 and dnwell
1591 grow 840
1592 and-not nwell
1593 and dnwell
1594 grow 840
1595 and-not nwell
1596 and dnwell
1597 grow 840
1598 and-not nwell
1599 and dnwell
1600 grow 840
1601 and-not nwell
1602 and dnwell
1603 grow 840
1604 and-not nwell
1605 and dnwell
1606 grow 840
1607 and-not nwell
1608 and dnwell
1609 grow 635
1610 and-not nwell
1611 and dnwell
1612
1613 templayer dptap_missing *ndiff,*mvndiff
1614 and dnwell
1615 and-not dptap_reach
1616
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1617 templayer pdiff_crosses_dnwell dnwell
1618 grow 20
1619 and-not dnwell
1620 and allpdifflv,allpdiffmv
1621
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1622 # MV nwell must be 2um from any other nwell
1623 templayer mvnwell
1624 bloat-all alldiffmv nwell
1625 grow-min 840
1626 bridge 700 600
1627
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1628 # Simple spacing checks to lvnwell must use CIF-DRC rule
1629 templayer allmvdiffnowell *mvndiff,*mvpsd
1630
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1631 templayer lvnwell nwell
1632 and-not mvnwell
1633
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1634 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1635 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1636
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1637 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1638 and-not nwell_with_tap
1639
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1640 templayer tap_with_licon
1641 bloat-all psc,mvpsc psd,mvpsd
1642 bloat-all nsc,mvnsc nsd,mvnsd
1643
1644 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1645 and-not tap_with_licon
1646
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1647 # Make sure varactor nwell contains no P diffusion
1648 templayer pdiff_in_varactor_well
1649 bloat-all varactor,mvvaractor nwell
1650 and allpactive
1651
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1652 # HVNTM spacing requires recreating HVNTM
1653 templayer hvntm_block *mvpsd
1654 grow 185
1655
1656 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1657 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1658 bloat-all mvvaractor *mvnsd
1659 and-not hvntm_block
1660 grow 185
1661 grow 345
1662 shrink 345
1663 and-not hvntm_block
1664
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1665 # RPM spacing checks require recreating RPM
1666 templayer rpm_generate
1667 bloat-all xhrpoly,uhrpoly xpc
1668 grow 200
1669 grow-min 1270
1670 grow 420
1671 shrink 420
1672
1673 # Check distance RPM to NSDM
1674 templayer rpm_nsd_check rpm_generate
1675 grow 325
1676 and allndifflv,allndiffmv
1677
1678 # Check distance RPM to (unrelated) POLY
1679 templayer rpm_poly_check rpm_generate
1680 grow 200
1681 and-not xhrpoly,uhrpoly,xpc
1682 and allpoly
1683
1684 # Check distance RPM to HVNTM
1685 templayer rpm_hvntm_check rpm_generate
1686 grow 385
1687 and allndiffmvnontap
1688
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1689 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1690 close 140000
1691
1692 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1693 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1694
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1695 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1696 close 140000
1697
1698 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1699 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1700
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1701 templayer m1_huge allm1
1702 shrink 1500
1703 grow 1500
1704
1705 templayer m1_large_halo m1_huge
1706 grow 280
1707 and-not m1_huge
1708 and allm1
1709
1710 templayer m2_huge allm2
1711 shrink 1500
1712 grow 1500
1713
1714 templayer m2_large_halo m2_huge
1715 grow 280
1716 and-not m2_huge
1717 and allm2
1718
1719 templayer m3_huge allm3
1720 shrink 1500
1721 grow 1500
1722
1723 templayer m3_large_halo m3_huge
1724 grow 400
1725 and-not m3_huge
1726 and allm3
1727
1728 templayer m4_huge allm4
1729 shrink 1500
1730 grow 1500
1731
1732 templayer m4_large_halo m4_huge
1733 grow 400
1734 and-not m4_huge
1735 and allm4
1736
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1737#ifdef EXPERIMENTAL
1738#----------------------------------------------------------------
1739style paint
1740#----------------------------------------------------------------
1741# NOTE: This style is used for database manipulations only via
1742# the "cif paint" command.
1743#----------------------------------------------------------------
1744
1745 scalefactor 10 nanometers
1746
1747 templayer m1grow *m1
1748 grow 290
1749
1750 # layer listrap: Use the following set of commands to strap local
1751 # interconnect wires with metal1 (inside the cursor box) to satisfy
1752 # the maximum aspect ratio rule for local interconnect:
1753 #
1754 # tech unlock *
1755 # cif ostyle paint
1756 # cif paint m1strap comment
1757 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1758 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1759 # erase comment
1760
1761 templayer m1strap *li
1762 and-not m1grow
1763 grow 30
1764
1765 templayer listrap comment
1766 slots 30 170 170 60
1767
1768#endif (EXPERIMENTAL)
1769
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1770#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1771style density
1772#----------------------------------------------------------------
1773# Style used by scripts to check for fill density
1774#----------------------------------------------------------------
1775 scalefactor 10 nanometers
1776 options calma-permissive-labels
1777 gridlimit 5
1778
1779 templayer fom_all alldiff,fomfill
1780
1781 templayer poly_all allpoly,polyfill
1782
1783 templayer li_all allli,lifill
1784
1785 templayer m1_all allm1,m1fill
1786
1787 templayer m2_all allm2,m2fill
1788
1789 templayer m3_all allm3,m3fill
1790
1791 templayer m4_all allm4,m4fill
1792
1793 templayer m5_all allm5,m5fill
1794
1795#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1796style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1797#----------------------------------------------------------------
1798# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1799# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1800#----------------------------------------------------------------
1801 scalefactor 10 nanometers
1802 options calma-permissive-labels
1803 gridlimit 5
1804
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1805#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1806# Generate and retain a layer representing the bounding box.
1807#
1808# For variant ():
1809# The bounding box is the full extent of geometry on the top level
1810# cell.
1811#
1812# For variant (tiled):
1813# Use with a script that breaks layout into flattened tiles and runs
1814# fill individually on each. The tiles should be larger than the
1815# step size, and each should draw a layer "comment" the size of the
1816# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1817#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1818
1819 variants ()
1820 templayer topbox
1821 bbox top
1822
1823 variants (tiled)
1824 templayer topbox comment
1825 # Each tile imposes the full keepout distance rule of
1826 # 3um on all sides.
1827 shrink 1500
1828
1829 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1830
1831#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1832# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1833# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1834# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1835# Enclosure by nwell = Diff/Tap 8 = 0.18um
1836#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1837
1838 templayer mvnwell
1839 bloat-all alldiffmv nwell
1840
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1841 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1842 and-not mvnwell
1843
1844 templayer well_shrink mvnwell
1845 shrink 250
1846 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1847 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1848 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1849 grow 340
1850 and-not well_shrink
1851
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1852#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1853# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1854#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1855 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1856 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1857 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1858 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1859
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1860 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1861 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1862 grow 1000
1863
1864#---------------------------------------------------
1865# FOM and POLY fill
1866#---------------------------------------------------
1867 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1868 # slots 0 4080 1320 0 4080 1320 1360 0
1869 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1870 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1871 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1872 shrink 2035
1873 grow 2035
1874
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1875#---------------------------------------------------
1876
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1877 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1878 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1879 or obstruct_poly
1880 templayer polyfill_pass1 topbox
1881 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1882 and-not obstruct_poly_pass1
1883 and topbox
1884 shrink 355
1885 grow 355
1886
1887#---------------------------------------------------
1888
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1889 templayer obstruct_fom_pass2 fomfill_pass1
1890 grow 1290
1891 or polyfill_pass1
1892 grow 300
1893 or obstruct_fom
1894 templayer fomfill_pass2 topbox
1895 slots 0 2500 1320 0 2500 1320 1360 0
1896 and-not obstruct_fom_pass2
1897 and topbox
1898 shrink 1245
1899 grow 1245
1900
1901#---------------------------------------------------
1902
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1903 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1904 grow 60
1905 or fomfill_pass1,fomfill_pass2
1906 grow 300
1907 or obstruct_poly
1908 templayer polyfill_coarse topbox
1909 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1910 and-not obstruct_poly_coarse
1911 and topbox
1912 shrink 355
1913 grow 355
1914
1915#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1916 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1917 grow 60
1918 or fomfill_pass1,fomfill_pass2
1919 grow 300
1920 or obstruct_poly
1921 templayer polyfill_medium topbox
1922 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1923 and-not obstruct_poly_medium
1924 and topbox
1925 shrink 265
1926 grow 265
1927
1928#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1929 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1930 grow 60
1931 or fomfill_pass1,fomfill_pass2
1932 grow 300
1933 or obstruct_poly
1934 templayer polyfill_fine topbox
1935 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1936 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1937 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1938 shrink 235
1939 grow 235
1940
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1941#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1942
1943 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1944 grow 1290
1945 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1946 grow 300
1947 or obstruct_fom
1948 templayer fomfill_coarse topbox
1949 slots 0 1500 1320 0 1500 1320 1360 0
1950 and-not obstruct_fom_coarse
1951 and topbox
1952 shrink 745
1953 grow 745
1954
1955#---------------------------------------------------
1956
1957 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1958 grow 1290
1959 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1960 grow 300
1961 or obstruct_fom
1962 templayer fomfill_fine topbox
1963 slots 0 500 400 0 500 400 160 0
1964 and-not obstruct_fom_fine
1965 and topbox
1966 shrink 245
1967 grow 245
1968
1969#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1970 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1971 or fomfill_pass2
1972 or fomfill_coarse
1973 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1974 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1975
1976 layer POLYFILL polyfill_pass1
1977 or polyfill_coarse
1978 or polyfill_medium
1979 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1980 calma 28 28
1981
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1982#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1983# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1984# Note requirement that LI fill may not overlap (non-fill)
1985# diff or poly.
1986#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1987
1988 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1989 grow 2800
1990 or alldiff,allpoly
1991 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1992 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]1993 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]1994 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1995 and-not obstruct_li_coarse
1996 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1997 shrink 1495
1998 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1999
2000 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2001 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2002 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2003 grow 300
2004 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2005 grow 200
2006 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2007 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2008 and-not obstruct_li_medium
2009 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2010 shrink 745
2011 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2012
2013 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2014 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2015 grow 300
2016 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2017 grow 200
2018 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2019 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2020 and-not obstruct_li_fine
2021 and topbox
2022 shrink 285
2023 grow 285
2024
2025 layer LIFILL lifill_coarse
2026 or lifill_medium
2027 or lifill_fine
2028 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2029
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2030#---------------------------------------------------
2031# MET1 fill
2032#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2033
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2034 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2035 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2036 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2037 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2038 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2039 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2040 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2041 shrink 995
2042 grow 995
2043
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2044 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2045 grow 2800
2046 or met1fill_coarse
2047 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2048 templayer met1fill_medium topbox
2049 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2050 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2051 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2052 shrink 495
2053 grow 495
2054
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2055 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2056 grow 300
2057 or met1fill_coarse,met1fill_medium
2058 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2059 templayer met1fill_fine topbox
2060 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2061 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2062 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2063 shrink 285
2064 grow 285
2065
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2066 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2067 grow 100
2068 or met1fill_coarse,met1fill_medium,met1fill_fine
2069 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2070 templayer met1fill_veryfine topbox
2071 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2072 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2073 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2074 shrink 145
2075 grow 145
2076
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2077 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2078 or met1fill_medium
2079 or met1fill_fine
2080 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2081 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2082
2083#---------------------------------------------------
2084# MET2 fill
2085#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2086 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2087 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2088 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2089 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2090 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2091 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2092 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2093 shrink 995
2094 grow 995
2095
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2096 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2097 grow 2800
2098 or met2fill_coarse
2099 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2100 templayer met2fill_medium topbox
2101 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2102 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2103 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2104 shrink 495
2105 grow 495
2106
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2107 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2108 grow 300
2109 or met2fill_coarse,met2fill_medium
2110 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2111 templayer met2fill_fine topbox
2112 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2113 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2114 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115 shrink 285
2116 grow 285
2117
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2118 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2119 grow 100
2120 or met2fill_coarse,met2fill_medium,met2fill_fine
2121 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2122 templayer met2fill_veryfine topbox
2123 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2124 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2125 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2126 shrink 145
2127 grow 145
2128
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2129 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2130 or met2fill_medium
2131 or met2fill_fine
2132 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2133 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2134
2135#---------------------------------------------------
2136# MET3 fill
2137#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2138 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2139 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2140 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2141 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2142 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2143 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2144 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2145 shrink 995
2146 grow 995
2147
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2148 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2149 grow 2700
2150 or met3fill_coarse
2151 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2152 templayer met3fill_medium topbox
2153 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2154 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2155 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2156 shrink 495
2157 grow 495
2158
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2159 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2160 grow 200
2161 or met3fill_coarse,met3fill_medium
2162 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2163 templayer met3fill_fine topbox
2164 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2165 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2166 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2167 shrink 285
2168 grow 285
2169
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2170 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2171 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2172 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2173 or met3fill_coarse,met3fill_medium,met3fill_fine
2174 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2175 templayer met3fill_veryfine topbox
2176 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2177 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2178 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2179 shrink 195
2180 grow 195
2181
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2182 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2183 or met3fill_medium
2184 or met3fill_fine
2185 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2186 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2187
2188#ifdef METAL5
2189#---------------------------------------------------
2190# MET4 fill
2191#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2192 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2193 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2194 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2195 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2196 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2197 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2198 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2199 shrink 995
2200 grow 995
2201
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2202 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2203 grow 2700
2204 or met4fill_coarse
2205 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2206 templayer met4fill_medium topbox
2207 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2208 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2209 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2210 shrink 495
2211 grow 495
2212
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2213 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2214 grow 200
2215 or met4fill_coarse,met4fill_medium
2216 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2217 templayer met4fill_fine topbox
2218 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2219 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2220 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2221 shrink 285
2222 grow 285
2223
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2224 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2225 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2226 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2227 or met4fill_coarse,met4fill_medium,met4fill_fine
2228 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2229 templayer met4fill_veryfine topbox
2230 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2231 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2232 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2233 shrink 195
2234 grow 195
2235
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2236 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2237 or met4fill_medium
2238 or met4fill_fine
2239 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2240 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2241
2242#---------------------------------------------------
2243# MET5 fill
2244#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2245 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2246 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2247 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2248 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2249 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2250 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2251 shrink 2495
2252 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2253
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2254 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2255 grow 1400
2256 or met5fill_coarse
2257 grow 1600
2258 templayer met5fill_medium topbox
2259 slots 0 3000 1600 0 3000 1600 1000 100
2260 and-not obstruct_m5_medium
2261 and topbox
2262 shrink 1495
2263 grow 1495
2264
2265 layer MET5FILL met5fill_coarse
2266 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2267 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2268#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2269
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2270end
2271
2272#-----------------------------------------------------------------------
2273cifinput
2274#-----------------------------------------------------------------------
2275# NOTE: All values in this section MUST be multiples of 25
2276# or else magic will scale below the allowed layout grid size
2277#-----------------------------------------------------------------------
2278
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2279style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2280 scalefactor 10 nanometers
2281 gridlimit 5
2282
2283 options ignore-unknown-layer-labels no-reconnect-labels
2284
2285#ifndef MIM
2286 ignore CAPM
2287 ignore CAPM2
2288#endif (!MIM)
2289#ifndef METAL5
2290 ignore MET4,VIA3
2291 ignore MET5,VIA4
2292#endif
2293 ignore NPC
2294 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2295 ignore CAPID
2296 ignore LDNTM
2297 ignore HVNTM
2298 ignore POLYMOD
2299 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2300 ignore FILLOBSPOLY
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2301 ignore OUTLINE
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2302
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2303 layer pnp NWELL,WELLTXT,WELLPIN
2304 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2305 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2306 variants (vendor)
2307 labels WELLTXT port
2308 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2309 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2310 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2311 labels WELLPIN port
2312
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2313 layer nwell NWELL,WELLTXT,WELLPIN
2314 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2315 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2316 variants (vendor)
2317 labels WELLTXT port
2318 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2319 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2320 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2321 labels WELLPIN port
2322
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2323 templayer nwellarea NWELL
2324 copyup nwelcheck
2325
2326 # Copy nwell areas up for diffusion checks
2327 templayer xnwelcheck nwelcheck
2328 copyup nwelcheck
2329
2330 templayer hvarea HVI
2331 copyup hvcheck
2332
2333 # Copy high-voltage (HVI) areas up for diffusion checks
2334 templayer xhvcheck hvcheck
2335 copyup hvcheck
2336
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2337 # Always draw pwell under p-tap and n-diff. This is not always
2338 # necessary but works better with deep nwell for correct extraction.
2339 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2340 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2341 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2342 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2343 grow 420
2344 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2345 variants (vendor)
2346 labels SUBTXT port
2347 variants ()
2348 labels SUBTXT text
2349 variants *
2350 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2351
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2352 layer dnwell DNWELL
2353 labels DNWELL
2354
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2355 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2356 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2357 and NPNID
2358
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2359 layer rpw PWRES
2360 and DNWELL
2361 labels PWRES
2362
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2363 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2364 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2365 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2366 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2367 and-not DIODE
2368 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2369 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2370 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2371 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2372 copyup ndifcheck
2373 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2374 variants (vendor)
2375 labels DIFFTXT port
2376 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2377 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2378 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2379 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2380
2381 layer ndiff ndiffarea
2382
2383 # Copy ndiff areas up for contact checks
2384 templayer xndifcheck ndifcheck
2385 copyup ndifcheck
2386
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2387 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2388 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2389 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2390 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2391 and-not DIODE
2392 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2393 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2394 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2395 copyup ndifcheck
2396 labels DIFF
2397 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2398 variants (vendor)
2399 labels DIFFTXT port
2400 variants ()
2401 labels DIFFTXT text
2402 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2403 labels DIFFPIN port
2404
2405 layer mvndiff mvndiffarea
2406
2407 # Copy ndiff areas up for contact checks
2408 templayer mvxndifcheck mvndifcheck
2409 copyup mvndifcheck
2410
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2411 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2412 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2413 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2414 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2415 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2416 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2417 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2418 and-not LVTN
2419 labels DIFF
2420
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2421 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2422 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2423 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2424 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2425 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2426 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2427 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2428 and LVTN
2429 labels DIFF
2430
2431 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2432 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2433 and-not HVI,hvcheck
2434 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2435 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2436
2437 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2438 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2439 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2440 labels DIFF
2441
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2442 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2443 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2444 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2445 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2446 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2447 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2448 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2449 copyup pdifcheck
2450 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2451 variants (vendor)
2452 labels DIFFTXT port
2453 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2454 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2455 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2456 labels DIFFPIN port
2457
2458 layer pdiff pdiffarea
2459
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2460 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2461 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2462 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2463 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2464 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2465 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2466 and-not LVTN
2467 labels DIFF
2468
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2469 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2470 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2471 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2472 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2473 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2474 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2475 and LVTN
2476 labels DIFF
2477
2478 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2479 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2480 and HVI,hvcheck
2481 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2482 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2483
2484 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2485 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2486 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2487 labels DIFF
2488
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2489 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2490 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2491 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2492 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2493 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2494 and-not DIODE
2495 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2496 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2497 copyup mvpdifcheck
2498 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2499 variants (vendor)
2500 labels DIFFTXT port
2501 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2502 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2503 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2504 labels DIFFPIN port
2505
2506 layer mvpdiff mvpdiffarea
2507
2508 # Copy pdiff areas up for contact checks
2509 templayer xpdifcheck pdifcheck
2510 copyup pdifcheck
2511
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2512 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2513 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2514 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2515 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2516 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2517 and-not LVTN
2518 and-not HVTP
2519 and DIODE
2520 labels DIFF
2521
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2522 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2523 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2524 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2525 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2526 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2527 and LVTN
2528 and-not HVTP
2529 and DIODE
2530 labels DIFF
2531
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2532 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2533 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2534 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2535 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2536 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2537 and-not LVTN
2538 and HVTP
2539 and DIODE
2540 labels DIFF
2541
2542 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2543 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2544 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2545 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2546
2547 # Define pfet areas as known pdiff, regardless of the presence of a well.
2548
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2549 templayer pfetarea DIFF,barediff
2550 and POLY
2551 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2552 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2553 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2554
2555 layer pfet pfetarea
2556 and-not LVTN
2557 and-not HVTP
2558 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2559 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2560 labels DIFF
2561
2562 layer scpfet pfetarea
2563 and-not LVTN
2564 and-not HVTP
2565 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2566 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2567 labels DIFF
2568
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2569 layer scpfethvt pfetarea
2570 and-not LVTN
2571 and HVTP
2572 and STDCELL
2573 labels DIFF
2574
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2575 layer ppu pfetarea
2576 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2577 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2578 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2579 # Shrink-grow operation eliminates the smaller parasitie device
2580 # shrink 70
2581 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2582 labels DIFF
2583
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2584 layer pfetlvt pfetarea
2585 and LVTN
2586 labels DIFF
2587
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2588 layer pfetmvt pfetarea
2589 and HVTR
2590 labels DIFF
2591
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2592 layer pfethvt pfetarea
2593 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2594 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2595 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2596 labels DIFF
2597
2598 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2599 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2600 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2601 grow 180
2602
2603 # Copy mvpdiff areas up for contact checks
2604 templayer mvxpdifcheck mvpdifcheck
2605 copyup mvpdifcheck
2606
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2607 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2608 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2609 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2610 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2611 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2612 and DIODE
2613 labels DIFF
2614
2615 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2616 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2617 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2618 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2619
2620 # Define pfet areas as known pdiff,
2621 # regardless of the presence of a
2622 # well.
2623
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2624 templayer mvpfetarea DIFF,barediff
2625 and POLY
2626 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2627 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2628 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2629
2630 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2631 and-not ESDID
2632 labels DIFF
2633
2634 layer mvpfetesd mvpfetarea
2635 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2636 labels DIFF
2637
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2638 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2639 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2640 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2641 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2642 and-not DIODE
2643 and-not DIFFRES
2644 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2645 variants (vendor)
2646 labels DIFFTXT port
2647 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2648 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2649 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2650 labels DIFFPIN port
2651
2652 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2653 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2654 and NWELL,nwelcheck
2655 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2656 labels DIFF
2657
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2658 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2659 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2660 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2661 and-not PSDM
2662 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2663 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2664 and-not LVTN
2665 and-not SONOS
2666 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2667 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2668 labels DIFF
2669
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2670 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2671 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2672 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2673 and-not PSDM
2674 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2675 and-not NWELL,nwelcheck
2676 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2677 and-not LVTN
2678 and-not SONOS
2679 and STDCELL
2680 labels DIFF
2681
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2682 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2683 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2684 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2685 and-not PSDM
2686 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2687 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2688 and COREID
2689 labels DIFF
2690
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2691 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2692 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2693 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2694 and-not PSDM
2695 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2696 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2697 and COREID
2698 # Shrink-grow operation eliminates the smaller npass device
2699 shrink 70
2700 grow 70
2701 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2702
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2703 # Devices abutting tap under gate are officially npd, not npass
2704 layer npd TAP
2705 grow 100
2706 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2707 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2708 and-not PSDM
2709 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2710 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2711 and COREID
2712 labels DIFF
2713
2714 layer nfetlvt DIFF,barediff
2715 and POLY
2716 or baretrans
2717 and-not PSDM
2718 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2719 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2720 and LVTN
2721 and-not SONOS
2722 labels DIFF
2723
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2724 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2725 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2726 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2727 and-not PSDM
2728 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2729 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2730 and LVTN
2731 and SONOS
2732 labels DIFF
2733
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2734 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2735 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2736 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2737 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2738 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2739 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2740 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2741 copyup nsubcheck
2742
2743 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2744 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2745
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2746 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2747 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2748 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2749 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2750 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2751 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2752
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2753 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2754 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2755 and POLY
2756 and COREID
2757 labels TAP
2758
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2759 templayer nsdexpand nsdarea
2760 grow 500
2761
2762 # Copy nsub areas up for contact checks
2763 templayer xnsubcheck nsubcheck
2764 copyup nsubcheck
2765
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2766 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2767 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2768 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2769 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2770 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2771 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2772 and-not pfetexpand
2773 copyup psubcheck
2774
2775 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2776 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2777
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2778 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2779 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2780 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2781 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2782 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2783 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2784
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2785 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2786 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2787 and POLY
2788 and COREID
2789 labels TAP
2790
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2791 templayer psdexpand psdarea
2792 grow 500
2793
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2794 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2795 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2796 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2797 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2798 and mvpfetexpand
2799 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2800 variants (vendor)
2801 labels DIFFTXT port
2802 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2803 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2804 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2805 labels DIFFPIN port
2806
2807 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2808 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2809 and NWELL,nwelcheck
2810 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2811 and-not mvrdpioedge
2812 labels DIFF
2813
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2814 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2815 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2816 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2817 and-not PSDM
2818 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2819 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2820 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2821 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2822
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2823 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2824 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2825 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2826 and-not PSDM
2827 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2828 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2829 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2830 and-not mvnfetarea
2831
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2832 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2833 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2834 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2835 and-not PSDM
2836 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2837 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2838 and ESDID
2839 and-not mvnnfetarea
2840 labels DIFF
2841
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2842 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2843 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2844 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2845 and-not PSDM
2846 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2847 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2848 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2849 and-not mvnnfetarea
2850 labels DIFF
2851
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2852 layer nnfet mvnnfetarea
2853 and LVID
2854 labels DIFF
2855
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2856 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2857 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2858 labels DIFF
2859
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2860 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2861 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2862 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2863 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2864 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2865 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2866 copyup mvnsubcheck
2867
2868 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2869 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2870
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2871 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2872 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2873 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2874 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2875 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2876
2877 templayer mvnsdexpand mvnsdarea
2878 grow 500
2879
2880 # Copy nsub areas up for contact checks
2881 templayer mvxnsubcheck mvnsubcheck
2882 copyup mvnsubcheck
2883
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2884 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2885 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2886 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2887 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2888 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2889 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2890 and-not mvpfetexpand
2891 copyup mvpsubcheck
2892
2893 layer mvpsd mvpsdarea
2894 labels DIFF
2895
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2896 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2897 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2898 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2899 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2900 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2901
2902 templayer mvpsdexpand mvpsdarea
2903 grow 500
2904
2905 # Copy psub areas up for contact checks
2906 templayer xpsubcheck psubcheck
2907 copyup psubcheck
2908
2909 templayer mvxpsubcheck mvpsubcheck
2910 copyup mvpsubcheck
2911
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2912 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2913 and-not PSDM
2914 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2915 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2916 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2917 and-not pfetexpand
2918 and psdexpand
2919
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2920 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2921 and-not PSDM
2922 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2923 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2924 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2925 and nsdexpand
2926
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2927 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2928 and-not PSDM
2929 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2930 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2931 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2932 and-not mvpfetexpand
2933 and mvpsdexpand
2934
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2935 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2936 and-not PSDM
2937 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2938 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2939 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2940 and mvnsdexpand
2941
2942 templayer hresarea POLY
2943 and RPM
2944 grow 3000
2945
2946 templayer uresarea POLY
2947 and URPM
2948 grow 3000
2949
2950 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2951 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2952 grow 3000
2953
2954 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2955 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2956 grow 3000
2957
2958 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2959
2960 layer pfet POLY
2961 and DIFF
2962 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2963 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2964 and-not STDCELL
2965
2966 layer scpfet POLY
2967 and DIFF
2968 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2969 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2970 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2971 and STDCELL
2972
2973 layer scpfethvt POLY
2974 and DIFF
2975 and diffresarea
2976 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2977 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2978 and STDCELL
2979
2980 templayer xpolyterm RPM,URPM
2981 and POLY
2982 and-not POLYRES
2983 # add back the 0.06um contact surround in the direction of the resistor
2984 grow 60
2985 and POLY
2986
2987 layer xpc xpolyterm
2988
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2989 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2990 and-not POLYRES
2991 and-not POLYSHORT
2992 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2993 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2994 and-not RPM
2995 and-not URPM
2996 copyup polycheck
2997
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2998 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2999 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3000 variants (vendor)
3001 labels POLYTXT port
3002 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3003 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3004 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3005 labels POLYPIN port
3006
3007 # Copy (non-resistor) poly areas up for contact checks
3008 templayer xpolycheck polycheck
3009 copyup polycheck
3010
3011 layer mrp1 POLY
3012 and POLYRES
3013 and-not RPM
3014 and-not URPM
3015 labels POLY
3016
3017 layer rmp POLY
3018 and POLYSHORT
3019 labels POLY
3020
3021 layer xhrpoly POLY
3022 and POLYRES
3023 and RPM
3024 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3025 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3026 and NPC
3027 and-not xpolyterm
3028 labels POLY
3029
3030 layer uhrpoly POLY
3031 and POLYRES
3032 and URPM
3033 and-not RPM
3034 and NPC
3035 and-not xpolyterm
3036 labels POLY
3037
3038 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3039 or barecont
3040 and LI
3041 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3042 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3043 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3044 and-not NWELL,nwelcheck
3045 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3046
3047 layer ndc ndcbase
3048 grow 85
3049 shrink 85
3050 shrink 85
3051 grow 85
3052 or ndcbase
3053 labels CONT
3054
3055 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3056 or barecont
3057 and LI
3058 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3059 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3060 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3061 and NWELL,nwelcheck
3062 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3063
3064 layer nsc nscbase
3065 grow 85
3066 shrink 85
3067 shrink 85
3068 grow 85
3069 or nscbase
3070 labels CONT
3071
3072 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3073 or barecont
3074 and LI
3075 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3076 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3077 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3078 and NWELL,nwelcheck
3079 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3080
3081 layer pdc pdcbase
3082 grow 85
3083 shrink 85
3084 shrink 85
3085 grow 85
3086 or pdcbase
3087 labels CONT
3088
3089 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3090 or barecont
3091 and LI
3092 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3093 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3094 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3095 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3096 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3097
3098 layer pdc pdcnowell
3099 grow 85
3100 shrink 85
3101 shrink 85
3102 grow 85
3103 or pdcnowell
3104 labels CONT
3105
3106 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3107 or barecont
3108 and LI
3109 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3110 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3111 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3112 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3113 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3114 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3115
3116 layer psc pscbase
3117 grow 85
3118 shrink 85
3119 shrink 85
3120 grow 85
3121 or pscbase
3122 labels CONT
3123
3124 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3125 or barecont
3126 and LI
3127 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3128 and POLY
3129 and-not DIFF
3130 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3131
3132 layer pc pcbase
3133 grow 85
3134 shrink 85
3135 shrink 85
3136 grow 85
3137 or pcbase
3138 labels CONT
3139
3140 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3141 or barecont
3142 and LI
3143 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3144 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3145 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3146 and DIODE
3147 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3148 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3149 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3150 and-not LVTN
3151
3152 layer ndic ndicbase
3153 grow 85
3154 shrink 85
3155 shrink 85
3156 grow 85
3157 or ndicbase
3158 labels CONT
3159
3160 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3161 or barecont
3162 and LI
3163 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3164 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3165 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3166 and DIODE
3167 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3168 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3169 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3170 and LVTN
3171
3172 layer ndilvtc ndilvtcbase
3173 grow 85
3174 shrink 85
3175 shrink 85
3176 grow 85
3177 or ndilvtcbase
3178 labels CONT
3179
3180 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3181 or barecont
3182 and LI
3183 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3184 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3185 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3186 and DIODE
3187 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3188 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3189 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3190 and-not LVTN
3191 and-not HVTP
3192
3193 layer pdic pdicbase
3194 grow 85
3195 shrink 85
3196 shrink 85
3197 grow 85
3198 or pdicbase
3199 labels CONT
3200
3201 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3202 or barecont
3203 and LI
3204 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3205 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3206 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3207 and DIODE
3208 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3209 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3210 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3211 and LVTN
3212 and-not HVTP
3213
3214 layer pdilvtc pdilvtcbase
3215 grow 85
3216 shrink 85
3217 shrink 85
3218 grow 85
3219 or pdilvtcbase
3220 labels CONT
3221
3222 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3223 or barecont
3224 and LI
3225 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3226 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3227 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3228 and DIODE
3229 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3230 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3231 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3232 and-not LVTN
3233 and HVTP
3234
3235 layer pdihvtc pdihvtcbase
3236 grow 85
3237 shrink 85
3238 shrink 85
3239 grow 85
3240 or pdihvtcbase
3241 labels CONT
3242
3243 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3244 or barecont
3245 and LI
3246 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3247 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3248 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3249 and-not NWELL,nwelcheck
3250 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3251
3252 layer mvndc mvndcbase
3253 grow 85
3254 shrink 85
3255 shrink 85
3256 grow 85
3257 or mvndcbase
3258 labels CONT
3259
3260 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3261 or barecont
3262 and LI
3263 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3264 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3265 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3266 and NWELL,nwelcheck
3267 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3268
3269 layer mvnsc mvnscbase
3270 grow 85
3271 shrink 85
3272 shrink 85
3273 grow 85
3274 or mvnscbase
3275 labels CONT
3276
3277 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3278 or barecont
3279 and LI
3280 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3281 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3282 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3283 and NWELL,nwelcheck
3284 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3285
3286 layer mvpdc mvpdcbase
3287 grow 85
3288 shrink 85
3289 shrink 85
3290 grow 85
3291 or mvpdcbase
3292 labels CONT
3293
3294 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3295 or barecont
3296 and LI
3297 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3298 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3299 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3300 and mvpfetexpand
3301 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3302 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3303
3304 layer mvpdc mvpdcnowell
3305 grow 85
3306 shrink 85
3307 shrink 85
3308 grow 85
3309 or mvpdcnowell
3310 labels CONT
3311
3312 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3313 or barecont
3314 and LI
3315 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3316 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3317 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3318 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3319 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3320 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3321
3322 layer mvpsc mvpscbase
3323 grow 85
3324 shrink 85
3325 shrink 85
3326 grow 85
3327 or mvpscbase
3328 labels CONT
3329
3330 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3331 or barecont
3332 and LI
3333 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3334 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3335 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3336 and DIODE
3337 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3338 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3339 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3340 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3341
3342 layer mvndic mvndicbase
3343 grow 85
3344 shrink 85
3345 shrink 85
3346 grow 85
3347 or mvndicbase
3348 labels CONT
3349
3350 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3351 or barecont
3352 and LI
3353 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3354 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3355 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3356 and DIODE
3357 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3358 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3359 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3360 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3361
3362 layer nndic nndicbase
3363 grow 85
3364 shrink 85
3365 shrink 85
3366 grow 85
3367 or nndicbase
3368 labels CONT
3369
3370 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3371 or barecont
3372 and LI
3373 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3374 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3375 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3376 and DIODE
3377 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3378 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3379 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3380
3381 layer mvpdic mvpdicbase
3382 grow 85
3383 shrink 85
3384 shrink 85
3385 grow 85
3386 or mvpdicbase
3387 labels CONT
3388
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3389 layer fomfill FOMFILL
3390 labels FOMFILL
3391
3392 layer polyfill POLYFILL
3393 labels POLYFILL
3394
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3395 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3396 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3397 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3398 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3399 variants (vendor)
3400 labels LITXT port
3401 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3402 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3403 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3404 labels LIPIN port
3405
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3406 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3407 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3408 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3409 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3410 variants (vendor)
3411 labels LITXT port
3412 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3413 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3414 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3415 labels LIPIN port
3416
3417 layer rli LI
3418 and LIRES,LISHORT
3419 labels LIRES,LISHORT
3420
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3421 layer lifill LIFILL
3422 labels LIFILL
3423
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3424 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3425 grow 95
3426 shrink 95
3427 shrink 85
3428 grow 85
3429 or MCON
3430 labels MCON
3431
3432 layer m1 MET1,MET1TXT,MET1PIN
3433 and-not MET1RES,MET1SHORT
3434 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3435 variants (vendor)
3436 labels MET1TXT port
3437 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3438 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3439 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3440 labels MET1PIN port
3441
3442 layer rm1 MET1
3443 and MET1RES,MET1SHORT
3444 labels MET1RES,MET1SHORT
3445
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3446 layer m1fill MET1FILL
3447 labels MET1FILL
3448
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3449#ifdef MIM
3450 layer mimcap MET3
3451 and CAPM
3452 labels CAPM
3453
3454 layer mimcc VIA3
3455 and CAPM
3456 grow 60
3457 grow 40
3458 shrink 40
3459 labels CAPM
3460
3461 layer mimcap2 MET4
3462 and CAPM2
3463 labels CAPM2
3464
3465 layer mim2cc VIA4
3466 and CAPM2
3467 grow 190
3468 grow 210
3469 shrink 210
3470 labels CAPM2
3471
3472#endif (MIM)
3473
3474 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3475 and-not COREID
3476 grow 5
3477 or VIA1
3478 grow 50
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3479
3480 layer m2c m2cbase
3481 grow 30
3482 shrink 30
3483 shrink 130
3484 grow 130
3485 or m2cbase
3486
3487 layer m2 MET2,MET2TXT,MET2PIN
3488 and-not MET2RES,MET2SHORT
3489 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3490 variants (vendor)
3491 labels MET2TXT port
3492 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3493 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3494 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3495 labels MET2PIN port
3496
3497 layer rm2 MET2
3498 and MET2RES,MET2SHORT
3499 labels MET2RES,MET2SHORT
3500
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3501 layer m2fill MET2FILL
3502 labels MET2FILL
3503
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3504 templayer m3cbase VIA2
3505 grow 40
3506
3507 layer m3c m3cbase
3508 grow 60
3509 shrink 60
3510 shrink 140
3511 grow 140
3512 or m3cbase
3513
3514 layer m3 MET3,MET3TXT,MET3PIN
3515 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3516 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3517 variants (vendor)
3518 labels MET3TXT port
3519 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3520 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3521 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3522 labels MET3PIN port
3523
3524 layer rm3 MET3
3525 and MET3RES,MET3SHORT
3526 labels MET3RES,MET3SHORT
3527
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3528 layer m3fill MET3FILL
3529 labels MET3FILL
3530
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3531#ifdef (METAL5)
3532
3533 templayer via3base VIA3
3534#ifdef MIM
3535 and-not CAPM
3536#endif (MIM)
3537 grow 60
3538
3539 layer via3 via3base
3540 grow 40
3541 shrink 40
3542 shrink 160
3543 grow 160
3544 or via3base
3545
3546 layer m4 MET4,MET4TXT,MET4PIN
3547 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3548 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3549 variants (vendor)
3550 labels MET4TXT port
3551 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3552 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3553 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3554 labels MET4PIN port
3555
3556 layer rm4 MET4
3557 and MET4RES,MET4SHORT
3558 labels MET4RES,MET4SHORT
3559
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3560 layer m4fill MET4FILL
3561 labels MET4FILL
3562
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3563 layer m5 MET5,MET5TXT,MET5PIN
3564 and-not MET5RES,MET5SHORT
3565 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3566 variants (vendor)
3567 labels MET5TXT port
3568 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3569 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3570 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3571 labels MET5PIN port
3572
3573 layer rm5 MET5
3574 and MET5RES,MET5SHORT
3575 labels MET5RES,MET5SHORT
3576
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3577 layer m5fill MET5FILL
3578 labels MET5FILL
3579
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3580 templayer via4base VIA4
3581#ifdef MIM
3582 and-not CAPM2
3583#endif (MIM)
3584 grow 190
3585
3586 layer via4 via4base
3587 grow 210
3588 shrink 210
3589 shrink 590
3590 grow 590
3591 or via4base
3592#endif (METAL5)
3593
3594#ifdef REDISTRIBUTION
3595 layer metrdl RDL,RDLTXT,RDLPIN
3596 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3597 variants (vendor)
3598 labels RDLTXT port
3599 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3600 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3601 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3602 labels RDLPIN port
3603#endif
3604
3605 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3606 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3607 # the next layer up
3608
3609 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3610 and-not PSDM
3611 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3612 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3613 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3614
3615 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3616 and-not PSDM
3617 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3618 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3619 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3620 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3621
3622 # Handle contacts found by copyup
3623
3624 templayer ndiccopy CONT
3625 and LI
3626 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3627 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3628 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3629
3630 layer ndic ndiccopy
3631 grow 85
3632 shrink 85
3633 shrink 85
3634 grow 85
3635 or ndiccopy
3636 labels CONT
3637
3638 templayer mvndiccopy CONT
3639 and LI
3640 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3641 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3642 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3643
3644 layer mvndic mvndiccopy
3645 grow 85
3646 shrink 85
3647 shrink 85
3648 grow 85
3649 or mvndiccopy
3650 labels CONT
3651
3652 templayer pdiccopy CONT
3653 and LI
3654 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3655 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3656 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3657
3658 layer pdic pdiccopy
3659 grow 85
3660 shrink 85
3661 shrink 85
3662 grow 85
3663 or pdiccopy
3664 labels CONT
3665
3666 templayer mvpdiccopy CONT
3667 and LI
3668 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3669 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3670 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3671
3672 layer mvpdic mvpdiccopy
3673 grow 85
3674 shrink 85
3675 shrink 85
3676 grow 85
3677 or mvpdiccopy
3678 labels CONT
3679
3680 templayer ndccopy CONT
3681 and ndifcheck
3682
3683 layer ndc ndccopy
3684 grow 85
3685 shrink 85
3686 shrink 85
3687 grow 85
3688 or ndccopy
3689 labels CONT
3690
3691 templayer mvndccopy CONT
3692 and mvndifcheck
3693
3694 layer mvndc mvndccopy
3695 grow 85
3696 shrink 85
3697 shrink 85
3698 grow 85
3699 or mvndccopy
3700 labels CONT
3701
3702 templayer pdccopy CONT
3703 and pdifcheck
3704
3705 layer pdc pdccopy
3706 grow 85
3707 shrink 85
3708 shrink 85
3709 grow 85
3710 or pdccopy
3711 labels CONT
3712
3713 templayer mvpdccopy CONT
3714 and mvpdifcheck
3715
3716 layer mvpdc mvpdccopy
3717 grow 85
3718 shrink 85
3719 shrink 85
3720 grow 85
3721 or mvpdccopy
3722 labels CONT
3723
3724 templayer pccopy CONT
3725 and polycheck
3726
3727 layer pc pccopy
3728 grow 85
3729 shrink 85
3730 shrink 85
3731 grow 85
3732 or pccopy
3733 labels CONT
3734
3735 templayer nsccopy CONT
3736 and nsubcheck
3737
3738 layer nsc nsccopy
3739 grow 85
3740 shrink 85
3741 shrink 85
3742 grow 85
3743 or nsccopy
3744 labels CONT
3745
3746 templayer mvnsccopy CONT
3747 and mvnsubcheck
3748
3749 layer mvnsc mvnsccopy
3750 grow 85
3751 shrink 85
3752 shrink 85
3753 grow 85
3754 or mvnsccopy
3755 labels CONT
3756
3757 templayer psccopy CONT
3758 and psubcheck
3759
3760 layer psc psccopy
3761 grow 85
3762 shrink 85
3763 shrink 85
3764 grow 85
3765 or psccopy
3766 labels CONT
3767
3768 templayer mvpsccopy CONT
3769 and mvpsubcheck
3770
3771 layer mvpsc mvpsccopy
3772 grow 85
3773 shrink 85
3774 shrink 85
3775 grow 85
3776 or mvpsccopy
3777 labels CONT
3778
3779 # Find contacts not covered in
3780 # metal and pull them into the
3781 # next layer up
3782
3783 templayer gencont CONT
3784 and LI
3785 and-not DIFF,TAP
3786 and-not POLY
3787 and-not DIODE
3788 and-not nsubcheck
3789 and-not psubcheck
3790 and-not mvnsubcheck
3791 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3792 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3793 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3794
3795 templayer barecont CONT
3796 and-not LI
3797 and-not nsubcheck
3798 and-not psubcheck
3799 and-not mvnsubcheck
3800 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3801 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3802 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3803
3804 layer glass GLASS,PADTXT,PADPIN
3805 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3806 variants (vendor)
3807 labels PADTXT port
3808 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3809 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3810 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3811 labels PADPIN port
3812
3813 templayer boundary BOUND,STDCELL,PADCELL
3814 boundary
3815
3816 layer comment LVSTEXT
3817 labels LVSTEXT text
3818
3819 layer comment TTEXT
3820 labels TTEXT text
3821
3822 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3823 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3824
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3825 layer obsactive FILLOBSFOM
3826
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3827# MOS Varactor
3828
3829 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3830 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3831 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3832 and NWELL,nwelcheck
3833 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3834 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3835 # NOTE: Else forms a varactor that is not in the vendor netlist.
3836 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3837 labels POLY
3838
3839 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3840 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3841 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3842 and NWELL,nwelcheck
3843 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3844 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3845 labels POLY
3846
3847 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3848 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3849 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3850 and NWELL,nwelcheck
3851 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3852 labels POLY
3853
3854 calma NWELL 64 20
3855 calma DIFF 65 20
3856 calma DNWELL 64 18
3857 calma PWRES 64 13
3858 calma TAP 65 44
3859 # LVTN
3860 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3861 # HVTR
3862 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3863 # HVTP
3864 calma HVTP 78 44
3865 # SONOS (TUNM)
3866 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3867 # NSDM (NPLUS)
3868 calma NSDM 93 44
3869 # PSDM (PPLUS)
3870 calma PSDM 94 20
3871 # HVI (THKOX)
3872 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3873 # NPC
3874 calma NPC 95 20
3875 # P+ POLY MASK
3876 calma RPM 86 20
3877 calma URPM 79 20
3878 calma LDNTM 11 44
3879 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3880 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3881 calma POLYRES 66 13
3882 # Diffusion resistor ID mark
3883 calma DIFFRES 65 13
3884 calma POLY 66 20
3885 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]3886 # 3.3V native FET ID mark
3887 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3888 # Diode ID mark
3889 calma DIODE 81 23
3890 # Bipolar NPN mark
3891 calma NPNID 82 20
3892 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3893 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3894 # Capacitor ID
3895 calma CAPID 82 64
3896 # Core area ID mark
3897 calma COREID 81 2
3898 # Standard cell ID mark
3899 calma STDCELL 81 4
3900 # Padframe cell ID mark
3901 calma PADCELL 81 3
3902 # Seal ring ID mark
3903 calma SEALID 81 1
3904 # Low tap density ID mark
3905 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3906 # ESD area ID
3907 calma ESDID 81 19
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]3908 calma OUTLINE 236 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3909
3910 # LICON
3911 calma CONT 66 44
3912 calma LI 67 20
3913 calma MCON 67 44
3914
3915 calma MET1 68 20
3916 calma VIA1 68 44
3917 calma MET2 69 20
3918 calma VIA2 69 44
3919 calma MET3 70 20
3920#ifdef METAL5
3921 calma VIA3 70 44
3922 calma MET4 71 20
3923 calma VIA4 71 44
3924 calma MET5 72 20
3925#endif
3926#ifdef REDISTRIBUTION
3927 calma RDL 74 20
3928#endif
3929 calma GLASS 76 20
3930
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3931 calma SUBTXT 64 59
3932 calma PADTXT 76 5
3933 calma DIFFTXT 65 6
3934 calma TAPTXT 65 5
3935 calma WELLTXT 64 5
3936 calma LITXT 67 5
3937 calma POLYTXT 66 5
3938 calma MET1TXT 68 5
3939 calma MET2TXT 69 5
3940 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3941#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3942 calma MET4TXT 71 5
3943 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3944#endif
3945#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3946 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3947#endif
3948
3949 calma LIRES 67 13
3950 calma MET1RES 68 13
3951 calma MET2RES 69 13
3952 calma MET3RES 70 13
3953#ifdef METAL5
3954 calma MET4RES 71 13
3955 calma MET5RES 72 13
3956#endif
3957
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3958 calma LIFILL 56 28
3959 calma MET1FILL 36 28
3960 calma MET2FILL 41 28
3961 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3962#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3963 calma MET4FILL 51 28
3964 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3965#endif
3966
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3967 calma POLYSHORT 66 15
3968 calma LISHORT 67 15
3969 calma MET1SHORT 68 15
3970 calma MET2SHORT 69 15
3971 calma MET3SHORT 70 15
3972#ifdef METAL5
3973 calma MET4SHORT 71 15
3974 calma MET5SHORT 72 15
3975#endif
3976
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3977 calma SUBPIN 122 16
3978 calma PADPIN 76 16
3979 calma DIFFPIN 65 16
3980 calma POLYPIN 66 16
3981 calma WELLPIN 64 16
3982 calma LIPIN 67 16
3983 calma MET1PIN 68 16
3984 calma MET2PIN 69 16
3985 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3986#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3987 calma MET4PIN 71 16
3988 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3989#endif
3990#ifdef REDISTRIBUTION
3991 calma RDLPIN 74 16
3992#endif
3993
3994 calma BOUND 235 4
3995
3996 calma LVSTEXT 83 44
3997
3998#ifdef (MIM)
3999 calma CAPM 89 44
4000 calma CAPM2 97 44
4001#endif (MIM)
4002
4003 calma FILLOBSM1 62 24
4004 calma FILLOBSM2 105 52
4005 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]4006 calma FILLOBSM4 112 4
4007 calma FILLOBSFOM 22 24
4008 calma FILLOBSPOLY 33 24
4009
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4010 calma FOMFILL 23 28
4011 calma POLYFILL 28 28
4012 calma LIFILL 56 28
4013 calma MET1FILL 36 28
4014 calma MET2FILL 41 28
4015 calma MET3FILL 34 28
4016 calma MET4FILL 51 28
4017 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4018
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4019#-----------------------------------------------------------------------
4020
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4021style rdlimport
4022 # This style is for reading shapes generated with the RDL layers
4023
4024 scalefactor 10 nanometers
4025 gridlimit 5
4026
4027 options ignore-unknown-layer-labels no-reconnect-labels
4028
4029 layer mrdl RDL
4030 layer mrdlc RDLC
4031
4032 calma RDL 10 0
4033 calma RDLC 20 0
4034
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4035end
4036
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4037#-----------------------------------------------------
4038# Digital flow maze router cost parameters
4039#-----------------------------------------------------
4040
4041mzrouter
4042end
4043
4044#-----------------------------------------------------
4045# Vendor DRC rules
4046#-----------------------------------------------------
4047
4048drc
4049
4050 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4051 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4052 cifstyle drc
4053
4054 variants (fast),(full)
4055
4056#-----------------------------
4057# DNWELL
4058#-----------------------------
4059
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4060 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4061 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4062 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4063 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4064
4065 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4066 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4067 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4068 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4069 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4070
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4071 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4072 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4073 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4074
4075#-----------------------------
4076# NWELL
4077#-----------------------------
4078
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4079 width allnwell 840 "N-well width < %d (nwell.1)"
4080 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4081
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4082 variants (full)
4083 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4084 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4085
4086 cifspacing mvnwell lvnwell 2000 touching_illegal \
4087 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4088 cifspacing mvnwell mvnwell 2000 touching_ok \
4089 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4090 variants (fast),(full)
4091
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4092#-----------------------------
4093# DIFF
4094#-----------------------------
4095
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4096 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4097 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4098 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4099 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4100
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4101 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4102 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4103 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4104 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4105 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4106 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4107 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4108 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4109 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4110 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4111 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4112 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4113 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4114 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4115 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4116 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4117 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4118 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4119 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4120 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4121 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4122 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4123 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4124 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4125 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4126 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4127 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4128 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4129 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4130 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4131 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4132 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4133 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4134 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4135 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4136 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4137
4138variants (full)
4139 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4140 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
4141variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4142
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4143 spacing allnfets allpactivenonfet 270 touching_illegal \
4144 "nFET cannot abut P-diffusion (diff/tap.3)"
4145 spacing allpfets allnactivenonfet 270 touching_illegal \
4146 "pFET cannot abut N-diffusion (diff/tap.3)"
4147
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4148 # Butting junction rules
4149 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4150 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4151 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4152 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4153 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4154 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4155 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4156 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4157
4158 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4159 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4160 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4161 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4162 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4163 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4164 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4165 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4166
4167 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4168 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4169 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4170
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4171 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4172 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4173
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4174 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4175
4176 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4177 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4178
4179 # Latchup rules
4180 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4181 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4182 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4183 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4184 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4185 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4186
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4187 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4188
4189#-----------------------------
4190# POLY
4191#-----------------------------
4192
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4193 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4194 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4195
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4196 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4197 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4198 75 corner_ok allfets \
4199 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4200 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4201 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4202 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4203 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4204 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4205 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4206 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4207 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4208 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4209 rect_only allfets "No bends in transistors (poly.11)"
4210 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4211 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4212 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4213 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4214 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4215
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4216 variants (fast)
4217
4218 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4219 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4220 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4221 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4222 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4223 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4224
4225 # Minimum width requirement means actual spacing from res to ndiff has to be
4226 # constructed from mask rules. These supercede the simpler checks.
4227
4228 variants (full)
4229
4230 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4231 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4232 cifmaxwidth rpm_poly_check 0 bend_illegal \
4233 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4234 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4235 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4236
Tim Edwards75dea452021-05-08 15:55:26 -0400[diff] [blame]4237 variants (fast),(full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4238
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4239 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4240
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4241#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4242# HVTP
4243#--------------------------------------------------------------------
4244
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4245 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4246 360 touching_illegal \
4247 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4248
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4249 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4250 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4251
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4252#--------------------------------------------------------------------
4253# LVTN
4254#--------------------------------------------------------------------
4255
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4256 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4257 allfetsnolvt 360 touching_illegal \
4258 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4259
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4260 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4261 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4262 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4263
4264 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4265 edge4way allfetsnolvt allactivenonfet 415 \
4266 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4267 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4268
4269#--------------------------------------------------------------------
4270# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4271#--------------------------------------------------------------------
4272
4273# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4274
4275#--------------------------------------------------------------------
4276# CONT (LICON, contact between poly/diff and LI)
4277#--------------------------------------------------------------------
4278
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4279 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4280 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4281 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4282 width psc/li 170 "P-tap contact width < %d (licon.1)"
4283 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4284 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4285 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4286
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4287 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4288 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4289 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4290
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4291 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4292 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4293 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4294 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4295 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4296 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4297
4298 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4299 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4300 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4301 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4302 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4303 "Diffusion contact spacing < %d (licon.2)"
4304 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4305
4306 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4307 "poly contact spacing to diffusion < %d (licon.14)"
4308 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4309 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4310
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4311 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4312 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4313 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4314 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4315 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4316 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4317 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4318 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4319 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4320 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4321 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4322 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4323
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4324 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4325 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4326 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4327 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4328 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4329 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4330 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4331 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4332 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4333
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4334 spacing psc/a allnactivenontap 60 touching_illegal \
4335 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4336 spacing nsc/a allpactivenontap 60 touching_illegal \
4337 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4338
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4339 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4340 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4341 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4342 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4343 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4344 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4345 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4346 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4347 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4348
4349 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4350 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4351 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4352 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4353
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4354 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4355 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4356 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4357 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4358 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4359 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4360 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4361 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4362
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4363 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4364 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4365 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4366 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4367
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4368 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4369 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4370 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4371 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4372 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4373 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4374 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4375 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4376
4377 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4378 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4379 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4380 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4381
4382 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4383 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4384 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4385 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4386
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4387 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4388
4389#-------------------------------------------------------------
4390# LI - Local interconnect layer
4391#-------------------------------------------------------------
4392
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4393variants *
4394
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4395 width *li 170 "Local interconnect width < %d (li.1)"
4396 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4397
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4398 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4399 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4400
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4401 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4402 # no special layers for the contacts in core cells, so they must be included
4403 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4404 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4405 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4406
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4407 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4408 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4409
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4410 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4411 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4412
4413 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4414 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4415 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4416
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4417 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4418
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4419 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4420 angles coreli 45 \
4421 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4422
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4423#-------------------------------------------------------------
4424# MCON - Contact between local interconnect and metal1
4425#-------------------------------------------------------------
4426
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4427 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4428 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4429
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4430 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4431
4432#-------------------------------------------------------------
4433# METAL1 -
4434#-------------------------------------------------------------
4435
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4436 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4437 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4438 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4439
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4440 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4441 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4442 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4443 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4444
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4445 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4446
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4447variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4448 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4449 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4450 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4451 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4452
4453variants (full)
4454 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4455 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4456
4457 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4458 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4459variants *
4460
4461#--------------------------------------------------
4462# VIA1
4463#--------------------------------------------------
4464
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4465 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4466 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4467 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4468 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4469 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4470 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4471
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4472 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4473
4474#--------------------------------------------------
4475# METAL2 -
4476#--------------------------------------------------
4477
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4478 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4479 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4480 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4481
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4482 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4483
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4484variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4485 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4486 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4487 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4488 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4489
4490variants (full)
4491 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4492 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4493
4494 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4495 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4496variants *
4497
4498#--------------------------------------------------
4499# VIA2
4500#--------------------------------------------------
4501
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4502 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4503
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4504 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4505
4506 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4507 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4508 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4509
4510 exact_overlap v2/m2
4511
4512#--------------------------------------------------
4513# METAL3 -
4514#--------------------------------------------------
4515
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4516 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4517 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4518 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4519
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4520 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4521
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4522variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4523 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4524 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4525 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4526 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4527variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4528 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4529 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4530variants *
4531
4532
4533#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4534#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4535#--------------------------------------------------
4536# VIA3 - Requires METAL5 Module
4537#--------------------------------------------------
4538
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4539 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4540 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4541 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4542 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4543 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4544 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4545
4546 exact_overlap v3/m3
4547
4548#-----------------------------
4549# METAL4 - METAL4 Module
4550#-----------------------------
4551
4552variants *
4553
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4554 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4555 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4556 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4557
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4558 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4559
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4560variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4561 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4562 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4563 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4564 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4565variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4566 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4567 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4568variants *
4569
4570#--------------------------------------------------
4571# VIA4 - Requires METAL5 Module
4572#--------------------------------------------------
4573
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4574 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4575 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4576 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4577 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4578
4579 exact_overlap v4/m4
4580
4581#-----------------------------
4582# METAL5 - METAL5 Module
4583#-----------------------------
4584
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4585 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4586 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4587 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4588
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4589 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4590
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4591#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4592#endif (METAL5)
4593
4594#ifdef REDISTRIBUTION
4595
4596variants (full)
4597
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4598 width metrdl 10000 "RDL width < %d (rdl.1)"
4599 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4600 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4601 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4602
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4603variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4604
4605#endif (REDISTRIBUTION)
4606
4607#--------------------------------------------------
4608# NMOS, PMOS
4609#--------------------------------------------------
4610
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4611 edge4way *poly allfetsstd 420 allfets 0 0 \
4612 "Transistor width < %d (diff/tap.2)"
4613 edge4way *poly allfetsspecial 360 allfets 0 0 \
4614 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4615 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4616 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4617 edge4way *poly ppu 140 allfets 0 0 \
4618 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4619
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4620 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4621 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4622
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4623 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4624 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4625 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4626 "poly spacing to diffusion tap < %d (poly.5)"
4627 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4628 "poly spacing to diffusion tap < %d (poly.5)"
4629 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4630 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4631
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4632 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4633 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4634 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4635 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4636 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4637 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4638 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4639 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4640
4641 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4642 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4643 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4644
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4645 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4646 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4647
4648 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4649 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4650 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4651
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4652 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4653 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4654
4655 # Minimum length of MV FETs. Note that this is larger than the minimum
4656 # width (0.29um), so an edge rule is required
4657
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4658 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4659 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4660
4661 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4662 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4663
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4664 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4665 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4666
4667#--------------------------------------------------
4668# mrp1 (N+ poly resistor)
4669#--------------------------------------------------
4670
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4671 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4672
4673#--------------------------------------------------
4674# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4675# uhrpoly (P+ poly resistor, 2kOhm/sq)
4676#--------------------------------------------------
4677
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4678 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4679 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4680 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4681
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4682 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4683 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4684
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4685 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4686 "Poly resistor spacing to poly < %d (poly.9)"
4687
4688 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4689 "Poly resistor spacing to poly < %d (poly.9)"
4690
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4691 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4692 "Poly resistor spacing to poly < %d (poly.9)"
4693
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4694 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4695 "Poly resistor spacing to diffusion < %d (poly.9)"
4696
4697#------------------------------------
4698# nsonos
4699#------------------------------------
4700
4701variants (full)
4702 cifmaxwidth bbox_missing 0 bend_illegal \
4703 "SONOS transistor must be in cell with abutment box (tunm.8)"
4704variants (fast),(full)
4705
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4706#------------------------------------
4707# MOS Varactor device rules
4708#------------------------------------
4709
4710 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4711 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4712
4713 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4714 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4715
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4716 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4717 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4718
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4719variants (full)
4720 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4721 "N-well overlap of varactor poly < 0.15um (varac.5)"
4722
4723 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4724 "Varactor N-well must not contain P+ diffusion (varac.7)"
4725variants (fast),(full)
4726
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4727#ifdef MIM
4728#-----------------------------------------------------------
4729# MiM CAP (CAPM) -
4730#-----------------------------------------------------------
4731
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4732 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4733 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4734 spacing *mimcap via3/m3 80 touching_illegal \
4735 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4736 surround *mimcc *mimcap 80 absence_illegal \
4737 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4738 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4739
4740 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4741 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4742 spacing via2 *mimcap 100 touching_illegal \
4743 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4744 spacing *mimcap *metal3/m3 500 surround_ok \
4745 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4746
4747variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4748 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4749 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4750variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4751
4752 # MiM cap contact rules (VIA3)
4753
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4754 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4755 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4756 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4757 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4758 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4759
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4760 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4761 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4762 spacing *mimcap2 via4/m4 10 touching_illegal \
4763 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4764 surround *mim2cc *mimcap2 10 absence_illegal \
4765 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4766 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4767
4768 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4769 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4770 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4771 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4772 spacing *mimcap2 *metal4/m4 500 surround_ok \
4773 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4774
4775variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4776 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4777 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4778variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4779
4780 # MiM cap contact rules (VIA4)
4781
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4782 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4783 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4784 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4785 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4786 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4787 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4788
4789#endif (MIM)
4790
4791#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4792# HVNTM
4793#----------------------------
4794variants (full)
4795 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4796 "HVNTM spacing < %d (hvntm.2)"
4797variants (fast),(full)
4798
4799#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4800# End DRC style
4801#----------------------------
4802
4803end
4804
4805#----------------------------
4806# LEF format definitions
4807#----------------------------
4808
4809lef
4810
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4811 masterslice pwell pwell PWELL substrate
4812 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4813
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4814 routing li li1 LI1 LI li
4815
4816 routing m1 met1 MET1 m1
4817 routing m2 met2 MET2 m2
4818 routing m3 met3 MET3 m3
4819#ifdef METAL5
4820 routing m4 met4 MET4 m4
4821 routing m5 met5 MET5 m5
4822#endif (METAL5)
4823#ifdef REDISTRIBUTION
4824 routing mrdl met6 MET6 m6 MRDL METRDL
4825#endif
4826
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4827 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4828 cut m2c via via1 VIA VIA1 cont2 via12
4829 cut m3c via2 VIA2 cont3 via23
4830#ifdef METAL5
4831 cut via3 via3 VIA3 cont4 via34
4832 cut via4 via4 VIA4 cont5 via45
4833#endif (METAL5)
4834
4835 obs obsli li1
4836 obs obsm1 met1
4837 obs obsm2 met2
4838 obs obsm3 met3
4839
4840#ifdef METAL5
4841 obs obsm4 met4
4842 obs obsm5 met5
4843#endif (METAL5)
4844#ifdef REDISTRIBUTION
4845 obs obsmrdl met6
4846#endif
4847
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4848 # NOTE: obsmcon only used with li1, not obsli.
4849 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4850
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4851 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4852 obs obsm1 via
4853 obs obsm2 via2
4854#ifdef METAL5
4855 obs obsm3 via3
4856 obs obsm4 via4
4857#endif (METAL5)
4858
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4859end
4860
4861#-----------------------------------------------------
4862# Device and Parasitic extraction
4863#-----------------------------------------------------
4864
4865
4866extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4867 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4868 cscale 1
4869 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4870 # dimensions must be in units of microns in the extract file.
4871 # Use extract style "ngspice(si)" to override this and produce
4872 # a file with SI units for length/area.
4873
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4874 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4875 lambda 1E6
4876 variants (si)
4877 lambda 1.0
4878 variants *
4879
4880 units microns
4881 step 7
4882 sidehalo 2
4883
4884 # NOTE: MiM cap layers have been purposely put out of order,
4885 # may want to reconsider.
4886
4887 planeorder dwell 0
4888 planeorder well 1
4889 planeorder active 2
4890 planeorder locali 3
4891 planeorder metal1 4
4892 planeorder metal2 5
4893 planeorder metal3 6
4894#ifdef METAL5
4895 planeorder metal4 7
4896 planeorder metal5 8
4897#ifdef REDISTRIBUTION
4898 planeorder metali 9
4899 planeorder block 10
4900 planeorder comment 11
4901 planeorder cap1 12
4902 planeorder cap2 13
4903#else (!REDISTRIBUTION)
4904 planeorder block 9
4905 planeorder comment 10
4906 planeorder cap1 11
4907 planeorder cap2 12
4908#endif (!REDISTRIBUTION)
4909#else (!METAL5)
4910#ifdef REDISTRIBUTION
4911 planeorder metali 7
4912 planeorder block 8
4913 planeorder comment 9
4914 planeorder cap1 10
4915 planeorder cap2 11
4916#else (!REDISTRIBUTION)
4917 planeorder block 7
4918 planeorder comment 8
4919 planeorder cap1 9
4920 planeorder cap2 10
4921#endif (!REDISTRIBUTION)
4922#endif (!METAL5)
4923
4924 height dnwell -0.1 0.1
4925 height nwell,pwell 0.0 0.2062
4926 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4927 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4928 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4929 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4930 height alldiffcont 0.3262 0.61
4931 height pc 0.5062 0.43
4932 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4933 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4934 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4935 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4936 height v1 1.7361 0.27
4937 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4938 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4939 height v2 2.3661 0.42
4940 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4941 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4942#ifdef METAL5
4943 height v3 3.6311 0.39
4944 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4945 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4946 height v4 4.8661 0.505
4947 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4948 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4949 height mimcap 2.4661 0.2
4950 height mimcap2 3.7311 0.2
4951 height mimcc 2.6661 0.12
4952 height mim2cc 3.9311 0.09
4953#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]4954 height mrdlc 6.6311 0.63
4955 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4956#endif (!REDISTRIBUTION)
4957#endif (!METAL5)
4958
4959 # Antenna check parameters
4960 # Note that checks w/diode diffusion are not modeled
4961 model partial
4962 antenna poly sidewall 50 none
4963 antenna allcont surface 3 none
4964 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4965 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4966 antenna m1,m2,m3 sidewall 400 2600 400
4967 antenna v1 surface 3 0 18
4968 antenna v2 surface 6 0 36
4969#ifdef METAL5
4970 antenna m4,m5 sidewall 400 2600 400
4971 antenna v3,v4 surface 6 0 36
4972#endif (METAL5)
4973
4974 tiedown alldiffnonfet
4975
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]4976 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4977
4978# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4979
4980# Resistances are in milliohms per square
4981# Optional 3rd argument is the corner adjustment fraction
4982# Device values come from trtc.cor (typical corner)
4983 resist (dnwell)/dwell 2200000
4984 resist (pwell)/well 3050000
4985 resist (nwell)/well 1700000
4986 resist (rpw)/well 3050000 0.5
4987 resist (*ndiff,nsd)/active 120000
4988 resist (*pdiff,*psd)/active 197000
4989 resist (*mvndiff,mvnsd)/active 114000
4990 resist (*mvpdiff,*mvpsd)/active 191000
4991
4992 resist ndiffres/active 120000 0.5
4993 resist pdiffres/active 197000 0.5
4994 resist mvndiffres/active 114000 0.5
4995 resist mvpdiffres/active 191000 0.5
4996 resist mrp1/active 48200 0.5
4997 resist xhrpoly/active 319800 0.5
4998 resist uhrpoly/active 2000000 0.5
4999
5000 resist (allpolynonres)/active 48200
5001 resist rmp/active 48200
5002
5003 resist (allli)/locali 12200
5004 resist (allm1)/metal1 125
5005 resist (allm2)/metal2 125
5006 resist (allm3)/metal3 47
5007#ifdef METAL5
5008 resist (allm4)/metal4 47
5009 resist (allm5)/metal5 29
5010#endif (METAL5)
5011#ifdef REDISTRIBUTION
5012 resist mrdl/metali 5
5013#endif (REDISTRIBUTION)
5014
5015 contact ndc,nsc 15000
5016 contact pdc,psc 15000
5017 contact mvndc,mvnsc 15000
5018 contact mvpdc,mvpsc 15000
5019 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5020 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5021 contact m2c 4500
5022 contact m3c 3410
5023#ifdef METAL5
5024#ifdef MIM
5025 contact mimcc 4500
5026 contact mim2cc 3410
5027#endif (MIM)
5028 contact via3 3410
5029 contact via4 380
5030#endif (METAL5)
5031#ifdef REDISTRIBUTION
5032 contact mrdlc 6
5033#endif (REDISTRIBUTION)
5034
5035#-------------------------------------------------------------------------
5036# Parasitic capacitance values: Use document (...)
5037#-------------------------------------------------------------------------
5038# This uses the new "default" definitions that determine the intervening
5039# planes from the planeorder stack, take care of the reflexive sideoverlap
5040# definitions, and generally clean up the section and make it more readable.
5041#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5042# Also uses "units microns" statement. All values are taken from the
5043# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5044# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5045#-------------------------------------------------------------------------
5046# Remember that device capacitances to substrate are taken care of by the
5047# models. Thus, active and poly definitions ignore all "fet" types.
5048# fet types are excluded when computing parasitic capacitance to
5049# active from layers above them because poly is a shield; fet types are
5050# included for parasitics from layers above to poly. Resistor types
5051# should be removed from all parasitic capacitance calculations, or else
5052# they just create floating caps. Technically, the capacitance probably
5053# should be split between the two terminals. Unsure of the correct model.
5054#-------------------------------------------------------------------------
5055
5056#n-well
5057# NOTE: This value not found in PEX files
5058defaultareacap nwell well 120
5059
5060#n-active
5061# Rely on device models to capture *ndiff area cap
5062# Do not extract parasitics from resistors
5063# defaultareacap allnactivenonfet active 790
5064# defaultperimeter allnactivenonfet active 280
5065
5066#p-active
5067# Rely on device models to capture *pdiff area cap
5068# Do not extract parasitics from resistors
5069# defaultareacap allpactivenonfet active 810
5070# defaultperimeter allpactivenonfet active 300
5071
5072#poly
5073# Do not extract parasitics from resistors
5074# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5075# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5076# defaultperimeter allpolynonfet active 57
5077
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5078 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5079 defaultareacap *poly active nwell,obswell,pwell well 106
5080 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5081
5082#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5083 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5084 defaultareacap allli locali nwell,obswell,pwell well 37
5085 defaultperimeter allli locali nwell,obswell,pwell well 55
5086 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5087
5088#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5089 defaultoverlap allli locali allactivenonfet active 37
5090 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5091
5092#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5093 defaultoverlap allli locali allpolynonres active 94
5094 defaultsideoverlap allli locali allpolynonres active 52
5095 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5096
5097#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5098 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5099 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5100 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5101 defaultoverlap allm1 metal1 nwell well 26
5102
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5103#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5104 defaultoverlap allm1 metal1 allactivenonfet active 26
5105 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5106
5107#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5108 defaultoverlap allm1 metal1 allpolynonres active 45
5109 defaultsideoverlap allm1 metal1 allpolynonres active 47
5110 defaultsideoverlap *poly active allm1 metal1 17
5111
5112#metal1->locali
5113 defaultoverlap allm1 metal1 allli locali 114
5114 defaultsideoverlap allm1 metal1 allli locali 59
5115 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5116
5117#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5118 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5119 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5120 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5121 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5122
5123#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5124 defaultoverlap allm2 metal2 allactivenonfet active 17
5125 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5126
5127#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5128 defaultoverlap allm2 metal2 allpolynonres active 24
5129 defaultsideoverlap allm2 metal2 allpolynonres active 41
5130 defaultsideoverlap *poly active allm2 metal2 11
5131
5132#metal2->locali
5133 defaultoverlap allm2 metal2 allli locali 38
5134 defaultsideoverlap allm2 metal2 allli locali 46
5135 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5136
5137#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5138 defaultoverlap allm2 metal2 allm1 metal1 134
5139 defaultsideoverlap allm2 metal2 allm1 metal1 67
5140 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5141
5142#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5143 defaultsidewall allm3 metal3 63
5144 defaultoverlap allm3 metal3 nwell well 12
5145 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5146 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5147
5148#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5149 defaultoverlap allm3 metal3 allactive active 12
5150 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5151
5152#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5153 defaultoverlap allm3 metal3 allpolynonres active 16
5154 defaultsideoverlap allm3 metal3 allpolynonres active 44
5155 defaultsideoverlap *poly active allm3 metal3 9
5156
5157#metal3->locali
5158 defaultoverlap allm3 metal3 allli locali 21
5159 defaultsideoverlap allm3 metal3 allli locali 47
5160 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5161
5162#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5163 defaultoverlap allm3 metal3 allm1 metal1 35
5164 defaultsideoverlap allm3 metal3 allm1 metal1 55
5165 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5166
5167#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5168 defaultoverlap allm3 metal3 allm2 metal2 86
5169 defaultsideoverlap allm3 metal3 allm2 metal2 70
5170 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5171
5172#ifdef METAL5
5173#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5174 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5175# defaultareacap alltopm metal4 well 6
5176 areacap allm4/m4 8
5177 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5178 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5179
5180#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5181 defaultoverlap allm4 metal4 allactivenonfet active 8
5182 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5183
5184#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5185 defaultoverlap allm4 metal4 allpolynonres active 10
5186 defaultsideoverlap allm4 metal4 allpolynonres active 38
5187 defaultsideoverlap *poly active allm4 metal4 6
5188
5189#metal4->locali
5190 defaultoverlap allm4 metal4 allli locali 12
5191 defaultsideoverlap allm4 metal4 allli locali 40
5192 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5193
5194#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5195 defaultoverlap allm4 metal4 allm1 metal1 15
5196 defaultsideoverlap allm4 metal4 allm1 metal1 43
5197 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5198
5199#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5200 defaultoverlap allm4 metal4 allm2 metal2 20
5201 defaultsideoverlap allm4 metal4 allm2 metal2 46
5202 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5203
5204#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5205 defaultoverlap allm4 metal4 allm3 metal3 84
5206 defaultsideoverlap allm4 metal4 allm3 metal3 71
5207 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5208
5209#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5210 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5211# defaultareacap allm5 metal5 well 6
5212 areacap allm5/m5 6
5213 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5214 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5215
5216#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5217 defaultoverlap allm5 metal5 allactivenonfet active 6
5218 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5219
5220#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5221 defaultoverlap allm5 metal5 allpolynonres active 7
5222 defaultsideoverlap allm5 metal5 allpolynonres active 40
5223 defaultsideoverlap *poly active allm5 metal5 6
5224
5225#metal5->locali
5226 defaultoverlap allm5 metal5 allli locali 8
5227 defaultsideoverlap allm5 metal5 allli locali 41
5228 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5229
5230#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5231 defaultoverlap allm5 metal5 allm1 metal1 9
5232 defaultsideoverlap allm5 metal5 allm1 metal1 43
5233 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5234
5235#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5236 defaultoverlap allm5 metal5 allm2 metal2 11
5237 defaultsideoverlap allm5 metal5 allm2 metal2 46
5238 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5239
5240#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5241 defaultoverlap allm5 metal5 allm3 metal3 20
5242 defaultsideoverlap allm5 metal5 allm3 metal3 54
5243 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5244
5245#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5246 defaultoverlap allm5 metal5 allm4 metal4 68
5247 defaultsideoverlap allm5 metal5 allm4 metal4 83
5248 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5249#endif (METAL5)
5250
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5251#ifdef REDISTRIBUTION
5252#endif (REDISTRIBUTION)
5253
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5254# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5255
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5256variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5257
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5258 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5259 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5260 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5261 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5262 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5263 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5264 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5265 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5266 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5267 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5268 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5269 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5270 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5271 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5272 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5273
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5274 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5275 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5276 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5277 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5278 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5279 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5280 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5281 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5282 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5283 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5284 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5285 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5286 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5287 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5288 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5289 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5290 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5291 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5292 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5293 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5294 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5295 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5296 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5297 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5298
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5299 # Bipolars
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]5300 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
5301 error +npn1p00
5302 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
5303 error +npn2p00
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]5304 device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]5305 device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
5306 pwell,space/w +pnp0p68
5307 device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
5308 pwell,space/w +pnp3p40
5309 device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
5310 dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5311 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5312
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5313 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5314 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5315 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5316 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5317
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5318 # Extended drain devices (must appear before the regular devices)
5319 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5320 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5321 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5322 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5323 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5324 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5325
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5326 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5327 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5328 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5329 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5330 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5331 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5332 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5333 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5334 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5335 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5336 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5337 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5338 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5339 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5340 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5341 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5342 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5343 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5344
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5345 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5346 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5347 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5348 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5349#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5350 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5351 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5352#endif (METAL5)
5353
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5354 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5355 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5356 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5357 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5358 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5359 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5360 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5361 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5362 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5363 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5364 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5365 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5366 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5367 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5368 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5369 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5370 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5371 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5372 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5373 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5374 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5375 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5376 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5377 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5378
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5379 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5380 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5381 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5382 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5383 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5384 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5385 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5386 *mvndiff pwell,space/w error l=l w=w
5387 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5388 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5389
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5390 device resistor sky130_fd_pr__res_generic_po rmp *poly
5391 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5392
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5393 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
5394 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
5395 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
5396 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5397
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5398 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
5399 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
5400 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
5401 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5402
5403#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5404 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5405 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5406#endif (MIM)
5407
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5408 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5409
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5410 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5411 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5412 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5413 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5414 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5415 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5416 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5417 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5418 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5419 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5420 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5421 pwell,space/w
5422
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5423 # Note that corenvar, corepvar are not considered devices, and extract as
5424 # parasitic capacitance instead (but cap values need to be added).
5425
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5426 # Extended drain devices (must appear before the regular devices)
5427 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5428 dnwell pwell,space/w error
5429 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5430 dnwell pwell,space/w error
5431 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5432 pwell,space/w nwell error
5433
5434 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5435 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5436 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5437 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5438 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5439 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5440
5441 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5442 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5443 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5444 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5445
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5446 device resistor sky130_fd_pr__res_generic_po rmp *poly
5447 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5448 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5449 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5450 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5451#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5452 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5453 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5454#endif (METAL5)
5455
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5456 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5457 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5458 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5459 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5460 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5461 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5462 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5463 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5464 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5465 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5466 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5467 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5468 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5469 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5470 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5471 device resistor mrdn_hv mvndiffres *mvndiff
5472 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5473 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5474
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5475 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5476 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5477 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5478 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5479
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5480 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5481 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5482 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5483 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5484
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]5485 device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
5486 device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5487 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]5488 device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
5489 device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5490 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame^]5491 device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5492 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5493
5494#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5495 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5496 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5497#endif (MIM)
5498
5499end
5500
5501#-----------------------------------------------------
5502# Wiring tool definitions
5503#-----------------------------------------------------
5504
5505wiring
5506 # All wiring values are in nanometers
5507 scalefactor 10
5508
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5509 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5510 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5511 contact v2 280 m2 0 45 m3 25 0
5512#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5513 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5514 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5515#endif (METAL5)
5516
5517 contact pc 170 poly 50 80 li 0 80
5518 contact pdc 170 pdiff 40 60 li 0 80
5519 contact ndc 170 ndiff 40 60 li 0 80
5520 contact psc 170 psd 40 60 li 0 80
5521 contact nsc 170 nsd 40 60 li 0 80
5522
5523end
5524
5525#-----------------------------------------------------
5526# Plain old router. . .
5527#-----------------------------------------------------
5528
5529router
5530end
5531
5532#------------------------------------------------------------
5533# Plowing (restored in magic 8.2, need to fill this section)
5534#------------------------------------------------------------
5535
5536plowing
5537end
5538
5539#-----------------------------------------------------------------
5540# No special plot layers defined (use default PNM color choices)
5541#-----------------------------------------------------------------
5542
5543plot
5544 style pnm
5545 default
5546 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5547 draw fillblock4 no_color_at_all
5548 draw fomfill no_color_at_all
5549 draw polyfill no_color_at_all
5550 draw m1fill no_color_at_all
5551 draw m2fill no_color_at_all
5552 draw m3fill no_color_at_all
5553 draw m4fill no_color_at_all
5554 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5555 draw nwell cwell
5556end
5557