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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / acba7d8c31a35efbcc33bf7928b0b883613c45da / . / sky130 / magic / sky130.tech
blob: b5546bf1d9db50e298d6b68191a0c9731090d89d [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]66# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v5 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]144 dwell isosubstrate,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]163 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]167 -active mvnmosesd,mvntransistoresd,mvnfetesd
168 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]169 active varactor,varact,var
170 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]171
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]172 active pmoslvt,pfetlvt
173 active pmosmvt,pfetmvt
174 active pmoshvt,pfethvt
175 active nmoslvt,nfetlvt
176 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]177 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]178 -active sramnvar,corenvar,corenvaractor
179 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]180
181# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]182 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]183 active ndiff,ndiffusion,ndif
184 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]185 active mvndiff,mvndiffusion,mvndif
186 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]187 active ndiffc,ndcontact,ndc
188 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]189 active mvndiffc,mvndcontact,mvndc
190 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]191 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
192 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
193 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
194 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
195 active psubdiffcont,psubstratepcontact,psc,ptapc
196 active nsubdiffcont,nsubstratencontact,nsc,ntapc
197 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
198 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]199 -active obsactive
200 -active mvobsactive
201
202# Poly
203 active poly,p,polysilicon
204 active polycont,pc,pcontact,polycut,polyc
205 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]206 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]207
208# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]209 active npolyres,npres,mrp1
210 active ppolyres,ppres,xhrpoly
211 active xpolyres,xpres,xres,uhrpoly
212 active ndiffres,rnd,rdn,rndiff
213 active pdiffres,rpd,rdp,rpdiff
214 active mvndiffres,mvrnd,mvrdn,mvrndiff
215 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
216 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]217
218# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]219 active pdiode,pdi
220 active ndiode,ndi
221 active nndiode,nndi
222 active pdiodec,pdic
223 active ndiodec,ndic
224 active nndiodec,nndic
225 active mvpdiode,mvpdi
226 active mvndiode,mvndi
227 active mvpdiodec,mvpdic
228 active mvndiodec,mvndic
229 active pdiodelvt,pdilvt
230 active pdiodehvt,pdihvt
231 active ndiodelvt,ndilvt
232 active pdiodelvtc,pdilvtc
233 active pdiodehvtc,pdihvtc
234 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235
236# Local Interconnect
237 locali locali,li1,li
238 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]239 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]240 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]243 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]244
245# Metal 1
246 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]248 metal1 via1,m2contact,m2cut,m2c,via,v,v1
249 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]250 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 2
254 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 metal2 via2,m3contact,m3cut,m3c,v2
257 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]258 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259
260# Metal 3
261 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]263 -metal3 obsm3
264#ifdef METAL5
265 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]266 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]267
268#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]269 cap1 mimcap,mim,capm
270 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]271#endif
272
273# Metal 4
274 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276 -metal4 obsm4
277 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]278 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]279
280#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 cap2 mimcap2,mim2,capm2
282 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif
284
285# Metal 5
286 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]289 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]290#endif (METAL5)
291
292#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]293 metal5 mrdlcontact,mrdlc,pi1
294 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]296 metali pi2
297 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]298#endif (REDISTRIBUTION)
299
300# Miscellaneous
301 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]302 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]303 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]305# fixed resistor width identifiers
306 -comment res0p35
307 -comment res0p69
308 -comment res1p41
309 -comment res2p85
310 -comment res5p73
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]311# fixed bipolar area identifiers
312 -comment pnp0p68
313 -comment pnp3p40
314 -comment npn1p00
315 -comment npn2p00
316 -comment npn11p0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]317
318end
319
320#-----------------------------------------------------
321# Magic contact types
322#-----------------------------------------------------
323
324contact
325 pc poly locali
326 ndc ndiff locali
327 pdc pdiff locali
328 nsc nsd locali
329 psc psd locali
330 ndic ndiode locali
331 ndilvtc ndiodelvt locali
332 nndic nndiode locali
333 pdic pdiode locali
334 pdilvtc pdiodelvt locali
335 pdihvtc pdiodehvt locali
336 xpc xpc locali
337
338 mvndc mvndiff locali
339 mvpdc mvpdiff locali
340 mvnsc mvnsd locali
341 mvpsc mvpsd locali
342 mvndic mvndiode locali
343 mvpdic mvpdiode locali
344
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]345 mcon locali metal1
346 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]347
348 via1 metal1 metal2
349 via2 metal2 metal3
350#ifdef METAL5
351 via3 metal3 metal4
352 via4 metal4 metal5
353#endif (METAL5)
354 stackable
355
356#ifdef METAL5
357#ifdef MIM
358 # MiM cap contacts are not stackable!
359 mimcc mimcap metal4
360 mim2cc mimcap2 metal5
361#endif (MIM)
362
363 padl m1 m2 m3 m4 m5 glass
364#else
365 padl m1 m2 m3 glass
366#endif (!METAL5)
367
368#ifdef REDISTRIBUTION
369 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]370 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]371#endif (REDISTRIBUTION)
372end
373
374#-----------------------------------------------------
375# Layer aliases
376#-----------------------------------------------------
377
378aliases
379
380 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]381 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]382
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]383 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]384 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]385 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]386 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allfetsspecial scnfet,scpfet,scpfethvt
388 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]389 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]390
391 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
392 allnactive allnactivenonfet,allnfets
393 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]394 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]395
396 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
397 allpactive allpactivenonfet,allpfets
398 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]399 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]400
401 allactivenonfet allnactivenonfet,allpactivenonfet
402 allactive allactivenonfet,allfets
403
404 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
405
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]406 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]407 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]408 alldifflv allndifflv,allpdifflv
409 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
410 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
411 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
412
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]413 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]414 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]415 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]416 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]417 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]418 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
419 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
420 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
421 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
422
423 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]424 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]425
426 allpolyres mrp1,xhrpoly,uhrpoly,rmp
427 allpolynonfet *poly,allpolyres,xpc
428 allpolynonres *poly,allfets,xpc
429
430 allpoly allpolynonfet,allfets
431 allpolynoncap *poly,xpc,allfets,allpolyres
432
433 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
434 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
435 allndiffcontmv mvndc,mvnsc,mvndic
436 allpdiffcontmv mvpdc,mvpsc,mvpdic
437 allndiffcont allndiffcontlv,allndiffcontmv
438 allpdiffcont allpdiffcontlv,allpdiffcontmv
439 alldiffcontlv allndiffcontlv,allpdiffcontlv
440 alldiffcontmv allndiffcontmv,allpdiffcontmv
441 alldiffcont alldiffcontlv,alldiffcontmv
442
443 allcont alldiffcont,pc
444
445 allres allpolyres,allactiveres
446
447 allli *locali,coreli,rli
448 allm1 *m1,rm1
449 allm2 *m2,rm2
450 allm3 *m3,rm3
451#ifdef METAL5
452 allm4 *m4,rm4
453 allm5 *m5,rm5
454#endif (METAL5)
455
456 allpad padl
457
458 psub pwell
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]459
460 obstypes obswell,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment
461 idtypes res0p35,res0p69,res1p41,res2p85,res5p73,pnp0p68,pnp3p40,npn1p00,npn2p00,npn11p0
462 blocktypes fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]463
464end
465
466#-----------------------------------------------------
467# Layer drawing styles
468#-----------------------------------------------------
469
470styles
471 styletype mos
472 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]473 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]474 nwell nwell
475 pwell pwell
476 rpwell pwell ptransistor_stripes
477 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]478 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]479 pdiff pdiffusion
480 nsd ndiff_in_nwell
481 psd pdiff_in_pwell
482 nfet ntransistor ntransistor_stripes
483 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]484 npass ntransistor ntransistor_stripes
485 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 pfet ptransistor ptransistor_stripes
487 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]488 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]489 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]490 var polysilicon ndiff_in_nwell
491 ndc ndiffusion metal1 contact_X'es
492 pdc pdiffusion metal1 contact_X'es
493 nsc ndiff_in_nwell metal1 contact_X'es
494 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]495 corenvar polysilicon ndiff_in_nwell
496 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]498 pnp nwell ntransistor_stripes
499 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]500
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]501 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]502 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]503 pfethvt ptransistor ptransistor_stripes implant2
504 nfetlvt ntransistor ntransistor_stripes implant1
505 nsonos ntransistor implant3
506 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]507 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508
509 mvndiff ndiffusion hvndiff_mask
510 mvpdiff pdiffusion hvpdiff_mask
511 mvnsd ndiff_in_nwell hvndiff_mask
512 mvpsd pdiff_in_pwell hvpdiff_mask
513 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]514 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]515 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
516 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]517 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]518 mvvar polysilicon ndiff_in_nwell hvndiff_mask
519 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
520 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
521 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
522 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
523
524 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]525 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]526 pc polysilicon metal1 contact_X'es
527 npolyres polysilicon silicide_block nselect2
528 ppolyres polysilicon silicide_block pselect2
529 xpc polysilicon pselect2 metal1 contact_X'es
530 rmp polysilicon poly_resist_stripes
531
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]532 res0p35 implant1
533 res0p69 implant1
534 res1p41 implant1
535 res2p85 implant1
536 res5p73 implant1
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]537 pnp0p68 implant1
538 pnp3p40 implant1
539 npn1p00 implant1
540 npn2p00 implant1
541 npn11p0 implant1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]542
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]543 pdiode pdiffusion pselect2
544 ndiode ndiffusion nselect2
545 pdiodec pdiffusion pselect2 metal1 contact_X'es
546 ndiodec ndiffusion nselect2 metal1 contact_X'es
547
548 nndiode ndiffusion nselect2 implant3
549 ndiodelvt ndiffusion nselect2 implant1
550 pdiodelvt pdiffusion pselect2 implant1
551 pdiodehvt pdiffusion pselect2 implant2
552 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
553 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
554 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
555
556 mvpdiode pdiffusion pselect2 hvpdiff_mask
557 mvndiode ndiffusion nselect2 hvndiff_mask
558 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
559 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
560 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
561
562 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]563 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]564 coreli metal1
565 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]566 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]567 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]568 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]569
570 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]571 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]572 rm1 metal2 poly_resist_stripes
573 obsm1 metal2
574 m2c metal2 metal3 via2arrow
575 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]576 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]577 rm2 metal3 poly_resist_stripes
578 obsm2 metal3
579 m3c metal3 metal4 via3alt
580 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]581 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]582 rm3 metal4 poly_resist_stripes
583 obsm3 metal4
584#ifdef METAL5
585#ifdef MIM
586 mimcap metal3 mems
587 mimcc metal3 contact_X'es mems
588 mimcap2 metal4 mems
589 mim2cc metal4 contact_X'es mems
590#endif (MIM)
591 via3 metal4 metal5 via4
592 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]593 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]594 rm4 metal5 poly_resist_stripes
595 obsm4 metal5
596 via4 metal5 metal6 via5
597 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]598 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]599 rm5 metal6 poly_resist_stripes
600 obsm5 metal6
601#endif (METAL5)
602#ifdef REDISTRIBUTION
603 mrdlc metal6 metal7 via6
604 metalrdl metal7
605 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]606 ubm metal8
607 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]608#endif (REDISTRIBUTION)
609
610 glass overglass
611 mrp1 poly_resist poly_resist_stripes
612 xhrpoly poly_resist silicide_block
613 uhrpoly poly_resist
614 ndiffres ndiffusion ndop_stripes
615 pdiffres pdiffusion pdop_stripes
616 mvndiffres ndiffusion hvndiff_mask ndop_stripes
617 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
618 comment comment
619 error_p error_waffle
620 error_s error_waffle
621 error_ps error_waffle
622 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]623 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]624
625 obswell cwell
626 obsactive implant4
627
628#ifndef METAL5
629 padl metal4 via4 overglass
630#else
631 padl metal6 via6 overglass
632#endif
633
634 magnet substrate_field_implant
635 rotate via3alt
636 fence via5
637end
638
639#-----------------------------------------------------
640# Special paint/erase rules
641#-----------------------------------------------------
642
643compose
644 compose nfet poly ndiff
645 compose pfet poly pdiff
646 compose var poly nsd
647
648 compose mvnfet poly mvndiff
649 compose mvpfet poly mvpdiff
650 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]651
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]652 paint obsmcon locali via1
653 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]654
655 paint ndc nwell pdc
656 paint nfet nwell pfet
657 paint scnfet nwell scpfet
658 paint ndiff nwell pdiff
659 paint psd nwell nsd
660 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]661 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]662
663 paint pdc pwell ndc
664 paint pfet pwell nfet
665 paint scpfet pwell scnfet
666 paint pdiff pwell ndiff
667 paint nsd pwell psd
668 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]669 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]670
671 paint pdc coreli pdc
672 paint ndc coreli ndc
673 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]674 paint nsc coreli nsc
675 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]676 paint viali coreli viali
677
678 paint coreli pdc pdc
679 paint coreli ndc ndc
680 paint coreli pc pc
681 paint coreli nsc nsc
682 paint coreli psc psc
683 paint coreli viali viali
684
685#ifdef METAL5
686 paint m4 obsm4 m4
687 paint m5 obsm5 m5
688#endif (METAL5)
689end
690
691#-----------------------------------------------------
692# Electrical connectivity
693#-----------------------------------------------------
694
695connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]696 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
697 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]698 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]699 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]700 *m2,m2fill *m2,m2fill
701 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]702#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]703 *m4,m4fill *m4,m4fill
704 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]705#ifdef MIM
706 *mimcap *mimcap
707 *mimcap2 *mimcap2
708#endif (MIM)
709#endif (METAL5)
710 allnactivenonfet allnactivenonfet
711 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]712 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]713#ifdef REDISTRIBUTION
714 # RDL connects to m5 (i.e., padl) through glass cut
715 *mrdl *mrdl
716 glass metrdl
717#endif (REDISTRIBUTION)
718end
719
720#-----------------------------------------------------
721# CIF/GDS output layer definitions
722#-----------------------------------------------------
723# NOTE: All values in this section MUST be multiples of 25
724# or else magic will scale below the allowed layout grid size
725
726cifoutput
727
728#----------------------------------------------------------------
729style gdsii
730# NOTE: This section is used for actual GDS output
731#----------------------------------------------------------------
732 scalefactor 10 nanometers
733 options calma-permissive-labels
734 gridlimit 5
735
736#----------------------------------------------------------------
737# Create a temp layer from the cell bounding box for use in
738# generating ID layers. Note that "boundary", unlike "bbox",
739# requires the FIXED_BBOX property (abutment box) in the cell.
740#----------------------------------------------------------------
741 templayer CELLBOUND
742 boundary
743
744#----------------------------------------------------------------
745# BOUND
746#----------------------------------------------------------------
747 layer BOUND CELLBOUND
748 calma 235 4
749
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]750#----------------------------------------------------------------
751# DNWELL
752#----------------------------------------------------------------
753
Tim Edwards4d579412021-06-01 15:59:24 -0400[diff] [blame]754 layer DNWELL dnwell,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]755 calma 64 18
756
757 layer PWRES rpw
758 and dnwell
759 calma 64 13
760
761#----------------------------------------------------------------
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]762# SUBCUT
763#----------------------------------------------------------------
764
765 layer SUBCUT isosub
766 calma 81 53
767
768#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]769# NWELL
770#----------------------------------------------------------------
771
772 layer NWELL allnwell
773 bloat-all rpw dnwell
774 and-not rpw,pwell
775 calma 64 20
776
777 layer WELLTXT
778 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]779 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]780
781 layer WELLPIN
782 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]783 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]784
785#----------------------------------------------------------------
786# SUB (text/port only)
787#----------------------------------------------------------------
788
789 layer SUBTXT
790 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]791 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]792
793 layer SUBPIN
794 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]795 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]796
797#----------------------------------------------------------------
798# DIFF
799#----------------------------------------------------------------
800
801 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]802 calma 65 20
803
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]804 layer DIFFTXT
805 labels allnactivenontap,allpactivenontap noport
806 calma 65 6
807
808 layer DIFFPIN
809 labels allnactivenontap,allpactivenontap port
810 calma 65 16
811
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]812#----------------------------------------------------------------
813# TAP
814#----------------------------------------------------------------
815
816 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]817 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]818 calma 65 44
819
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]820 layer TAPTXT
821 labels allnactivetap,allpactivetap noport
822 calma 65 5
823
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]824#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]825# FOM
826#----------------------------------------------------------------
827
828 layer FOMFILL fomfill
829 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]830 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]831
832#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]833# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]834#----------------------------------------------------------------
835
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]836 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]837 grow 15
838 or xhrpoly,uhrpoly,xpc
839 grow 110
840 bloat-or allpactivetap * 125 allnactivenontap 0
841 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]842
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]843 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]844 grow 125
845 bloat-or allnactivetap * 125 allpactivenontap 0
846 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]847
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]848 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]849 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]850 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]851
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]852 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]853 grow 185
854 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]855 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]856 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]857 calma 94 20
858
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]859 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]860 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]861 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]862
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]863 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]864 grow 185
865 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]866 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]867 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]868 calma 93 44
869
870#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]871# LVID
872#----------------------------------------------------------------
873
874 layer LVID nnfet
875 grow 100
876 calma 81 60
877
878#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]879# LVTN
880#----------------------------------------------------------------
881
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]882 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]883 grow 180
884 bridge 380 380
885 grow 185
886 shrink 185
887 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]888 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]889 calma 125 44
890
891#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]892# HVTR
893#----------------------------------------------------------------
894
895 layer HVTR pfetmvt
896 grow 180
897 bridge 380 380
898 grow 185
899 shrink 185
900 close 265000
901 calma 18 20
902
903#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]904# HVTP
905#----------------------------------------------------------------
906
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]907 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]908 grow 180
909 bridge 380 380
910 grow 185
911 shrink 185
912 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]913 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]914 calma 78 44
915
916#----------------------------------------------------------------
917# SONOS
918#----------------------------------------------------------------
919
920 layer SONOS nsonos
921 grow 100
922 grow-min 410
923 bridge 500 410
924 grow 250
925 shrink 250
926 calma 80 20
927
928#----------------------------------------------------------------
929# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]930# coreli layer indicates a cell needing COREID. Also, devices
931# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]932#----------------------------------------------------------------
933
934 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]935 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]936 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]937 calma 81 2
938
939#----------------------------------------------------------------
940# STDCELL applies to all cells containing scnfet or scpfet.
941#----------------------------------------------------------------
942
943 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]944 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]945 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]946 calma 81 4
947
948#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]949# ESDID is a marker layer for ESD devices in the padframe I/O.
950#----------------------------------------------------------------
951
952 layer ESDID
953 bloat-all mvnfetesd *mvndiff,*poly
954 bloat-all mvpfetesd *mvpdiff,*poly
955 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]956 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]957 calma 81 19
958
959#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]960# NPNID and PNPID apply to bipolar transistors
961#----------------------------------------------------------------
962
963 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]964 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]965 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]966 calma 82 20
967
968 templayer pnparea pnp
969 grow 400
970
971 layer PNPID
972 bloat-all pnparea *psd
973 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]974 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]975 calma 82 44
976
977#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]978# RPM
979#----------------------------------------------------------------
980
981 layer RPM
982 bloat-all xhrpoly xpc
983 grow 200
984 grow-min 1270
985 grow 420
986 shrink 420
987 calma 86 20
988
989#----------------------------------------------------------------
990# URPM (2kOhms/sq. poly implant)
991#----------------------------------------------------------------
992
993 layer URPM
994 bloat-all uhrpoly xpc
995 grow 200
996 grow-min 1270
997 grow 420
998 shrink 420
999 calma 79 20
1000
1001#----------------------------------------------------------------
1002# LDNTM (Tip implant for SONOS FETs)
1003#----------------------------------------------------------------
1004
1005 layer LDNTM
1006 bloat-all nsonos *ndiff
1007 grow 185
1008 grow 345
1009 shrink 345
1010 calma 11 44
1011
1012#----------------------------------------------------------------
1013# HVNTM (Tip implant for MV ndiff devices)
1014#----------------------------------------------------------------
1015
1016 templayer hvntm_block *mvpsd
1017 grow 185
1018
1019 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1020 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1021 bloat-all mvvaractor *mvnsd
1022 and-not hvntm_block
1023 grow 185
1024 grow 345
1025 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1026 and-not hvntm_block
Tim Edwardsce38f722021-07-22 11:43:58 -0400[diff] [blame]1027 mask-hints HVNTM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1028 calma 125 20
1029
1030#----------------------------------------------------------------
1031# POLY
1032#----------------------------------------------------------------
1033
1034 layer POLY allpoly
1035 calma 66 20
1036
1037 layer POLYTXT
1038 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1039 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1040
1041 layer POLYPIN
1042 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1043 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1044
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1045 layer POLYFILL polyfill
1046 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1047 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1048
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1049#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1050# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1051#----------------------------------------------------------------
1052
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1053 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1054 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1055 bloat-all alldiffmv nwell
1056 grow 345
1057 shrink 345
1058
1059 templayer large_ptap_mv thkox_area
1060 shrink 420
1061 grow 420
1062
1063 templayer small_ptap_mv thkox_area
1064 and-not large_ptap_mv
1065 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1066 grow-min 840
1067
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1068 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1069 bridge 700 600
1070 grow 345
1071 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1072 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1073 calma 75 20
1074
1075#----------------------------------------------------------------
1076# CONT (LICON)
1077#----------------------------------------------------------------
1078
1079 layer CONT allcont
1080 squares-grid 0 170 170
1081 calma 66 44
1082
1083 # Contact for pres is different than other LICON contacts
1084 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1085 templayer xpc_horiz xpc
1086 shrink 1007
1087 grow 1007
1088
1089 layer CONT xpc
1090 and-not xpc_horiz
1091 # Force long edge vertical for contacts narrower than 2um
1092 # Minimum space is 350 but 520 satisfies no. of contacts rule
1093 slots 80 190 520 80 2000 350
1094 calma 66 44
1095
1096 layer CONT xpc
1097 and xpc_horiz
1098 # Force long edge vertical for contacts wider than 2um
1099 # Minimum space is 350 but 520 satisfies no. of contacts rule
1100 slots 80 2000 350 80 190 520
1101 calma 66 44
1102
1103#----------------------------------------------------------------
1104# NPC (Nitride poly cut)
1105# surrounds CONT (LICON) on poly only (i.e., pc)
1106#----------------------------------------------------------------
1107
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1108 # Avoids a common case of NPC bridges too close to other LICON shapes.
1109 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1110 grow 90
1111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1112 layer NPC pc
1113 squares-grid 0 170 170
1114 grow 100
1115 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1116 and-not diffcutarea
1117 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1118 grow 130
1119 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1120 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1121 calma 95 20
1122
1123 # NPC is also generated on xhrpoly and uhrpoly resistors
1124
1125 layer NPC xpc,xhrpoly,uhrpoly
1126 # xpc surrounds precision_resistor by 0.095um
1127 grow 95
1128 grow 130
1129 shrink 130
1130 calma 95 20
1131
1132#----------------------------------------------------------------
1133# Device markers
1134#----------------------------------------------------------------
1135
1136 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1137 calma 65 13
1138
1139 layer POLYRES mrp1
1140 calma 66 13
1141
1142 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1143 layer POLYSHORT rmp
1144 calma 66 15
1145
1146 # POLYRES extends to edge of contact cut
1147 layer POLYRES xhrpoly,uhrpoly
1148 grow 60
1149 and xpc
1150 or xhrpoly,uhrpoly
1151 calma 66 13
1152
1153 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1154 # To be done: Expand to include anode, cathode, and guard ring
1155 calma 81 23
1156
1157#----------------------------------------------------------------
1158# LI
1159#----------------------------------------------------------------
1160 layer LI allli
1161 calma 67 20
1162
1163 layer LITXT
1164 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1165 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1166
1167 layer LIPIN
1168 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1169 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1170
1171 layer LIRES rli
1172 labels rli
1173 calma 67 13
1174
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1175 layer LIFILL lifill
1176 labels lifill
1177 calma 56 28
1178
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1179#----------------------------------------------------------------
1180# MCON
1181#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1182 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1183 squares-grid 0 170 190
1184 calma 67 44
1185
1186#----------------------------------------------------------------
1187# MET1
1188#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1189 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1190 calma 68 20
1191
1192 layer MET1TXT
1193 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1194 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1195
1196 layer MET1PIN
1197 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1198 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1199
1200 layer MET1RES rm1
1201 labels rm1
1202 calma 68 13
1203
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1204 layer MET1FILL m1fill
1205 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1206 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1207
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1208#----------------------------------------------------------------
1209# VIA1
1210#----------------------------------------------------------------
1211 layer VIA1 via1
1212 squares-grid 55 150 170
1213 calma 68 44
1214
1215#----------------------------------------------------------------
1216# MET2
1217#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1218 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1219 calma 69 20
1220
1221 layer MET2TXT
1222 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1223 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1224
1225 layer MET2PIN
1226 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1227 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1228
1229 layer MET2RES rm2
1230 labels rm2
1231 calma 69 13
1232
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1233 layer MET2FILL m2fill
1234 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1235 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1236
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1237#----------------------------------------------------------------
1238# VIA2
1239#----------------------------------------------------------------
1240 layer VIA2 via2
1241 squares-grid 40 200 200
1242 calma 69 44
1243
1244#----------------------------------------------------------------
1245# MET3
1246#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1247 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1248 calma 70 20
1249
1250 layer MET3TXT
1251 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1252 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1253
1254 layer MET3PIN
1255 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1256 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1257
1258 layer MET3RES rm3
1259 labels rm3
1260 calma 70 13
1261
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1262 layer MET3FILL m3fill
1263 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1264 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1265
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1266#ifdef METAL5
1267#----------------------------------------------------------------
1268# VIA3
1269#----------------------------------------------------------------
1270 layer VIA3 via3
1271#ifdef MIM
1272 or mimcc
1273#endif (MIM)
1274 squares-grid 60 200 200
1275 calma 70 44
1276
1277#----------------------------------------------------------------
1278# MET4
1279#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1280 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1281 calma 71 20
1282
1283 layer MET4TXT
1284 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1285 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1286
1287 layer MET4PIN
1288 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1289 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1290
1291 layer MET4RES rm4
1292 labels rm4
1293 calma 71 13
1294
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1295 layer MET4FILL m4fill
1296 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1297 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1298
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1299#----------------------------------------------------------------
1300# VIA4
1301#----------------------------------------------------------------
1302 layer VIA4 via4
1303#ifdef MIM
1304 or mim2cc
1305#endif (MIM)
1306 squares-grid 190 800 800
1307 calma 71 44
1308
1309#----------------------------------------------------------------
1310# MET5
1311#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1312 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1313 calma 72 20
1314
1315 layer MET5TXT
1316 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1317 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1318
1319 layer MET5PIN
1320 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1321 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1322
1323 layer MET5RES rm5
1324 labels rm5
1325 calma 72 13
1326
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1327 layer MET5FILL m5fill
1328 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1329 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1330
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1331#endif (METAL5)
1332
1333#ifdef REDISTRIBUTION
1334#----------------------------------------------------------------
1335# RDL
1336#----------------------------------------------------------------
1337 layer RDL *metrdl
1338 calma 74 20
1339
1340 layer RDLTXT
1341 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1342 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1343
1344 layer RDLPIN
1345 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1346 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1347
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1348 layer PI1 *metrdl
1349 and padl,glass
1350 # Test only---needs GDS layer number
1351
1352 layer UBM *metrdl
1353 shrink 50000
1354 grow 40000
1355 # Test only---needs GDS layer number
1356
1357 layer PI2 *metrdl
1358 shrink 50000
1359 grow 25000
1360 # Test only---needs GDS layer number
1361
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1362#endif REDISTRIBUTION
1363
1364#----------------------------------------------------------------
1365# GLASS
1366#----------------------------------------------------------------
1367 layer GLASS glass
1368 calma 76 20
1369
1370#ifdef MIM
1371#----------------------------------------------------------------
1372# CAPM
1373#----------------------------------------------------------------
1374 layer CAPM *mimcap
1375 labels mimcap
1376 calma 89 44
1377
1378 layer CAPM2 *mimcap2
1379 labels mimcap2
1380 calma 97 44
1381#endif (MIM)
1382
1383#----------------------------------------------------------------
1384# Chip top level marker for DRC latchup rules to check 15um
1385# distance to taps (otherwise 6um is used)
1386#----------------------------------------------------------------
1387
1388 layer LOWTAPDENSITY
1389 bbox top
1390 # Clear 200um for pads + 50um for required high tap density
1391 # in critical area.
1392 shrink 250000
1393 calma 81 14
1394
1395#----------------------------------------------------------------
1396# FILLBLOCK
1397#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1398 layer FILLOBSFOM obsactive
1399 calma 22 24
1400
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1401 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1402 calma 62 24
1403
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1404 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1405 calma 105 52
1406
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1407 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1408 calma 107 24
1409
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1410 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1411 calma 112 4
1412
1413 render DNWELL cwell -0.1 0.1
1414 render NWELL nwell 0.0 0.2062
1415 render DIFF ndiffusion 0.2062 0.12
1416 render TAP pdiffusion 0.2062 0.12
1417 render POLY polysilicon 0.3262 0.18
1418 render CONT via 0.5062 0.43
1419 render LI metal1 0.9361 0.10
1420 render MCON via 1.0361 0.34
1421 render MET1 metal2 1.3761 0.36
1422 render VIA1 via 1.7361 0.27
1423 render MET2 metal3 2.0061 0.36
1424 render VIA2 via 2.3661 0.42
1425 render MET3 metal4 2.7861 0.845
1426#ifdef METAL5
1427 render VIA3 via 3.6311 0.39
1428 render MET4 metal5 4.0211 0.845
1429 render VIA4 via 4.8661 0.505
1430 render MET5 metal6 5.3711 1.26
1431 render CAPM metal8 2.4661 0.2
1432 render CAPM2 metal9 3.7311 0.2
1433#ifdef REDISTRIBUTION
1434 render RDL metal7 11.8834 4.0
1435#endif (!REDISTRIBUTION)
1436#endif (!METAL5)
1437
1438#----------------------------------------------------------------
1439style drc
1440#----------------------------------------------------------------
1441# NOTE: This style is used for DRC only, not for GDS output
1442#----------------------------------------------------------------
1443 scalefactor 10 nanometers
1444 options calma-permissive-labels
1445
1446 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1447 templayer dnwell_shrink dnwell
1448 shrink 1030
1449
1450 templayer nwell_missing dnwell
1451 grow 400
1452 and-not dnwell_shrink
1453 and-not nwell
1454
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1455 templayer pwell_in_dnwell dnwell
1456 and-not nwell
1457
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1458 # SONOS nFET devices must be in deep nwell
1459 templayer dnwell_missing nsonos
1460 and-not dnwell
1461
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1462 # SONOS nFET devices must be in cell with abutment box
1463 templayer abutment_box
1464 boundary
1465
1466 templayer bbox_missing nsonos
1467 and-not abutment_box
1468
1469 # Make sure nwell covers varactor poly
1470 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1471 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1472 grow 150
1473 and-not nwell
1474
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1475 # Define MiM cap bottom plate for spacing rule
1476 templayer mim_bottom
1477 bloat-all *mimcap *metal3
1478
1479 # Define MiM2 cap bottom plate for spacing rule
1480 templayer mim2_bottom
1481 bloat-all *mimcap2 *metal4
1482
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]1483 # Define areas where mim2cc is inside the boundary of mimcc
1484 # by more than the contact surround
1485 templayer mim2_contact_overlap
1486 bloat-all *mimcap2 mimcc
1487 shrink 60
1488 and-not *mimcap2
1489
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1490 # Note that metal fill is performed by the foundry and so is not
1491 # an option for a cifoutput style.
1492
1493 # Check latchup rule (15um minimum from tap LICON center to any
1494 # non-tap diffusion. Note that to count as a tap, the diffusion
1495 # must be contacted to LI
1496
1497 templayer ptap_reach psc,mvpsc
1498 and-not dnwell
1499 # grow total is 15um. grow in 0.84um increments to ensure that
1500 # no nwell ring is crossed
1501 grow 840
1502 and-not nwell,dnwell
1503 grow 840
1504 and-not nwell,dnwell
1505 grow 840
1506 and-not nwell,dnwell
1507 grow 840
1508 and-not nwell,dnwell
1509 grow 840
1510 and-not nwell,dnwell
1511 grow 840
1512 and-not nwell,dnwell
1513 grow 840
1514 and-not nwell,dnwell
1515 grow 840
1516 and-not nwell,dnwell
1517 grow 840
1518 and-not nwell,dnwell
1519 grow 840
1520 and-not nwell,dnwell
1521 grow 840
1522 and-not nwell,dnwell
1523 grow 840
1524 and-not nwell,dnwell
1525 grow 840
1526 and-not nwell,dnwell
1527 grow 840
1528 and-not nwell,dnwell
1529 grow 840
1530 and-not nwell,dnwell
1531 grow 840
1532 and-not nwell,dnwell
1533 grow 840
1534 and-not nwell,dnwell
1535 grow 635
1536 and-not nwell,dnwell
1537
1538 templayer ptap_missing *ndiff,*mvndiff
1539 and-not dnwell
1540 and-not ptap_reach
1541
1542 templayer ntap_reach nsc,mvnsc
1543 # grow total is 15um. grow in 1.27um increments to ensure that
1544 # no nwell ring is crossed. There is no difference between
1545 # ntaps in and out of deep nwell.
1546 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1547 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1548 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1549 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1550 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1551 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1552 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1553 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1554 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1555 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1556 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1557 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1558 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1559 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1560 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1561 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1562 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1563 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1564 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1565 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1566 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1567 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1568 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1569 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1570
1571 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1572 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1573 and-not ntap_reach
1574
1575 templayer dptap_reach psc,mvpsc
1576 and dnwell
1577 grow 840
1578 and-not nwell
1579 and dnwell
1580 grow 840
1581 and-not nwell
1582 and dnwell
1583 grow 840
1584 and-not nwell
1585 and dnwell
1586 grow 840
1587 and-not nwell
1588 and dnwell
1589 grow 840
1590 and-not nwell
1591 and dnwell
1592 grow 840
1593 and-not nwell
1594 and dnwell
1595 grow 840
1596 and-not nwell
1597 and dnwell
1598 grow 840
1599 and-not nwell
1600 and dnwell
1601 grow 840
1602 and-not nwell
1603 and dnwell
1604 grow 840
1605 and-not nwell
1606 and dnwell
1607 grow 840
1608 and-not nwell
1609 and dnwell
1610 grow 840
1611 and-not nwell
1612 and dnwell
1613 grow 840
1614 and-not nwell
1615 and dnwell
1616 grow 840
1617 and-not nwell
1618 and dnwell
1619 grow 840
1620 and-not nwell
1621 and dnwell
1622 grow 840
1623 and-not nwell
1624 and dnwell
1625 grow 840
1626 and-not nwell
1627 and dnwell
1628 grow 635
1629 and-not nwell
1630 and dnwell
1631
1632 templayer dptap_missing *ndiff,*mvndiff
1633 and dnwell
1634 and-not dptap_reach
1635
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1636 templayer pdiff_crosses_dnwell dnwell
1637 grow 20
1638 and-not dnwell
1639 and allpdifflv,allpdiffmv
1640
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1641 # MV nwell must be 2um from any other nwell
1642 templayer mvnwell
1643 bloat-all alldiffmv nwell
1644 grow-min 840
1645 bridge 700 600
1646
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1647 # Simple spacing checks to lvnwell must use CIF-DRC rule
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1648 # Note that HVI may *abut* lvnwell; this can only be handled
1649 # with mask-hints layers.
1650
1651 templayer drawn_hvi
1652 mask-hints HVI
1653
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1654 templayer allmvdiffnowell *mvndiff,*mvpsd
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1655 and-not drawn_hvi
1656
1657 templayer nwell_or_hvi nwell,drawn_hvi
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1658
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1659 templayer lvnwell nwell
1660 and-not mvnwell
1661
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1662 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1663 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1664
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1665 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1666 and-not nwell_with_tap
1667
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1668 templayer tap_with_licon
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1669 bloat-all allpactivetap psd,mvpsd
1670 bloat-all allnactivetap nsd,mvnsd
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1671
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1672 templayer tap_missing_licon allnactivetap,allpactivetap
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1673 and-not tap_with_licon
1674
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1675 # Make sure varactor nwell contains no P diffusion
1676 templayer pdiff_in_varactor_well
1677 bloat-all varactor,mvvaractor nwell
1678 and allpactive
1679
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1680 # HVNTM spacing requires recreating HVNTM
1681 templayer hvntm_block *mvpsd
1682 grow 185
1683
1684 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1685 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1686 bloat-all mvvaractor *mvnsd
1687 and-not hvntm_block
1688 grow 185
1689 grow 345
1690 shrink 345
1691 and-not hvntm_block
1692
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1693 # RPM spacing checks require recreating RPM
1694 templayer rpm_generate
1695 bloat-all xhrpoly,uhrpoly xpc
1696 grow 200
1697 grow-min 1270
1698 grow 420
1699 shrink 420
1700
1701 # Check distance RPM to NSDM
1702 templayer rpm_nsd_check rpm_generate
1703 grow 325
1704 and allndifflv,allndiffmv
1705
1706 # Check distance RPM to (unrelated) POLY
1707 templayer rpm_poly_check rpm_generate
1708 grow 200
1709 and-not xhrpoly,uhrpoly,xpc
1710 and allpoly
1711
1712 # Check distance RPM to HVNTM
1713 templayer rpm_hvntm_check rpm_generate
1714 grow 385
1715 and allndiffmvnontap
1716
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1717 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1718 close 140000
1719
1720 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1721 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1722
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1723 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1724 close 140000
1725
1726 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1727 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1728
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1729 templayer m1_huge allm1
1730 shrink 1500
1731 grow 1500
1732
1733 templayer m1_large_halo m1_huge
1734 grow 280
1735 and-not m1_huge
1736 and allm1
1737
1738 templayer m2_huge allm2
1739 shrink 1500
1740 grow 1500
1741
1742 templayer m2_large_halo m2_huge
1743 grow 280
1744 and-not m2_huge
1745 and allm2
1746
1747 templayer m3_huge allm3
1748 shrink 1500
1749 grow 1500
1750
1751 templayer m3_large_halo m3_huge
1752 grow 400
1753 and-not m3_huge
1754 and allm3
1755
1756 templayer m4_huge allm4
1757 shrink 1500
1758 grow 1500
1759
1760 templayer m4_large_halo m4_huge
1761 grow 400
1762 and-not m4_huge
1763 and allm4
1764
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1765#ifdef EXPERIMENTAL
1766#----------------------------------------------------------------
1767style paint
1768#----------------------------------------------------------------
1769# NOTE: This style is used for database manipulations only via
1770# the "cif paint" command.
1771#----------------------------------------------------------------
1772
1773 scalefactor 10 nanometers
1774
1775 templayer m1grow *m1
1776 grow 290
1777
1778 # layer listrap: Use the following set of commands to strap local
1779 # interconnect wires with metal1 (inside the cursor box) to satisfy
1780 # the maximum aspect ratio rule for local interconnect:
1781 #
1782 # tech unlock *
1783 # cif ostyle paint
1784 # cif paint m1strap comment
1785 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1786 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1787 # erase comment
1788
1789 templayer m1strap *li
1790 and-not m1grow
1791 grow 30
1792
1793 templayer listrap comment
1794 slots 30 170 170 60
1795
1796#endif (EXPERIMENTAL)
1797
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1798#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1799style density
1800#----------------------------------------------------------------
1801# Style used by scripts to check for fill density
1802#----------------------------------------------------------------
1803 scalefactor 10 nanometers
1804 options calma-permissive-labels
1805 gridlimit 5
1806
1807 templayer fom_all alldiff,fomfill
1808
1809 templayer poly_all allpoly,polyfill
1810
1811 templayer li_all allli,lifill
1812
1813 templayer m1_all allm1,m1fill
1814
1815 templayer m2_all allm2,m2fill
1816
1817 templayer m3_all allm3,m3fill
1818
1819 templayer m4_all allm4,m4fill
1820
1821 templayer m5_all allm5,m5fill
1822
1823#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1824style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1825#----------------------------------------------------------------
1826# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1827# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1828#----------------------------------------------------------------
1829 scalefactor 10 nanometers
1830 options calma-permissive-labels
1831 gridlimit 5
1832
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1833#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1834# Generate and retain a layer representing the bounding box.
1835#
1836# For variant ():
1837# The bounding box is the full extent of geometry on the top level
1838# cell.
1839#
1840# For variant (tiled):
1841# Use with a script that breaks layout into flattened tiles and runs
1842# fill individually on each. The tiles should be larger than the
1843# step size, and each should draw a layer "comment" the size of the
1844# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1845#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1846
1847 variants ()
1848 templayer topbox
1849 bbox top
1850
1851 variants (tiled)
1852 templayer topbox comment
1853 # Each tile imposes the full keepout distance rule of
1854 # 3um on all sides.
1855 shrink 1500
1856
1857 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1858
1859#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1860# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1861# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1862# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1863# Enclosure by nwell = Diff/Tap 8 = 0.18um
1864#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1865
1866 templayer mvnwell
1867 bloat-all alldiffmv nwell
1868
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1869 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1870 and-not mvnwell
1871
1872 templayer well_shrink mvnwell
1873 shrink 250
1874 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1875 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1876 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1877 grow 340
1878 and-not well_shrink
1879
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1880#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1881# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1882#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1883 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1884 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1885 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1886 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1887
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1888 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1889 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1890 grow 1000
1891
1892#---------------------------------------------------
1893# FOM and POLY fill
1894#---------------------------------------------------
1895 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1896 # slots 0 4080 1320 0 4080 1320 1360 0
1897 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1898 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1899 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1900 shrink 2035
1901 grow 2035
1902
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1903#---------------------------------------------------
1904
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1905 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1906 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1907 or obstruct_poly
1908 templayer polyfill_pass1 topbox
1909 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1910 and-not obstruct_poly_pass1
1911 and topbox
1912 shrink 355
1913 grow 355
1914
1915#---------------------------------------------------
1916
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1917 templayer obstruct_fom_pass2 fomfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1918 grow 1290
1919 or polyfill_pass1
1920 grow 300
1921 or obstruct_fom
1922 templayer fomfill_pass2 topbox
1923 slots 0 2500 1320 0 2500 1320 1360 0
1924 and-not obstruct_fom_pass2
1925 and topbox
1926 shrink 1245
1927 grow 1245
1928
1929#---------------------------------------------------
1930
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1931 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1932 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1933 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1934 grow 300
1935 or obstruct_poly
1936 templayer polyfill_coarse topbox
1937 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1938 and-not obstruct_poly_coarse
1939 and topbox
1940 shrink 355
1941 grow 355
1942
1943#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1944 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1945 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1946 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1947 grow 300
1948 or obstruct_poly
1949 templayer polyfill_medium topbox
1950 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1951 and-not obstruct_poly_medium
1952 and topbox
1953 shrink 265
1954 grow 265
1955
1956#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1957 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1958 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1959 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1960 grow 300
1961 or obstruct_poly
1962 templayer polyfill_fine topbox
1963 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1964 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1965 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1966 shrink 235
1967 grow 235
1968
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1969#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1970
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1971 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1972 grow 1290
1973 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1974 grow 300
1975 or obstruct_fom
1976 templayer fomfill_coarse topbox
1977 slots 0 1500 1320 0 1500 1320 1360 0
1978 and-not obstruct_fom_coarse
1979 and topbox
1980 shrink 745
1981 grow 745
1982
1983#---------------------------------------------------
1984
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1985 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1986 grow 1290
1987 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1988 grow 300
1989 or obstruct_fom
1990 templayer fomfill_fine topbox
1991 slots 0 500 400 0 500 400 160 0
1992 and-not obstruct_fom_fine
1993 and topbox
1994 shrink 245
1995 grow 245
1996
1997#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1998 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1999 or fomfill_pass2
2000 or fomfill_coarse
2001 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2002 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2003
2004 layer POLYFILL polyfill_pass1
2005 or polyfill_coarse
2006 or polyfill_medium
2007 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2008 calma 28 28
2009
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2010#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2011# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2012# Note requirement that LI fill may not overlap (non-fill)
2013# diff or poly.
2014#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2015
2016 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2017 grow 2800
2018 or alldiff,allpoly
2019 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2020 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]2021 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]2022 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2023 and-not obstruct_li_coarse
2024 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2025 shrink 1495
2026 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2027
2028 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2029 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2030 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2031 grow 300
2032 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2033 grow 200
2034 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2035 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2036 and-not obstruct_li_medium
2037 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2038 shrink 745
2039 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2040
2041 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2042 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2043 grow 300
2044 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2045 grow 200
2046 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2047 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2048 and-not obstruct_li_fine
2049 and topbox
2050 shrink 285
2051 grow 285
2052
2053 layer LIFILL lifill_coarse
2054 or lifill_medium
2055 or lifill_fine
2056 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2057
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2058#---------------------------------------------------
2059# MET1 fill
2060#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2061
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2062 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2063 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2064 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2065 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2066 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2067 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2068 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2069 shrink 995
2070 grow 995
2071
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2072 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2073 grow 2800
2074 or met1fill_coarse
2075 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2076 templayer met1fill_medium topbox
2077 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2078 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2079 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2080 shrink 495
2081 grow 495
2082
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2083 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2084 grow 300
2085 or met1fill_coarse,met1fill_medium
2086 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2087 templayer met1fill_fine topbox
2088 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2089 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2090 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2091 shrink 285
2092 grow 285
2093
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2094 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2095 grow 100
2096 or met1fill_coarse,met1fill_medium,met1fill_fine
2097 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2098 templayer met1fill_veryfine topbox
2099 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2100 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2101 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2102 shrink 145
2103 grow 145
2104
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2105 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2106 or met1fill_medium
2107 or met1fill_fine
2108 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2109 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2110
2111#---------------------------------------------------
2112# MET2 fill
2113#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2114 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2116 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2117 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2118 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2119 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2120 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2121 shrink 995
2122 grow 995
2123
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2124 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2125 grow 2800
2126 or met2fill_coarse
2127 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2128 templayer met2fill_medium topbox
2129 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2130 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2131 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2132 shrink 495
2133 grow 495
2134
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2135 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2136 grow 300
2137 or met2fill_coarse,met2fill_medium
2138 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2139 templayer met2fill_fine topbox
2140 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2141 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2142 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2143 shrink 285
2144 grow 285
2145
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2146 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2147 grow 100
2148 or met2fill_coarse,met2fill_medium,met2fill_fine
2149 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2150 templayer met2fill_veryfine topbox
2151 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2152 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2153 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2154 shrink 145
2155 grow 145
2156
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2157 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2158 or met2fill_medium
2159 or met2fill_fine
2160 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2161 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2162
2163#---------------------------------------------------
2164# MET3 fill
2165#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2166 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2167 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2168 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2169 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2170 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2171 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2172 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2173 shrink 995
2174 grow 995
2175
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2176 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2177 grow 2700
2178 or met3fill_coarse
2179 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2180 templayer met3fill_medium topbox
2181 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2182 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2183 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2184 shrink 495
2185 grow 495
2186
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2187 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2188 grow 200
2189 or met3fill_coarse,met3fill_medium
2190 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2191 templayer met3fill_fine topbox
2192 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2193 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2194 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2195 shrink 285
2196 grow 285
2197
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2198 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2199 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2200 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2201 or met3fill_coarse,met3fill_medium,met3fill_fine
2202 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2203 templayer met3fill_veryfine topbox
2204 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2205 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2206 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2207 shrink 195
2208 grow 195
2209
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2210 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2211 or met3fill_medium
2212 or met3fill_fine
2213 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2214 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2215
2216#ifdef METAL5
2217#---------------------------------------------------
2218# MET4 fill
2219#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2220 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2221 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2222 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2223 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2224 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2225 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2226 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2227 shrink 995
2228 grow 995
2229
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2230 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2231 grow 2700
2232 or met4fill_coarse
2233 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2234 templayer met4fill_medium topbox
2235 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2236 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2237 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2238 shrink 495
2239 grow 495
2240
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2241 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2242 grow 200
2243 or met4fill_coarse,met4fill_medium
2244 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2245 templayer met4fill_fine topbox
2246 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2247 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2248 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2249 shrink 285
2250 grow 285
2251
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2252 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2253 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2254 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2255 or met4fill_coarse,met4fill_medium,met4fill_fine
2256 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2257 templayer met4fill_veryfine topbox
2258 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2259 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2260 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2261 shrink 195
2262 grow 195
2263
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2264 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2265 or met4fill_medium
2266 or met4fill_fine
2267 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2268 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2269
2270#---------------------------------------------------
2271# MET5 fill
2272#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2273 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2274 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2275 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2276 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2277 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2278 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2279 shrink 2495
2280 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2281
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2282 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2283 grow 1400
2284 or met5fill_coarse
2285 grow 1600
2286 templayer met5fill_medium topbox
2287 slots 0 3000 1600 0 3000 1600 1000 100
2288 and-not obstruct_m5_medium
2289 and topbox
2290 shrink 1495
2291 grow 1495
2292
2293 layer MET5FILL met5fill_coarse
2294 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2295 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2296#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2297
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2298end
2299
2300#-----------------------------------------------------------------------
2301cifinput
2302#-----------------------------------------------------------------------
2303# NOTE: All values in this section MUST be multiples of 25
2304# or else magic will scale below the allowed layout grid size
2305#-----------------------------------------------------------------------
2306
Tim Edwardsd7d8a102021-07-21 10:56:23 -0400[diff] [blame]2307style sky130 variants (vendor),()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2308 scalefactor 10 nanometers
2309 gridlimit 5
2310
2311 options ignore-unknown-layer-labels no-reconnect-labels
2312
2313#ifndef MIM
2314 ignore CAPM
2315 ignore CAPM2
2316#endif (!MIM)
2317#ifndef METAL5
2318 ignore MET4,VIA3
2319 ignore MET5,VIA4
2320#endif
2321 ignore NPC
2322 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2323 ignore CAPID
2324 ignore LDNTM
2325 ignore HVNTM
2326 ignore POLYMOD
2327 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2328 ignore FILLOBSPOLY
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2329 ignore OUTLINE
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2330
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2331 layer pnp NWELL,WELLTXT,WELLPIN
2332 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2333 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2334 variants (vendor)
2335 labels WELLTXT port
2336 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2337 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2338 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2339 labels WELLPIN port
2340
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2341 layer nwell NWELL,WELLTXT,WELLPIN
2342 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2343 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2344 variants (vendor)
2345 labels WELLTXT port
2346 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2347 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2348 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2349 labels WELLPIN port
2350
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2351 templayer nwellarea NWELL
2352 copyup nwelcheck
2353
2354 # Copy nwell areas up for diffusion checks
2355 templayer xnwelcheck nwelcheck
2356 copyup nwelcheck
2357
2358 templayer hvarea HVI
2359 copyup hvcheck
2360
2361 # Copy high-voltage (HVI) areas up for diffusion checks
2362 templayer xhvcheck hvcheck
2363 copyup hvcheck
2364
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2365 # Always draw pwell under p-tap and n-diff. This is not always
2366 # necessary but works better with deep nwell for correct extraction.
2367 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2368 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2369 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2370 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2371 grow 420
2372 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2373 variants (vendor)
2374 labels SUBTXT port
2375 variants ()
2376 labels SUBTXT text
2377 variants *
2378 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2379
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2380 layer dnwell DNWELL
2381 labels DNWELL
2382
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]2383 layer isosub SUBCUT
2384 labels SUBCUT
2385
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2386 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2387 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2388 and NPNID
2389
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2390 layer rpw PWRES
2391 and DNWELL
2392 labels PWRES
2393
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2394 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2395 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2396 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2397 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2398 and-not DIODE
2399 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2400 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2401 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2402 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2403 copyup ndifcheck
2404 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2405 variants (vendor)
2406 labels DIFFTXT port
2407 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2408 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2409 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2410 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2411
2412 layer ndiff ndiffarea
2413
2414 # Copy ndiff areas up for contact checks
2415 templayer xndifcheck ndifcheck
2416 copyup ndifcheck
2417
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2418 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2419 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2420 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2421 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2422 and-not DIODE
2423 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2424 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2425 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2426 copyup ndifcheck
2427 labels DIFF
2428 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2429 variants (vendor)
2430 labels DIFFTXT port
2431 variants ()
2432 labels DIFFTXT text
2433 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2434 labels DIFFPIN port
2435
2436 layer mvndiff mvndiffarea
2437
2438 # Copy ndiff areas up for contact checks
2439 templayer mvxndifcheck mvndifcheck
2440 copyup mvndifcheck
2441
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2442 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2443 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2444 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2445 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2446 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2447 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2448 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2449 and-not LVTN
2450 labels DIFF
2451
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2452 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2453 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2454 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2455 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2456 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2457 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2458 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2459 and LVTN
2460 labels DIFF
2461
2462 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2463 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2464 and-not HVI,hvcheck
2465 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2466 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2467
2468 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2469 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2470 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2471 labels DIFF
2472
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2473 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2474 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2475 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2476 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2477 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2478 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2479 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2480 copyup pdifcheck
2481 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2482 variants (vendor)
2483 labels DIFFTXT port
2484 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2485 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2486 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2487 labels DIFFPIN port
2488
2489 layer pdiff pdiffarea
2490
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2491 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2492 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2493 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2494 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2495 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2496 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2497 and-not LVTN
2498 labels DIFF
2499
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2500 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2501 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2502 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2503 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2504 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2505 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2506 and LVTN
2507 labels DIFF
2508
2509 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2510 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2511 and HVI,hvcheck
2512 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2513 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2514
2515 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2516 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2517 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2518 labels DIFF
2519
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2520 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2521 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2522 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2523 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2524 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2525 and-not DIODE
2526 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2527 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2528 copyup mvpdifcheck
2529 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2530 variants (vendor)
2531 labels DIFFTXT port
2532 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2533 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2534 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2535 labels DIFFPIN port
2536
2537 layer mvpdiff mvpdiffarea
2538
2539 # Copy pdiff areas up for contact checks
2540 templayer xpdifcheck pdifcheck
2541 copyup pdifcheck
2542
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2543 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2544 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2545 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2546 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2547 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2548 and-not LVTN
2549 and-not HVTP
2550 and DIODE
2551 labels DIFF
2552
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2553 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2554 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2555 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2556 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2557 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2558 and LVTN
2559 and-not HVTP
2560 and DIODE
2561 labels DIFF
2562
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2563 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2564 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2565 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2566 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2567 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2568 and-not LVTN
2569 and HVTP
2570 and DIODE
2571 labels DIFF
2572
2573 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2574 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2575 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2576 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2577
2578 # Define pfet areas as known pdiff, regardless of the presence of a well.
2579
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2580 templayer pfetarea DIFF,barediff
2581 and POLY
2582 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2583 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2584 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2585
2586 layer pfet pfetarea
2587 and-not LVTN
2588 and-not HVTP
2589 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2590 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2591 labels DIFF
2592
2593 layer scpfet pfetarea
2594 and-not LVTN
2595 and-not HVTP
2596 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2597 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2598 labels DIFF
2599
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2600 layer scpfethvt pfetarea
2601 and-not LVTN
2602 and HVTP
2603 and STDCELL
2604 labels DIFF
2605
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2606 layer ppu pfetarea
2607 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2608 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2609 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2610 # Shrink-grow operation eliminates the smaller parasitie device
2611 # shrink 70
2612 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2613 labels DIFF
2614
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2615 layer pfetlvt pfetarea
2616 and LVTN
2617 labels DIFF
2618
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2619 layer pfetmvt pfetarea
2620 and HVTR
2621 labels DIFF
2622
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2623 layer pfethvt pfetarea
2624 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2625 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2626 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2627 labels DIFF
2628
2629 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2630 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2631 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2632 grow 180
2633
2634 # Copy mvpdiff areas up for contact checks
2635 templayer mvxpdifcheck mvpdifcheck
2636 copyup mvpdifcheck
2637
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2638 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2639 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2640 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2641 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2642 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2643 and DIODE
2644 labels DIFF
2645
2646 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2647 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2648 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2649 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2650
2651 # Define pfet areas as known pdiff,
2652 # regardless of the presence of a
2653 # well.
2654
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2655 templayer mvpfetarea DIFF,barediff
2656 and POLY
2657 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2658 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2659 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2660
2661 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2662 and-not ESDID
2663 labels DIFF
2664
2665 layer mvpfetesd mvpfetarea
2666 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2667 labels DIFF
2668
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2669 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2670 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2671 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2672 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2673 and-not DIODE
2674 and-not DIFFRES
2675 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2676 variants (vendor)
2677 labels DIFFTXT port
2678 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2679 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2680 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2681 labels DIFFPIN port
2682
2683 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2684 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2685 and NWELL,nwelcheck
2686 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2687 labels DIFF
2688
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2689 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2690 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2691 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2692 and-not PSDM
2693 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2694 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2695 and-not LVTN
2696 and-not SONOS
2697 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2698 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2699 labels DIFF
2700
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2701 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2702 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2703 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2704 and-not PSDM
2705 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2706 and-not NWELL,nwelcheck
2707 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2708 and-not LVTN
2709 and-not SONOS
2710 and STDCELL
2711 labels DIFF
2712
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2713 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2714 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2715 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2716 and-not PSDM
2717 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2718 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2719 and COREID
2720 labels DIFF
2721
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2722 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2723 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2724 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2725 and-not PSDM
2726 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2727 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2728 and COREID
2729 # Shrink-grow operation eliminates the smaller npass device
2730 shrink 70
2731 grow 70
2732 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2733
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2734 # Devices abutting tap under gate are officially npd, not npass
2735 layer npd TAP
2736 grow 100
2737 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2738 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2739 and-not PSDM
2740 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2741 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2742 and COREID
2743 labels DIFF
2744
2745 layer nfetlvt DIFF,barediff
2746 and POLY
2747 or baretrans
2748 and-not PSDM
2749 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2750 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2751 and LVTN
2752 and-not SONOS
2753 labels DIFF
2754
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2755 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2756 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2757 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2758 and-not PSDM
2759 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2760 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2761 and LVTN
2762 and SONOS
2763 labels DIFF
2764
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2765 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2766 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2767 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2768 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2769 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2770 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2771 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2772 copyup nsubcheck
2773
2774 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2775 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2776
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2777 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2778 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2779 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2780 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2781 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2782 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2783
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2784 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2785 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2786 and POLY
2787 and COREID
2788 labels TAP
2789
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2790 templayer nsdexpand nsdarea
2791 grow 500
2792
2793 # Copy nsub areas up for contact checks
2794 templayer xnsubcheck nsubcheck
2795 copyup nsubcheck
2796
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2797 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2798 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2799 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2800 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2801 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2802 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2803 and-not pfetexpand
2804 copyup psubcheck
2805
2806 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2807 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2809 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2810 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2811 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2812 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2813 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2814 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2815
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2816 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2817 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2818 and POLY
2819 and COREID
2820 labels TAP
2821
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2822 templayer psdexpand psdarea
2823 grow 500
2824
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2825 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2826 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2827 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2828 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2829 and mvpfetexpand
2830 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2831 variants (vendor)
2832 labels DIFFTXT port
2833 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2834 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2835 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2836 labels DIFFPIN port
2837
2838 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2839 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2840 and NWELL,nwelcheck
2841 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2842 and-not mvrdpioedge
2843 labels DIFF
2844
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2845 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2846 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2847 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2848 and-not PSDM
2849 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2850 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2851 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2852 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2853
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2854 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2855 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2856 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2857 and-not PSDM
2858 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2859 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2860 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2861 and-not mvnfetarea
2862
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2863 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2864 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2865 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2866 and-not PSDM
2867 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2868 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2869 and ESDID
2870 and-not mvnnfetarea
2871 labels DIFF
2872
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2873 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2874 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2875 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2876 and-not PSDM
2877 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2878 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2879 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2880 and-not mvnnfetarea
2881 labels DIFF
2882
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2883 layer nnfet mvnnfetarea
2884 and LVID
2885 labels DIFF
2886
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2887 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2888 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2889 labels DIFF
2890
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2891 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2892 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2893 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2894 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2895 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2896 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2897 copyup mvnsubcheck
2898
2899 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2900 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2901
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2902 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2903 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2904 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2905 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2906 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2907
2908 templayer mvnsdexpand mvnsdarea
2909 grow 500
2910
2911 # Copy nsub areas up for contact checks
2912 templayer mvxnsubcheck mvnsubcheck
2913 copyup mvnsubcheck
2914
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2915 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2916 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2917 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2918 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2919 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2920 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2921 and-not mvpfetexpand
2922 copyup mvpsubcheck
2923
2924 layer mvpsd mvpsdarea
2925 labels DIFF
2926
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2927 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2928 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2929 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2930 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2931 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2932
2933 templayer mvpsdexpand mvpsdarea
2934 grow 500
2935
2936 # Copy psub areas up for contact checks
2937 templayer xpsubcheck psubcheck
2938 copyup psubcheck
2939
2940 templayer mvxpsubcheck mvpsubcheck
2941 copyup mvpsubcheck
2942
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2943 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2944 and-not PSDM
2945 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2946 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2947 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2948 and-not pfetexpand
2949 and psdexpand
2950
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2951 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2952 and-not PSDM
2953 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2954 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2955 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2956 and nsdexpand
2957
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2958 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2959 and-not PSDM
2960 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2961 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2962 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2963 and-not mvpfetexpand
2964 and mvpsdexpand
2965
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2966 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2967 and-not PSDM
2968 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2969 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2970 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2971 and mvnsdexpand
2972
2973 templayer hresarea POLY
2974 and RPM
2975 grow 3000
2976
2977 templayer uresarea POLY
2978 and URPM
2979 grow 3000
2980
2981 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2982 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2983 grow 3000
2984
2985 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2986 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2987 grow 3000
2988
2989 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2990
2991 layer pfet POLY
2992 and DIFF
2993 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2994 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2995 and-not STDCELL
2996
2997 layer scpfet POLY
2998 and DIFF
2999 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3000 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3001 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3002 and STDCELL
3003
3004 layer scpfethvt POLY
3005 and DIFF
3006 and diffresarea
3007 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3008 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3009 and STDCELL
3010
3011 templayer xpolyterm RPM,URPM
3012 and POLY
3013 and-not POLYRES
3014 # add back the 0.06um contact surround in the direction of the resistor
3015 grow 60
3016 and POLY
3017
3018 layer xpc xpolyterm
3019
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3020 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3021 and-not POLYRES
3022 and-not POLYSHORT
3023 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3024 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3025 and-not RPM
3026 and-not URPM
3027 copyup polycheck
3028
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3029 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3030 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3031 variants (vendor)
3032 labels POLYTXT port
3033 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3034 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3035 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3036 labels POLYPIN port
3037
3038 # Copy (non-resistor) poly areas up for contact checks
3039 templayer xpolycheck polycheck
3040 copyup polycheck
3041
3042 layer mrp1 POLY
3043 and POLYRES
3044 and-not RPM
3045 and-not URPM
3046 labels POLY
3047
3048 layer rmp POLY
3049 and POLYSHORT
3050 labels POLY
3051
3052 layer xhrpoly POLY
3053 and POLYRES
3054 and RPM
3055 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3056 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3057 and NPC
3058 and-not xpolyterm
3059 labels POLY
3060
3061 layer uhrpoly POLY
3062 and POLYRES
3063 and URPM
3064 and-not RPM
3065 and NPC
3066 and-not xpolyterm
3067 labels POLY
3068
3069 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3070 or barecont
3071 and LI
3072 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3073 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3074 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3075 and-not NWELL,nwelcheck
3076 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3077
3078 layer ndc ndcbase
3079 grow 85
3080 shrink 85
3081 shrink 85
3082 grow 85
3083 or ndcbase
3084 labels CONT
3085
3086 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3087 or barecont
3088 and LI
3089 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3090 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3091 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3092 and NWELL,nwelcheck
3093 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3094
3095 layer nsc nscbase
3096 grow 85
3097 shrink 85
3098 shrink 85
3099 grow 85
3100 or nscbase
3101 labels CONT
3102
3103 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3104 or barecont
3105 and LI
3106 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3107 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3108 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3109 and NWELL,nwelcheck
3110 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3111
3112 layer pdc pdcbase
3113 grow 85
3114 shrink 85
3115 shrink 85
3116 grow 85
3117 or pdcbase
3118 labels CONT
3119
3120 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3121 or barecont
3122 and LI
3123 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3124 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3125 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3126 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3127 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3128
3129 layer pdc pdcnowell
3130 grow 85
3131 shrink 85
3132 shrink 85
3133 grow 85
3134 or pdcnowell
3135 labels CONT
3136
3137 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3138 or barecont
3139 and LI
3140 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3141 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3142 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3143 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3144 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3145 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3146
3147 layer psc pscbase
3148 grow 85
3149 shrink 85
3150 shrink 85
3151 grow 85
3152 or pscbase
3153 labels CONT
3154
3155 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3156 or barecont
3157 and LI
3158 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3159 and POLY
3160 and-not DIFF
3161 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3162
3163 layer pc pcbase
3164 grow 85
3165 shrink 85
3166 shrink 85
3167 grow 85
3168 or pcbase
3169 labels CONT
3170
3171 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3172 or barecont
3173 and LI
3174 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3175 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3176 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3177 and DIODE
3178 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3179 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3180 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3181 and-not LVTN
3182
3183 layer ndic ndicbase
3184 grow 85
3185 shrink 85
3186 shrink 85
3187 grow 85
3188 or ndicbase
3189 labels CONT
3190
3191 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3192 or barecont
3193 and LI
3194 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3195 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3196 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3197 and DIODE
3198 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3199 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3200 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3201 and LVTN
3202
3203 layer ndilvtc ndilvtcbase
3204 grow 85
3205 shrink 85
3206 shrink 85
3207 grow 85
3208 or ndilvtcbase
3209 labels CONT
3210
3211 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3212 or barecont
3213 and LI
3214 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3215 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3216 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3217 and DIODE
3218 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3219 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3220 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3221 and-not LVTN
3222 and-not HVTP
3223
3224 layer pdic pdicbase
3225 grow 85
3226 shrink 85
3227 shrink 85
3228 grow 85
3229 or pdicbase
3230 labels CONT
3231
3232 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3233 or barecont
3234 and LI
3235 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3236 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3237 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3238 and DIODE
3239 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3240 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3241 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3242 and LVTN
3243 and-not HVTP
3244
3245 layer pdilvtc pdilvtcbase
3246 grow 85
3247 shrink 85
3248 shrink 85
3249 grow 85
3250 or pdilvtcbase
3251 labels CONT
3252
3253 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3254 or barecont
3255 and LI
3256 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3257 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3258 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3259 and DIODE
3260 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3261 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3262 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3263 and-not LVTN
3264 and HVTP
3265
3266 layer pdihvtc pdihvtcbase
3267 grow 85
3268 shrink 85
3269 shrink 85
3270 grow 85
3271 or pdihvtcbase
3272 labels CONT
3273
3274 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3275 or barecont
3276 and LI
3277 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3278 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3279 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3280 and-not NWELL,nwelcheck
3281 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3282
3283 layer mvndc mvndcbase
3284 grow 85
3285 shrink 85
3286 shrink 85
3287 grow 85
3288 or mvndcbase
3289 labels CONT
3290
3291 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3292 or barecont
3293 and LI
3294 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3295 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3296 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3297 and NWELL,nwelcheck
3298 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3299
3300 layer mvnsc mvnscbase
3301 grow 85
3302 shrink 85
3303 shrink 85
3304 grow 85
3305 or mvnscbase
3306 labels CONT
3307
3308 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3309 or barecont
3310 and LI
3311 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3312 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3313 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3314 and NWELL,nwelcheck
3315 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3316
3317 layer mvpdc mvpdcbase
3318 grow 85
3319 shrink 85
3320 shrink 85
3321 grow 85
3322 or mvpdcbase
3323 labels CONT
3324
3325 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3326 or barecont
3327 and LI
3328 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3329 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3330 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3331 and mvpfetexpand
3332 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3333 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3334
3335 layer mvpdc mvpdcnowell
3336 grow 85
3337 shrink 85
3338 shrink 85
3339 grow 85
3340 or mvpdcnowell
3341 labels CONT
3342
3343 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3344 or barecont
3345 and LI
3346 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3347 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3348 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3349 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3350 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3351 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3352
3353 layer mvpsc mvpscbase
3354 grow 85
3355 shrink 85
3356 shrink 85
3357 grow 85
3358 or mvpscbase
3359 labels CONT
3360
3361 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3362 or barecont
3363 and LI
3364 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3365 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3366 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3367 and DIODE
3368 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3369 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3370 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3371 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3372
3373 layer mvndic mvndicbase
3374 grow 85
3375 shrink 85
3376 shrink 85
3377 grow 85
3378 or mvndicbase
3379 labels CONT
3380
3381 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3382 or barecont
3383 and LI
3384 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3385 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3386 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3387 and DIODE
3388 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3389 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3390 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3391 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3392
3393 layer nndic nndicbase
3394 grow 85
3395 shrink 85
3396 shrink 85
3397 grow 85
3398 or nndicbase
3399 labels CONT
3400
3401 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3402 or barecont
3403 and LI
3404 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3405 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3406 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3407 and DIODE
3408 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3409 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3410 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3411
3412 layer mvpdic mvpdicbase
3413 grow 85
3414 shrink 85
3415 shrink 85
3416 grow 85
3417 or mvpdicbase
3418 labels CONT
3419
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3420 layer fomfill FOMFILL
3421 labels FOMFILL
3422
3423 layer polyfill POLYFILL
3424 labels POLYFILL
3425
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3426 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3427 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3428 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3429 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3430 variants (vendor)
3431 labels LITXT port
3432 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3433 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3434 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3435 labels LIPIN port
3436
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3437 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3438 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3439 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3440 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3441 variants (vendor)
3442 labels LITXT port
3443 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3444 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3445 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3446 labels LIPIN port
3447
3448 layer rli LI
3449 and LIRES,LISHORT
3450 labels LIRES,LISHORT
3451
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3452 layer lifill LIFILL
3453 labels LIFILL
3454
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3455 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3456 grow 95
3457 shrink 95
3458 shrink 85
3459 grow 85
3460 or MCON
3461 labels MCON
3462
3463 layer m1 MET1,MET1TXT,MET1PIN
3464 and-not MET1RES,MET1SHORT
3465 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3466 variants (vendor)
3467 labels MET1TXT port
3468 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3469 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3470 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3471 labels MET1PIN port
3472
3473 layer rm1 MET1
3474 and MET1RES,MET1SHORT
3475 labels MET1RES,MET1SHORT
3476
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3477 layer m1fill MET1FILL
3478 labels MET1FILL
3479
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3480#ifdef MIM
3481 layer mimcap MET3
3482 and CAPM
3483 labels CAPM
3484
3485 layer mimcc VIA3
3486 and CAPM
3487 grow 60
3488 grow 40
3489 shrink 40
3490 labels CAPM
3491
3492 layer mimcap2 MET4
3493 and CAPM2
3494 labels CAPM2
3495
3496 layer mim2cc VIA4
3497 and CAPM2
3498 grow 190
3499 grow 210
3500 shrink 210
3501 labels CAPM2
3502
3503#endif (MIM)
3504
3505 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3506 and-not COREID
3507 grow 5
3508 or VIA1
3509 grow 50
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3510
3511 layer m2c m2cbase
3512 grow 30
3513 shrink 30
3514 shrink 130
3515 grow 130
3516 or m2cbase
3517
3518 layer m2 MET2,MET2TXT,MET2PIN
3519 and-not MET2RES,MET2SHORT
3520 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3521 variants (vendor)
3522 labels MET2TXT port
3523 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3524 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3525 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3526 labels MET2PIN port
3527
3528 layer rm2 MET2
3529 and MET2RES,MET2SHORT
3530 labels MET2RES,MET2SHORT
3531
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3532 layer m2fill MET2FILL
3533 labels MET2FILL
3534
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3535 templayer m3cbase VIA2
3536 grow 40
3537
3538 layer m3c m3cbase
3539 grow 60
3540 shrink 60
3541 shrink 140
3542 grow 140
3543 or m3cbase
3544
3545 layer m3 MET3,MET3TXT,MET3PIN
3546 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3547 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3548 variants (vendor)
3549 labels MET3TXT port
3550 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3551 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3552 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3553 labels MET3PIN port
3554
3555 layer rm3 MET3
3556 and MET3RES,MET3SHORT
3557 labels MET3RES,MET3SHORT
3558
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3559 layer m3fill MET3FILL
3560 labels MET3FILL
3561
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3562#ifdef (METAL5)
3563
3564 templayer via3base VIA3
3565#ifdef MIM
3566 and-not CAPM
3567#endif (MIM)
3568 grow 60
3569
3570 layer via3 via3base
3571 grow 40
3572 shrink 40
3573 shrink 160
3574 grow 160
3575 or via3base
3576
3577 layer m4 MET4,MET4TXT,MET4PIN
3578 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3579 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3580 variants (vendor)
3581 labels MET4TXT port
3582 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3583 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3584 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3585 labels MET4PIN port
3586
3587 layer rm4 MET4
3588 and MET4RES,MET4SHORT
3589 labels MET4RES,MET4SHORT
3590
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3591 layer m4fill MET4FILL
3592 labels MET4FILL
3593
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3594 layer m5 MET5,MET5TXT,MET5PIN
3595 and-not MET5RES,MET5SHORT
3596 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3597 variants (vendor)
3598 labels MET5TXT port
3599 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3600 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3601 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3602 labels MET5PIN port
3603
3604 layer rm5 MET5
3605 and MET5RES,MET5SHORT
3606 labels MET5RES,MET5SHORT
3607
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3608 layer m5fill MET5FILL
3609 labels MET5FILL
3610
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3611 templayer via4base VIA4
3612#ifdef MIM
3613 and-not CAPM2
3614#endif (MIM)
3615 grow 190
3616
3617 layer via4 via4base
3618 grow 210
3619 shrink 210
3620 shrink 590
3621 grow 590
3622 or via4base
3623#endif (METAL5)
3624
3625#ifdef REDISTRIBUTION
3626 layer metrdl RDL,RDLTXT,RDLPIN
3627 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3628 variants (vendor)
3629 labels RDLTXT port
3630 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3631 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3632 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3633 labels RDLPIN port
3634#endif
3635
3636 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3637 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3638 # the next layer up
3639
3640 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3641 and-not PSDM
3642 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3643 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3644 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3645
3646 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3647 and-not PSDM
3648 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3649 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3650 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3651 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3652
3653 # Handle contacts found by copyup
3654
3655 templayer ndiccopy CONT
3656 and LI
3657 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3658 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3659 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3660
3661 layer ndic ndiccopy
3662 grow 85
3663 shrink 85
3664 shrink 85
3665 grow 85
3666 or ndiccopy
3667 labels CONT
3668
3669 templayer mvndiccopy CONT
3670 and LI
3671 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3672 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3673 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3674
3675 layer mvndic mvndiccopy
3676 grow 85
3677 shrink 85
3678 shrink 85
3679 grow 85
3680 or mvndiccopy
3681 labels CONT
3682
3683 templayer pdiccopy CONT
3684 and LI
3685 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3686 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3687 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3688
3689 layer pdic pdiccopy
3690 grow 85
3691 shrink 85
3692 shrink 85
3693 grow 85
3694 or pdiccopy
3695 labels CONT
3696
3697 templayer mvpdiccopy CONT
3698 and LI
3699 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3700 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3701 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3702
3703 layer mvpdic mvpdiccopy
3704 grow 85
3705 shrink 85
3706 shrink 85
3707 grow 85
3708 or mvpdiccopy
3709 labels CONT
3710
3711 templayer ndccopy CONT
3712 and ndifcheck
3713
3714 layer ndc ndccopy
3715 grow 85
3716 shrink 85
3717 shrink 85
3718 grow 85
3719 or ndccopy
3720 labels CONT
3721
3722 templayer mvndccopy CONT
3723 and mvndifcheck
3724
3725 layer mvndc mvndccopy
3726 grow 85
3727 shrink 85
3728 shrink 85
3729 grow 85
3730 or mvndccopy
3731 labels CONT
3732
3733 templayer pdccopy CONT
3734 and pdifcheck
3735
3736 layer pdc pdccopy
3737 grow 85
3738 shrink 85
3739 shrink 85
3740 grow 85
3741 or pdccopy
3742 labels CONT
3743
3744 templayer mvpdccopy CONT
3745 and mvpdifcheck
3746
3747 layer mvpdc mvpdccopy
3748 grow 85
3749 shrink 85
3750 shrink 85
3751 grow 85
3752 or mvpdccopy
3753 labels CONT
3754
3755 templayer pccopy CONT
3756 and polycheck
3757
3758 layer pc pccopy
3759 grow 85
3760 shrink 85
3761 shrink 85
3762 grow 85
3763 or pccopy
3764 labels CONT
3765
3766 templayer nsccopy CONT
3767 and nsubcheck
3768
3769 layer nsc nsccopy
3770 grow 85
3771 shrink 85
3772 shrink 85
3773 grow 85
3774 or nsccopy
3775 labels CONT
3776
3777 templayer mvnsccopy CONT
3778 and mvnsubcheck
3779
3780 layer mvnsc mvnsccopy
3781 grow 85
3782 shrink 85
3783 shrink 85
3784 grow 85
3785 or mvnsccopy
3786 labels CONT
3787
3788 templayer psccopy CONT
3789 and psubcheck
3790
3791 layer psc psccopy
3792 grow 85
3793 shrink 85
3794 shrink 85
3795 grow 85
3796 or psccopy
3797 labels CONT
3798
3799 templayer mvpsccopy CONT
3800 and mvpsubcheck
3801
3802 layer mvpsc mvpsccopy
3803 grow 85
3804 shrink 85
3805 shrink 85
3806 grow 85
3807 or mvpsccopy
3808 labels CONT
3809
3810 # Find contacts not covered in
3811 # metal and pull them into the
3812 # next layer up
3813
3814 templayer gencont CONT
3815 and LI
3816 and-not DIFF,TAP
3817 and-not POLY
3818 and-not DIODE
3819 and-not nsubcheck
3820 and-not psubcheck
3821 and-not mvnsubcheck
3822 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3823 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3824 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3825
3826 templayer barecont CONT
3827 and-not LI
3828 and-not nsubcheck
3829 and-not psubcheck
3830 and-not mvnsubcheck
3831 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3832 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3833 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3834
3835 layer glass GLASS,PADTXT,PADPIN
3836 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3837 variants (vendor)
3838 labels PADTXT port
3839 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3840 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3841 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3842 labels PADPIN port
3843
3844 templayer boundary BOUND,STDCELL,PADCELL
3845 boundary
3846
3847 layer comment LVSTEXT
3848 labels LVSTEXT text
3849
3850 layer comment TTEXT
3851 labels TTEXT text
3852
3853 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3854 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3855
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3856 layer obsactive FILLOBSFOM
3857
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3858# MOS Varactor
3859
3860 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3861 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3862 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3863 and NWELL,nwelcheck
3864 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3865 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3866 # NOTE: Else forms a varactor that is not in the vendor netlist.
3867 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3868 labels POLY
3869
3870 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3871 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3872 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3873 and NWELL,nwelcheck
3874 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3875 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3876 labels POLY
3877
3878 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3879 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3880 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3881 and NWELL,nwelcheck
3882 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3883 labels POLY
3884
3885 calma NWELL 64 20
3886 calma DIFF 65 20
3887 calma DNWELL 64 18
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]3888 calma SUBCUT 81 53
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3889 calma PWRES 64 13
3890 calma TAP 65 44
3891 # LVTN
3892 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3893 # HVTR
3894 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3895 # HVTP
3896 calma HVTP 78 44
3897 # SONOS (TUNM)
3898 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3899 # NSDM (NPLUS)
3900 calma NSDM 93 44
3901 # PSDM (PPLUS)
3902 calma PSDM 94 20
3903 # HVI (THKOX)
3904 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3905 # NPC
3906 calma NPC 95 20
3907 # P+ POLY MASK
3908 calma RPM 86 20
3909 calma URPM 79 20
3910 calma LDNTM 11 44
3911 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3912 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3913 calma POLYRES 66 13
3914 # Diffusion resistor ID mark
3915 calma DIFFRES 65 13
3916 calma POLY 66 20
3917 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]3918 # 3.3V native FET ID mark
3919 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3920 # Diode ID mark
3921 calma DIODE 81 23
3922 # Bipolar NPN mark
3923 calma NPNID 82 20
3924 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3925 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3926 # Capacitor ID
3927 calma CAPID 82 64
3928 # Core area ID mark
3929 calma COREID 81 2
3930 # Standard cell ID mark
3931 calma STDCELL 81 4
3932 # Padframe cell ID mark
3933 calma PADCELL 81 3
3934 # Seal ring ID mark
3935 calma SEALID 81 1
3936 # Low tap density ID mark
3937 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3938 # ESD area ID
3939 calma ESDID 81 19
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]3940 calma OUTLINE 236 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3941
3942 # LICON
3943 calma CONT 66 44
3944 calma LI 67 20
3945 calma MCON 67 44
3946
3947 calma MET1 68 20
3948 calma VIA1 68 44
3949 calma MET2 69 20
3950 calma VIA2 69 44
3951 calma MET3 70 20
3952#ifdef METAL5
3953 calma VIA3 70 44
3954 calma MET4 71 20
3955 calma VIA4 71 44
3956 calma MET5 72 20
3957#endif
3958#ifdef REDISTRIBUTION
3959 calma RDL 74 20
3960#endif
3961 calma GLASS 76 20
3962
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3963 calma SUBTXT 64 59
3964 calma PADTXT 76 5
3965 calma DIFFTXT 65 6
3966 calma TAPTXT 65 5
3967 calma WELLTXT 64 5
3968 calma LITXT 67 5
3969 calma POLYTXT 66 5
3970 calma MET1TXT 68 5
3971 calma MET2TXT 69 5
3972 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3973#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3974 calma MET4TXT 71 5
3975 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3976#endif
3977#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3978 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3979#endif
3980
3981 calma LIRES 67 13
3982 calma MET1RES 68 13
3983 calma MET2RES 69 13
3984 calma MET3RES 70 13
3985#ifdef METAL5
3986 calma MET4RES 71 13
3987 calma MET5RES 72 13
3988#endif
3989
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3990 calma LIFILL 56 28
3991 calma MET1FILL 36 28
3992 calma MET2FILL 41 28
3993 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3994#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3995 calma MET4FILL 51 28
3996 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3997#endif
3998
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3999 calma POLYSHORT 66 15
4000 calma LISHORT 67 15
4001 calma MET1SHORT 68 15
4002 calma MET2SHORT 69 15
4003 calma MET3SHORT 70 15
4004#ifdef METAL5
4005 calma MET4SHORT 71 15
4006 calma MET5SHORT 72 15
4007#endif
4008
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4009 calma SUBPIN 122 16
4010 calma PADPIN 76 16
4011 calma DIFFPIN 65 16
4012 calma POLYPIN 66 16
4013 calma WELLPIN 64 16
4014 calma LIPIN 67 16
4015 calma MET1PIN 68 16
4016 calma MET2PIN 69 16
4017 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4018#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4019 calma MET4PIN 71 16
4020 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4021#endif
4022#ifdef REDISTRIBUTION
4023 calma RDLPIN 74 16
4024#endif
4025
4026 calma BOUND 235 4
4027
4028 calma LVSTEXT 83 44
4029
4030#ifdef (MIM)
4031 calma CAPM 89 44
4032 calma CAPM2 97 44
4033#endif (MIM)
4034
4035 calma FILLOBSM1 62 24
4036 calma FILLOBSM2 105 52
4037 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]4038 calma FILLOBSM4 112 4
4039 calma FILLOBSFOM 22 24
4040 calma FILLOBSPOLY 33 24
4041
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4042 calma FOMFILL 23 28
4043 calma POLYFILL 28 28
4044 calma LIFILL 56 28
4045 calma MET1FILL 36 28
4046 calma MET2FILL 41 28
4047 calma MET3FILL 34 28
4048 calma MET4FILL 51 28
4049 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4050
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4051#-----------------------------------------------------------------------
4052
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4053style rdlimport
4054 # This style is for reading shapes generated with the RDL layers
4055
4056 scalefactor 10 nanometers
4057 gridlimit 5
4058
4059 options ignore-unknown-layer-labels no-reconnect-labels
4060
4061 layer mrdl RDL
4062 layer mrdlc RDLC
4063
4064 calma RDL 10 0
4065 calma RDLC 20 0
4066
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4067end
4068
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4069#-----------------------------------------------------
4070# Digital flow maze router cost parameters
4071#-----------------------------------------------------
4072
4073mzrouter
4074end
4075
4076#-----------------------------------------------------
4077# Vendor DRC rules
4078#-----------------------------------------------------
4079
4080drc
4081
4082 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4083 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4084 cifstyle drc
4085
4086 variants (fast),(full)
4087
4088#-----------------------------
4089# DNWELL
4090#-----------------------------
4091
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4092 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4093 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4094 spacing allnwell dnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4095 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4096
4097 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4098 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4099 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4100 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4101 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4102
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4103 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4104 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4105 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4106
4107#-----------------------------
4108# NWELL
4109#-----------------------------
4110
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4111 width allnwell 840 "N-well width < %d (nwell.1)"
4112 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4113
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4114 variants (full)
4115 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4116 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4117
4118 cifspacing mvnwell lvnwell 2000 touching_illegal \
4119 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4120 cifspacing mvnwell mvnwell 2000 touching_ok \
4121 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4122 variants (fast),(full)
4123
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4124#-----------------------------
4125# DIFF
4126#-----------------------------
4127
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4128 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4129 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4130 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4131 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4132
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4133 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4134 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4135 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4136 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4137 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4138 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4139 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4140 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwardsada35632021-08-19 21:00:32 -0400[diff] [blame]4141 spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \
4142 "LV to MV Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4143 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4144 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4145 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4146 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4147 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4148 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4149 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4150 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4151 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4152 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4153 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4154 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4155 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4156 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4157 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4158 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4159 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4160 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4161 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4162 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4163 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4164 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4165 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4166 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4167 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4168 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4169 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4170 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4171
4172variants (full)
4173 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4174 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]4175 cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
4176 "HVI to HVI or LV nwell spacing < %d (hvi.5)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4177variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4178
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4179 spacing allnfets allpactivenonfet 270 touching_illegal \
4180 "nFET cannot abut P-diffusion (diff/tap.3)"
4181 spacing allpfets allnactivenonfet 270 touching_illegal \
4182 "pFET cannot abut N-diffusion (diff/tap.3)"
4183
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4184 # Butting junction rules
4185 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4186 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4187 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4188 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4189 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4190 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4191 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4192 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4193
4194 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4195 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4196 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4197 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4198 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4199 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4200 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4201 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4202
4203 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4204 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4205 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4206
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4207 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4208 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4209
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4210 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4211
4212 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4213 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4214
4215 # Latchup rules
4216 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4217 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4218 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4219 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4220 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4221 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4222
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4223 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4224
4225#-----------------------------
4226# POLY
4227#-----------------------------
4228
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4229 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4230 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4231
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4232 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4233 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4234 75 corner_ok allfets \
4235 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4236 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4237 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4238 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4239 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4240 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4241 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4242 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4243 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4244 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4245 rect_only allfets "No bends in transistors (poly.11)"
4246 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4247 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4248 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4249 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4250 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4251
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4252 variants (fast)
4253
4254 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4255 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4256 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4257 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4258 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4259 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4260
4261 # Minimum width requirement means actual spacing from res to ndiff has to be
4262 # constructed from mask rules. These supercede the simpler checks.
4263
4264 variants (full)
4265
4266 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4267 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4268 cifmaxwidth rpm_poly_check 0 bend_illegal \
4269 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4270 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4271 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4272
Tim Edwards75dea452021-05-08 15:55:26 -0400[diff] [blame]4273 variants (fast),(full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4274
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4275 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4276
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4277#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4278# HVTP
4279#--------------------------------------------------------------------
4280
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4281 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4282 360 touching_illegal \
4283 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4284
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4285 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4286 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4287
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4288#--------------------------------------------------------------------
4289# LVTN
4290#--------------------------------------------------------------------
4291
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4292 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4293 allfetsnolvt 360 touching_illegal \
4294 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4295
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4296 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4297 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4298 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4299
4300 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4301 edge4way allfetsnolvt allactivenonfet 415 \
4302 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4303 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4304
4305#--------------------------------------------------------------------
4306# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4307#--------------------------------------------------------------------
4308
4309# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4310
4311#--------------------------------------------------------------------
4312# CONT (LICON, contact between poly/diff and LI)
4313#--------------------------------------------------------------------
4314
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4315 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4316 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4317 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4318 width psc/li 170 "P-tap contact width < %d (licon.1)"
4319 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4320 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4321 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4322
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4323 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4324 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4325 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4326
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4327 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4328 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4329 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4330 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4331 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4332 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4333
4334 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4335 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4336 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4337 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4338 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4339 "Diffusion contact spacing < %d (licon.2)"
4340 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4341
4342 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4343 "poly contact spacing to diffusion < %d (licon.14)"
4344 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4345 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4346
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4347 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4348 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4349 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4350 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4351 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4352 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4353 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4354 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4355 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4356 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4357 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4358 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4359
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4360 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4361 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4362 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4363 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4364 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4365 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4366 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4367 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4368 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4369
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4370 spacing psc/a allnactivenontap 60 touching_illegal \
4371 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4372 spacing nsc/a allpactivenontap 60 touching_illegal \
4373 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4374
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4375 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4376 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4377 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4378 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4379 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4380 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4381 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4382 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4383 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4384
4385 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4386 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4387 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4388 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4389
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4390 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4391 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4392 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4393 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4394 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4395 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4396 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4397 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4398
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4399 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4400 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4401 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4402 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4403
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4404 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4405 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4406 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4407 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4408 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4409 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4410 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4411 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4412
4413 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4414 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4415 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4416 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4417
4418 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4419 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4420 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4421 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4422
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4423 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4424
4425#-------------------------------------------------------------
4426# LI - Local interconnect layer
4427#-------------------------------------------------------------
4428
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4429variants *
4430
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4431 width *li 170 "Local interconnect width < %d (li.1)"
4432 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4433
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4434 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4435 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4436
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4437 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4438 # no special layers for the contacts in core cells, so they must be included
4439 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4440 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4441 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4442
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4443 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4444 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4445
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4446 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4447 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4448
4449 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4450 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4451 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4452
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4453 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4454
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4455 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4456 angles coreli 45 \
4457 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4458
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4459#-------------------------------------------------------------
4460# MCON - Contact between local interconnect and metal1
4461#-------------------------------------------------------------
4462
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4463 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4464 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4465
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4466 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4467
4468#-------------------------------------------------------------
4469# METAL1 -
4470#-------------------------------------------------------------
4471
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4472 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4473 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4474 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4475
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4476 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4477 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4478 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4479 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4480
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4481 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4482
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4483variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4484 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4485 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4486 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4487 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4488
4489variants (full)
4490 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4491 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4492
4493 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4494 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4495variants *
4496
4497#--------------------------------------------------
4498# VIA1
4499#--------------------------------------------------
4500
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4501 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4502 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4503 surround v1/m1 *m1,rm1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4504 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4505 surround v1/m2 *m2,rm2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4506 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4507
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4508 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4509
4510#--------------------------------------------------
4511# METAL2 -
4512#--------------------------------------------------
4513
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4514 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4515 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4516 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4517
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4518 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4519
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4520variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4521 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4522 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4523 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4524 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4525
4526variants (full)
4527 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4528 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4529
4530 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4531 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4532variants *
4533
4534#--------------------------------------------------
4535# VIA2
4536#--------------------------------------------------
4537
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4538 width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4539
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4540 spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4541
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4542 surround v2/m2 *m2,rm2 45 directional \
4543 "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
4544 surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4545
4546 exact_overlap v2/m2
4547
4548#--------------------------------------------------
4549# METAL3 -
4550#--------------------------------------------------
4551
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4552 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4553 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4554 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4555
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4556 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4557
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4558variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4559 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4560 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4561 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4562 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4563variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4564 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4565 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4566variants *
4567
4568
4569#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4570#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4571#--------------------------------------------------
4572# VIA3 - Requires METAL5 Module
4573#--------------------------------------------------
4574
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4575 width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
4576 spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
4577 surround v3/m3 *m3,rm3 30 directional \
4578 "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
4579 surround v3/m4 *m4,rm4 5 absence_illegal \
4580 "Metal4 overlap of via3 < %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4581
4582 exact_overlap v3/m3
4583
4584#-----------------------------
4585# METAL4 - METAL4 Module
4586#-----------------------------
4587
4588variants *
4589
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4590 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4591 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4592 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4593
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4594 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4595
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4596variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4597 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4598 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4599 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4600 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4601variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4602 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4603 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4604variants *
4605
4606#--------------------------------------------------
4607# VIA4 - Requires METAL5 Module
4608#--------------------------------------------------
4609
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4610 width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
4611 spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
4612 surround v4/m5 *m5,rm5 120 absence_illegal \
4613 "Metal5 overlap of via4 < %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4614
4615 exact_overlap v4/m4
4616
4617#-----------------------------
4618# METAL5 - METAL5 Module
4619#-----------------------------
4620
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4621 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4622 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4623 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4624
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4625 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4626
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4627#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4628#endif (METAL5)
4629
4630#ifdef REDISTRIBUTION
4631
4632variants (full)
4633
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4634 width metrdl 10000 "RDL width < %d (rdl.1)"
4635 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4636 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4637 spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4638
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4639variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4640
4641#endif (REDISTRIBUTION)
4642
4643#--------------------------------------------------
4644# NMOS, PMOS
4645#--------------------------------------------------
4646
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4647 edge4way *poly allfetsstd 420 allfets 0 0 \
4648 "Transistor width < %d (diff/tap.2)"
4649 edge4way *poly allfetsspecial 360 allfets 0 0 \
4650 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4651 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4652 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4653 edge4way *poly ppu 140 allfets 0 0 \
4654 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4655
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4656 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4657 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4658
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4659 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4660 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4661 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4662 "poly spacing to diffusion tap < %d (poly.5)"
4663 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4664 "poly spacing to diffusion tap < %d (poly.5)"
4665 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4666 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4667
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4668 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4669 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4670 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4671 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4672 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4673 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4674 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4675 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4676
4677 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4678 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4679 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4680
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4681 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4682 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4683
4684 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4685 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4686 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4687
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4688 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4689 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4690
4691 # Minimum length of MV FETs. Note that this is larger than the minimum
4692 # width (0.29um), so an edge rule is required
4693
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4694 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4695 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4696
4697 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4698 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4699
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4700 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4701 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4702
4703#--------------------------------------------------
4704# mrp1 (N+ poly resistor)
4705#--------------------------------------------------
4706
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4707 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4708
4709#--------------------------------------------------
4710# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4711# uhrpoly (P+ poly resistor, 2kOhm/sq)
4712#--------------------------------------------------
4713
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4714 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4715 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4716 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4717
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4718 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4719 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4720
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4721 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4722 "Poly resistor spacing to poly < %d (poly.9)"
4723
4724 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4725 "Poly resistor spacing to poly < %d (poly.9)"
4726
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4727 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4728 "Poly resistor spacing to poly < %d (poly.9)"
4729
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4730 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4731 "Poly resistor spacing to diffusion < %d (poly.9)"
4732
4733#------------------------------------
4734# nsonos
4735#------------------------------------
4736
4737variants (full)
4738 cifmaxwidth bbox_missing 0 bend_illegal \
4739 "SONOS transistor must be in cell with abutment box (tunm.8)"
4740variants (fast),(full)
4741
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4742#------------------------------------
4743# MOS Varactor device rules
4744#------------------------------------
4745
4746 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4747 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4748
4749 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4750 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4751
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4752 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4753 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4754
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4755variants (full)
4756 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4757 "N-well overlap of varactor poly < 0.15um (varac.5)"
4758
4759 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4760 "Varactor N-well must not contain P+ diffusion (varac.7)"
4761variants (fast),(full)
4762
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4763#ifdef MIM
4764#-----------------------------------------------------------
4765# MiM CAP (CAPM) -
4766#-----------------------------------------------------------
4767
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4768 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4769 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4770 spacing *mimcap via3/m3 80 touching_illegal \
4771 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4772 surround *mimcc *mimcap 80 absence_illegal \
4773 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4774 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4775
4776 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4777 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4778 spacing via2 *mimcap 100 touching_illegal \
4779 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4780 spacing *mimcap *metal3/m3 500 surround_ok \
4781 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4782
4783variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4784 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4785 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4786variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4787
4788 # MiM cap contact rules (VIA3)
4789
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4790 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4791 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4792 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4793 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4794 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4795
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4796 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4797 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4798 spacing *mimcap2 via4/m4 10 touching_illegal \
4799 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4800 surround *mim2cc *mimcap2 10 absence_illegal \
4801 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4802 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4803
4804 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4805 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4806 spacing via3 *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4807 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4808 spacing *mimcap2 *metal4/m4 500 surround_ok \
4809 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4810
4811variants (full)
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4812 cifmaxwidth mim2_contact_overlap 0 bend_illegal \
4813 "MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
4814
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4815 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4816 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4817variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4818
4819 # MiM cap contact rules (VIA4)
4820
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4821 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4822 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4823 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4825 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4826 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4827
4828#endif (MIM)
4829
4830#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4831# HVNTM
4832#----------------------------
4833variants (full)
4834 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4835 "HVNTM spacing < %d (hvntm.2)"
4836variants (fast),(full)
4837
4838#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4839# End DRC style
4840#----------------------------
4841
4842end
4843
4844#----------------------------
4845# LEF format definitions
4846#----------------------------
4847
4848lef
4849
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4850 masterslice pwell pwell PWELL substrate
4851 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4852
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4853 routing li li1 LI1 LI li
4854
4855 routing m1 met1 MET1 m1
4856 routing m2 met2 MET2 m2
4857 routing m3 met3 MET3 m3
4858#ifdef METAL5
4859 routing m4 met4 MET4 m4
4860 routing m5 met5 MET5 m5
4861#endif (METAL5)
4862#ifdef REDISTRIBUTION
4863 routing mrdl met6 MET6 m6 MRDL METRDL
4864#endif
4865
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4866 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4867 cut m2c via via1 VIA VIA1 cont2 via12
4868 cut m3c via2 VIA2 cont3 via23
4869#ifdef METAL5
4870 cut via3 via3 VIA3 cont4 via34
4871 cut via4 via4 VIA4 cont5 via45
4872#endif (METAL5)
4873
4874 obs obsli li1
4875 obs obsm1 met1
4876 obs obsm2 met2
4877 obs obsm3 met3
4878
4879#ifdef METAL5
4880 obs obsm4 met4
4881 obs obsm5 met5
4882#endif (METAL5)
4883#ifdef REDISTRIBUTION
4884 obs obsmrdl met6
4885#endif
4886
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4887 # NOTE: obsmcon only used with li1, not obsli.
4888 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4889
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4890 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4891 obs obsm1 via
4892 obs obsm2 via2
4893#ifdef METAL5
4894 obs obsm3 via3
4895 obs obsm4 via4
4896#endif (METAL5)
4897
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4898end
4899
4900#-----------------------------------------------------
4901# Device and Parasitic extraction
4902#-----------------------------------------------------
4903
4904
4905extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4906 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4907 cscale 1
4908 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4909 # dimensions must be in units of microns in the extract file.
4910 # Use extract style "ngspice(si)" to override this and produce
4911 # a file with SI units for length/area.
4912
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4913 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4914 lambda 1E6
4915 variants (si)
4916 lambda 1.0
4917 variants *
4918
4919 units microns
4920 step 7
4921 sidehalo 2
4922
4923 # NOTE: MiM cap layers have been purposely put out of order,
4924 # may want to reconsider.
4925
4926 planeorder dwell 0
4927 planeorder well 1
4928 planeorder active 2
4929 planeorder locali 3
4930 planeorder metal1 4
4931 planeorder metal2 5
4932 planeorder metal3 6
4933#ifdef METAL5
4934 planeorder metal4 7
4935 planeorder metal5 8
4936#ifdef REDISTRIBUTION
4937 planeorder metali 9
4938 planeorder block 10
4939 planeorder comment 11
4940 planeorder cap1 12
4941 planeorder cap2 13
4942#else (!REDISTRIBUTION)
4943 planeorder block 9
4944 planeorder comment 10
4945 planeorder cap1 11
4946 planeorder cap2 12
4947#endif (!REDISTRIBUTION)
4948#else (!METAL5)
4949#ifdef REDISTRIBUTION
4950 planeorder metali 7
4951 planeorder block 8
4952 planeorder comment 9
4953 planeorder cap1 10
4954 planeorder cap2 11
4955#else (!REDISTRIBUTION)
4956 planeorder block 7
4957 planeorder comment 8
4958 planeorder cap1 9
4959 planeorder cap2 10
4960#endif (!REDISTRIBUTION)
4961#endif (!METAL5)
4962
4963 height dnwell -0.1 0.1
4964 height nwell,pwell 0.0 0.2062
4965 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4966 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4967 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4968 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4969 height alldiffcont 0.3262 0.61
4970 height pc 0.5062 0.43
4971 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4972 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4973 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4974 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4975 height v1 1.7361 0.27
4976 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4977 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4978 height v2 2.3661 0.42
4979 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4980 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4981#ifdef METAL5
4982 height v3 3.6311 0.39
4983 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4984 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4985 height v4 4.8661 0.505
4986 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4987 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4988 height mimcap 2.4661 0.2
4989 height mimcap2 3.7311 0.2
4990 height mimcc 2.6661 0.12
4991 height mim2cc 3.9311 0.09
4992#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]4993 height mrdlc 6.6311 0.63
4994 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4995#endif (!REDISTRIBUTION)
4996#endif (!METAL5)
4997
4998 # Antenna check parameters
4999 # Note that checks w/diode diffusion are not modeled
5000 model partial
5001 antenna poly sidewall 50 none
5002 antenna allcont surface 3 none
5003 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5004 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5005 antenna m1,m2,m3 sidewall 400 2600 400
5006 antenna v1 surface 3 0 18
5007 antenna v2 surface 6 0 36
5008#ifdef METAL5
5009 antenna m4,m5 sidewall 400 2600 400
5010 antenna v3,v4 surface 6 0 36
5011#endif (METAL5)
5012
5013 tiedown alldiffnonfet
5014
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]5015 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5016
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5017# Resistances are in milliohms per square
5018# Optional 3rd argument is the corner adjustment fraction
5019# Device values come from trtc.cor (typical corner)
Tim Edwards14beb9c2021-09-15 16:19:23 -0400[diff] [blame]5020 resist (pwell,isosub)/well 4400000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5021 resist (dnwell)/dwell 2200000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5022 resist (nwell)/well 1700000
5023 resist (rpw)/well 3050000 0.5
5024 resist (*ndiff,nsd)/active 120000
5025 resist (*pdiff,*psd)/active 197000
5026 resist (*mvndiff,mvnsd)/active 114000
5027 resist (*mvpdiff,*mvpsd)/active 191000
5028
5029 resist ndiffres/active 120000 0.5
5030 resist pdiffres/active 197000 0.5
5031 resist mvndiffres/active 114000 0.5
5032 resist mvpdiffres/active 191000 0.5
5033 resist mrp1/active 48200 0.5
5034 resist xhrpoly/active 319800 0.5
5035 resist uhrpoly/active 2000000 0.5
5036
5037 resist (allpolynonres)/active 48200
5038 resist rmp/active 48200
5039
5040 resist (allli)/locali 12200
5041 resist (allm1)/metal1 125
5042 resist (allm2)/metal2 125
5043 resist (allm3)/metal3 47
5044#ifdef METAL5
5045 resist (allm4)/metal4 47
5046 resist (allm5)/metal5 29
5047#endif (METAL5)
5048#ifdef REDISTRIBUTION
5049 resist mrdl/metali 5
5050#endif (REDISTRIBUTION)
5051
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]5052 # These types should not be considered as electrical nodes
5053 resist blocktypes None
5054 resist obstypes None
5055 resist idtypes None
5056 resist comment None
5057
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5058 contact ndc,nsc 15000
5059 contact pdc,psc 15000
5060 contact mvndc,mvnsc 15000
5061 contact mvpdc,mvpsc 15000
5062 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5063 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5064 contact m2c 4500
5065 contact m3c 3410
5066#ifdef METAL5
5067#ifdef MIM
5068 contact mimcc 4500
5069 contact mim2cc 3410
5070#endif (MIM)
5071 contact via3 3410
5072 contact via4 380
5073#endif (METAL5)
5074#ifdef REDISTRIBUTION
5075 contact mrdlc 6
5076#endif (REDISTRIBUTION)
5077
5078#-------------------------------------------------------------------------
5079# Parasitic capacitance values: Use document (...)
5080#-------------------------------------------------------------------------
5081# This uses the new "default" definitions that determine the intervening
5082# planes from the planeorder stack, take care of the reflexive sideoverlap
5083# definitions, and generally clean up the section and make it more readable.
5084#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5085# Also uses "units microns" statement. All values are taken from the
5086# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5087# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5088#-------------------------------------------------------------------------
5089# Remember that device capacitances to substrate are taken care of by the
5090# models. Thus, active and poly definitions ignore all "fet" types.
5091# fet types are excluded when computing parasitic capacitance to
5092# active from layers above them because poly is a shield; fet types are
5093# included for parasitics from layers above to poly. Resistor types
5094# should be removed from all parasitic capacitance calculations, or else
5095# they just create floating caps. Technically, the capacitance probably
5096# should be split between the two terminals. Unsure of the correct model.
5097#-------------------------------------------------------------------------
5098
5099#n-well
5100# NOTE: This value not found in PEX files
5101defaultareacap nwell well 120
5102
5103#n-active
5104# Rely on device models to capture *ndiff area cap
5105# Do not extract parasitics from resistors
5106# defaultareacap allnactivenonfet active 790
5107# defaultperimeter allnactivenonfet active 280
5108
5109#p-active
5110# Rely on device models to capture *pdiff area cap
5111# Do not extract parasitics from resistors
5112# defaultareacap allpactivenonfet active 810
5113# defaultperimeter allpactivenonfet active 300
5114
5115#poly
5116# Do not extract parasitics from resistors
5117# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5118# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5119# defaultperimeter allpolynonfet active 57
5120
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5121 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5122 defaultareacap *poly active nwell,obswell,pwell well 106
5123 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5124
5125#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5126 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5127 defaultareacap allli locali nwell,obswell,pwell well 37
5128 defaultperimeter allli locali nwell,obswell,pwell well 55
5129 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5130
5131#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5132 defaultoverlap allli locali allactivenonfet active 37
5133 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5134
5135#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5136 defaultoverlap allli locali allpolynonres active 94
5137 defaultsideoverlap allli locali allpolynonres active 52
5138 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5139
5140#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5141 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5142 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5143 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5144 defaultoverlap allm1 metal1 nwell well 26
5145
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5146#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5147 defaultoverlap allm1 metal1 allactivenonfet active 26
5148 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5149
5150#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5151 defaultoverlap allm1 metal1 allpolynonres active 45
5152 defaultsideoverlap allm1 metal1 allpolynonres active 47
5153 defaultsideoverlap *poly active allm1 metal1 17
5154
5155#metal1->locali
5156 defaultoverlap allm1 metal1 allli locali 114
5157 defaultsideoverlap allm1 metal1 allli locali 59
5158 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5159
5160#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5161 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5162 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5163 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5164 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5165
5166#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5167 defaultoverlap allm2 metal2 allactivenonfet active 17
5168 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5169
5170#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5171 defaultoverlap allm2 metal2 allpolynonres active 24
5172 defaultsideoverlap allm2 metal2 allpolynonres active 41
5173 defaultsideoverlap *poly active allm2 metal2 11
5174
5175#metal2->locali
5176 defaultoverlap allm2 metal2 allli locali 38
5177 defaultsideoverlap allm2 metal2 allli locali 46
5178 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5179
5180#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5181 defaultoverlap allm2 metal2 allm1 metal1 134
5182 defaultsideoverlap allm2 metal2 allm1 metal1 67
5183 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5184
5185#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5186 defaultsidewall allm3 metal3 63
5187 defaultoverlap allm3 metal3 nwell well 12
5188 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5189 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5190
5191#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5192 defaultoverlap allm3 metal3 allactive active 12
5193 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5194
5195#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5196 defaultoverlap allm3 metal3 allpolynonres active 16
5197 defaultsideoverlap allm3 metal3 allpolynonres active 44
5198 defaultsideoverlap *poly active allm3 metal3 9
5199
5200#metal3->locali
5201 defaultoverlap allm3 metal3 allli locali 21
5202 defaultsideoverlap allm3 metal3 allli locali 47
5203 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5204
5205#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5206 defaultoverlap allm3 metal3 allm1 metal1 35
5207 defaultsideoverlap allm3 metal3 allm1 metal1 55
5208 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5209
5210#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5211 defaultoverlap allm3 metal3 allm2 metal2 86
5212 defaultsideoverlap allm3 metal3 allm2 metal2 70
5213 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5214
5215#ifdef METAL5
5216#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5217 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5218# defaultareacap alltopm metal4 well 6
5219 areacap allm4/m4 8
5220 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5221 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5222
5223#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5224 defaultoverlap allm4 metal4 allactivenonfet active 8
5225 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5226
5227#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5228 defaultoverlap allm4 metal4 allpolynonres active 10
5229 defaultsideoverlap allm4 metal4 allpolynonres active 38
5230 defaultsideoverlap *poly active allm4 metal4 6
5231
5232#metal4->locali
5233 defaultoverlap allm4 metal4 allli locali 12
5234 defaultsideoverlap allm4 metal4 allli locali 40
5235 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5236
5237#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5238 defaultoverlap allm4 metal4 allm1 metal1 15
5239 defaultsideoverlap allm4 metal4 allm1 metal1 43
5240 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5241
5242#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5243 defaultoverlap allm4 metal4 allm2 metal2 20
5244 defaultsideoverlap allm4 metal4 allm2 metal2 46
5245 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5246
5247#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5248 defaultoverlap allm4 metal4 allm3 metal3 84
5249 defaultsideoverlap allm4 metal4 allm3 metal3 71
5250 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5251
5252#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5253 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5254# defaultareacap allm5 metal5 well 6
5255 areacap allm5/m5 6
5256 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5257 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5258
5259#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5260 defaultoverlap allm5 metal5 allactivenonfet active 6
5261 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5262
5263#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5264 defaultoverlap allm5 metal5 allpolynonres active 7
5265 defaultsideoverlap allm5 metal5 allpolynonres active 40
5266 defaultsideoverlap *poly active allm5 metal5 6
5267
5268#metal5->locali
5269 defaultoverlap allm5 metal5 allli locali 8
5270 defaultsideoverlap allm5 metal5 allli locali 41
5271 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5272
5273#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5274 defaultoverlap allm5 metal5 allm1 metal1 9
5275 defaultsideoverlap allm5 metal5 allm1 metal1 43
5276 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5277
5278#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5279 defaultoverlap allm5 metal5 allm2 metal2 11
5280 defaultsideoverlap allm5 metal5 allm2 metal2 46
5281 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5282
5283#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5284 defaultoverlap allm5 metal5 allm3 metal3 20
5285 defaultsideoverlap allm5 metal5 allm3 metal3 54
5286 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5287
5288#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5289 defaultoverlap allm5 metal5 allm4 metal4 68
5290 defaultsideoverlap allm5 metal5 allm4 metal4 83
5291 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5292#endif (METAL5)
5293
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5294#ifdef REDISTRIBUTION
5295#endif (REDISTRIBUTION)
5296
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5297# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5298
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5299variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5300
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5301 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5302 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5303 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5304 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5305 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5306 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5307 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5308 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5309 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5310 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5311 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5312 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5313 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5314 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5315 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5316
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5317 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5318 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5319 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5320 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5321 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5322 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5323 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5324 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5325 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5326 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5327 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5328 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5329 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5330 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5331 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5332 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5333 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5334 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5335 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5336 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5337 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5338 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5339 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5340 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5341
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5342 # Bipolars
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5343 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
5344 error +npn1p00
5345 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
5346 error +npn2p00
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]5347 device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5348 device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
5349 pwell,space/w +pnp0p68
5350 device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
5351 pwell,space/w +pnp3p40
Tim Edwardsb9668302021-05-27 14:10:11 -0400[diff] [blame]5352 device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5353 device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
5354 dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5355 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5356
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5357 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5358 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5359 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5360 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5361
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5362 # Extended drain devices (must appear before the regular devices)
5363 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5364 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5365 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5366 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5367 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5368 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5369
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5370 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5371 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5372 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5373 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5374 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5375 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5376 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5377 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5378 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5379 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5380 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5381 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5382 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5383 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5384 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5385 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5386 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5387 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5388
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5389 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5390 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5391 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5392 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5393#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5394 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5395 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5396#endif (METAL5)
5397
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5398 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5399 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5400 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5401 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5402 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5403 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5404 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5405 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5406 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5407 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5408 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5409 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5410 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5411 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5412 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5413 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5414 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5415 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5416 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5417 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5418 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5419 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5420 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5421 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5422
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5423 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5424 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5425 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5426 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5427 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5428 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5429 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5430 *mvndiff pwell,space/w error l=l w=w
5431 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5432 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5433
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5434 device resistor sky130_fd_pr__res_generic_po rmp *poly
5435 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5436
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5437 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
5438 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
5439 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
5440 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5441
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5442 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
5443 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
5444 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
5445 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5446
5447#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5448 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5449 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5450#endif (MIM)
5451
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5452 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5453
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5454 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5455 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5456 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5457 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5458 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5459 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5460 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5461 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5462 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5463 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5464 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5465 pwell,space/w
5466
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5467 # Note that corenvar, corepvar are not considered devices, and extract as
5468 # parasitic capacitance instead (but cap values need to be added).
5469
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5470 # Extended drain devices (must appear before the regular devices)
5471 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5472 dnwell pwell,space/w error
5473 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5474 dnwell pwell,space/w error
5475 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5476 pwell,space/w nwell error
5477
5478 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5479 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5480 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5481 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5482 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5483 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5484
5485 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5486 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5487 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5488 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5489
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5490 device resistor sky130_fd_pr__res_generic_po rmp *poly
5491 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5492 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5493 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5494 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5495#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5496 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5497 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5498#endif (METAL5)
5499
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5500 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5501 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5502 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5503 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5504 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5505 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5506 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5507 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5508 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5509 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5510 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5511 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5512 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5513 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5514 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5515 device resistor mrdn_hv mvndiffres *mvndiff
5516 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5517 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5518
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5519 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5520 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5521 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5522 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5523
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5524 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5525 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5526 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5527 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5528
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5529 device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
5530 device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5531 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5532 device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
5533 device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5534 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5535 device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5536 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5537
5538#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5539 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5540 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5541#endif (MIM)
5542
5543end
5544
5545#-----------------------------------------------------
5546# Wiring tool definitions
5547#-----------------------------------------------------
5548
5549wiring
5550 # All wiring values are in nanometers
5551 scalefactor 10
5552
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5553 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5554 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5555 contact v2 280 m2 0 45 m3 25 0
5556#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5557 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5558 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5559#endif (METAL5)
5560
5561 contact pc 170 poly 50 80 li 0 80
5562 contact pdc 170 pdiff 40 60 li 0 80
5563 contact ndc 170 ndiff 40 60 li 0 80
5564 contact psc 170 psd 40 60 li 0 80
5565 contact nsc 170 nsd 40 60 li 0 80
5566
5567end
5568
5569#-----------------------------------------------------
5570# Plain old router. . .
5571#-----------------------------------------------------
5572
5573router
5574end
5575
5576#------------------------------------------------------------
5577# Plowing (restored in magic 8.2, need to fill this section)
5578#------------------------------------------------------------
5579
5580plowing
5581end
5582
5583#-----------------------------------------------------------------
5584# No special plot layers defined (use default PNM color choices)
5585#-----------------------------------------------------------------
5586
5587plot
5588 style pnm
5589 default
5590 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5591 draw fillblock4 no_color_at_all
5592 draw fomfill no_color_at_all
5593 draw polyfill no_color_at_all
5594 draw m1fill no_color_at_all
5595 draw m2fill no_color_at_all
5596 draw m3fill no_color_at_all
5597 draw m4fill no_color_at_all
5598 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5599 draw nwell cwell
5600end
5601