Added SPDX and removed cover traces (beacause of pre-check; this seems not good)
diff --git a/openlane/user_proj_example/.config.tcl.swp b/openlane/user_proj_example/.config.tcl.swp deleted file mode 100644 index 0a23798..0000000 --- a/openlane/user_proj_example/.config.tcl.swp +++ /dev/null Binary files differ
diff --git a/verilog/rtl/original/hyperram.v b/verilog/rtl/original/hyperram.v index ac4e915..7585941 100644 --- a/verilog/rtl/original/hyperram.v +++ b/verilog/rtl/original/hyperram.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 Steve Goldsmith, Aurifex Labs LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + module hyperram( input clk, input rst,
diff --git a/verilog/rtl/original/switch.v b/verilog/rtl/original/switch.v index af5ac00..28eb963 100644 --- a/verilog/rtl/original/switch.v +++ b/verilog/rtl/original/switch.v
@@ -1,3 +1,21 @@ + GNU nano 4.8 hyperram.v +// SPDX-FileCopyrightText: 2022 Steve Goldsmith, Aurifex Labs LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + + + module switch( // CPU Interface A input [31:0] address_a,
diff --git a/verilog/rtl/unit_test/bmc.sby b/verilog/rtl/unit_test/bmc.sby index 76bc9d2..760ffd8 100644 --- a/verilog/rtl/unit_test/bmc.sby +++ b/verilog/rtl/unit_test/bmc.sby
@@ -1,3 +1,21 @@ + GNU nano 4.8 hyperram.v +// SPDX-FileCopyrightText: 2022 Steve Goldsmith, Aurifex Labs LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + + + [options] mode bmc depth 100
diff --git a/verilog/rtl/unit_test/cover.sby b/verilog/rtl/unit_test/cover.sby index 13476bf..5e82845 100644 --- a/verilog/rtl/unit_test/cover.sby +++ b/verilog/rtl/unit_test/cover.sby
@@ -1,3 +1,21 @@ + GNU nano 4.8 hyperram.v +// SPDX-FileCopyrightText: 2022 Steve Goldsmith, Aurifex Labs LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + + + [options] mode cover depth 150
diff --git a/verilog/rtl/unit_test/cover/PASS b/verilog/rtl/unit_test/cover/PASS deleted file mode 100644 index f0793a6..0000000 --- a/verilog/rtl/unit_test/cover/PASS +++ /dev/null
@@ -1,9 +0,0 @@ -Elapsed clock time [H:MM:SS (secs)]: 0:00:05 (5) -Elapsed process time [H:MM:SS (secs)]: 0:00:05 (5) -engine_0 (smtbmc) returned pass -trace: cover/engine_0/trace0.vcd -trace: cover/engine_0/trace1.vcd -trace: cover/engine_0/trace2.vcd -trace: cover/engine_0/trace3.vcd -trace: cover/engine_0/trace4.vcd -and 4 further traces
diff --git a/verilog/rtl/unit_test/cover/config.sby b/verilog/rtl/unit_test/cover/config.sby deleted file mode 100644 index 13476bf..0000000 --- a/verilog/rtl/unit_test/cover/config.sby +++ /dev/null
@@ -1,13 +0,0 @@ -[options] -mode cover -depth 150 - -[engines] -smtbmc - -[script] -read -formal hyperram.v -prep -top hyperram - -[files] -../original/hyperram.v
diff --git a/verilog/rtl/unit_test/cover/cover.xml b/verilog/rtl/unit_test/cover/cover.xml deleted file mode 100644 index 626af86..0000000 --- a/verilog/rtl/unit_test/cover/cover.xml +++ /dev/null
@@ -1,157 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<testsuites> -<testsuite timestamp="2022-03-21T14:11:57" hostname="aurifex-tools" package="cover" id="0" name="default" tests="9" errors="0" failures="0" time="5" skipped="9"> -<properties> -<property name="os" value="Linux"/> -<property name="expect" value="PASS"/> -<property name="status" value="PASS"/> -</properties> -<testcase classname="default" name="build execution" time="0"> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:297.4-297.40" time="0" type="COVER" location="hyperram.v:297.4-297.40" id="cover_ca"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:301.4-301.45" time="0" type="COVER" location="hyperram.v:301.4-301.45" id="cover_done"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:296.4-296.42" time="0" type="COVER" location="hyperram.v:296.4-296.42" id="cover_idle"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:300.4-300.44" time="0" type="COVER" location="hyperram.v:300.4-300.44" id="cover_read"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:303.4-303.43" time="0" type="COVER" location="hyperram.v:303.4-303.43" id="cover_read_2"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:298.4-298.42" time="0" type="COVER" location="hyperram.v:298.4-298.42" id="cover_wait"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:299.4-299.43" time="0" type="COVER" location="hyperram.v:299.4-299.43" id="cover_write"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:302.4-302.45" time="0" type="COVER" location="hyperram.v:302.4-302.45" id="cover_write_2"> -<skipped /> -</testcase> -<testcase classname="default" name="Property COVER in hyperram at hyperram.v:304.4-304.65" time="0" type="COVER" location="hyperram.v:304.4-304.65" id="cover_write_read"> -<skipped /> -</testcase> -<system-out>SBY 14:11:51 [cover] Copy '/root/mar20/tool/caravel_tutorial/caravel_example/verilog/rtl/original/hyperram.v' to '/root/mar20/tool/caravel_tutorial/caravel_example/verilog/rtl/unit_test/cover/src/hyperram.v'. -SBY 14:11:51 [cover] engine_0: smtbmc -SBY 14:11:51 [cover] base: starting process "cd cover/src; yosys -ql ../model/design.log ../model/design.ys" -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:51) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:52) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:96) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:97) -SBY 14:11:51 [cover] base: Warning: wire '\transaction_end' is assigned in a block at hyperram.v:98.3-98.22. -SBY 14:11:51 [cover] base: Warning: wire '\transaction_end' is assigned in a block at hyperram.v:106.5-106.24. -SBY 14:11:51 [cover] base: Warning: wire '\rst' is assigned in a block at hyperram.v:281.4-281.11. -SBY 14:11:51 [cover] base: Warning: wire '\address' is assigned in a block at hyperram.v:282.4-282.24. -SBY 14:11:51 [cover] base: Warning: wire '\data_in' is assigned in a block at hyperram.v:287.4-287.24. -SBY 14:11:51 [cover] base: Warning: wire '\data_out' is assigned in a block at hyperram.v:288.4-288.25. -SBY 14:11:51 [cover] base: Warning: wire '\rst' is assigned in a block at hyperram.v:292.4-292.11. -SBY 14:11:51 [cover] base: finished (returncode=0) -SBY 14:11:51 [cover] smt2: starting process "cd cover/model; yosys -ql design_smt2.log design_smt2.ys" -SBY 14:11:51 [cover] smt2: finished (returncode=0) -SBY 14:11:51 [cover] engine_0: starting process "cd cover; yosys-smtbmc --presat --unroll -c --noprogress -t 150 --append 0 --dump-vcd engine_0/trace%.vcd --dump-vlogtb engine_0/trace%_tb.v --dump-smtc engine_0/trace%.smtc model/design_smt2.smt2" -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Solver: yices -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 0.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 1.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_idle in step 1. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace0.vcd -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace0_tb.v -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace0.smtc -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 1.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 2.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 3.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 4.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 5.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 6.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 7.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_ca in step 7. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace1.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace1_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace1.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 7.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 8.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_wait in step 8. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace2.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace2_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace2.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 8.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 9.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 10.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 11.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 12.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_write in step 13. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace3.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace3_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace3.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_read in step 13. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace4.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace4_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace4.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 14.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 15.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 16.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 17.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_done in step 17. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace5.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace5_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace5.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 17.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 18.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 19.. -SBY 14:11:52 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 20.. -SBY 14:11:52 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 21.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 22.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 23.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 24.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 25.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 26.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 27.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 28.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 29.. -SBY 14:11:53 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 30.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 31.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 32.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 33.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 34.. -SBY 14:11:54 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 35.. -SBY 14:11:55 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 36.. -SBY 14:11:55 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 37.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Checking cover reachability in step 38.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Reached cover statement at cover_write_read in step 38. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to VCD file: engine_0/trace6.vcd -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to Verilog testbench: engine_0/trace6_tb.v -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to constraints file: engine_0/trace6.smtc -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Checking cover reachability in step 38.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Reached cover statement at cover_write_2 in step 38. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to VCD file: engine_0/trace7.vcd -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace7_tb.v -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to constraints file: engine_0/trace7.smtc -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Checking cover reachability in step 38.. -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Reached cover statement at cover_read_2 in step 38. -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to VCD file: engine_0/trace8.vcd -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace8_tb.v -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to constraints file: engine_0/trace8.smtc -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Status: passed -SBY 14:11:57 [cover] engine_0: finished (returncode=0) -SBY 14:11:57 [cover] engine_0: Status returned by engine: pass -SBY 14:11:57 [cover] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:05 (5) -SBY 14:11:57 [cover] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:05 (5) -SBY 14:11:57 [cover] summary: engine_0 (smtbmc) returned pass -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace0.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace1.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace2.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace3.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace4.vcd -SBY 14:11:57 [cover] summary: and 4 further traces -SBY 14:11:57 [cover] DONE (PASS, rc=0) -</system-out> -<system-err> -</system-err> -</testsuite> -</testsuites>
diff --git a/verilog/rtl/unit_test/cover/engine_0/logfile.txt b/verilog/rtl/unit_test/cover/engine_0/logfile.txt deleted file mode 100644 index 226ef5e..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/logfile.txt +++ /dev/null
@@ -1,85 +0,0 @@ -## 0:00:00 Solver: yices -## 0:00:00 Checking cover reachability in step 0.. -## 0:00:00 Checking cover reachability in step 1.. -## 0:00:00 Reached cover statement at cover_idle in step 1. -## 0:00:00 Writing trace to VCD file: engine_0/trace0.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace0_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace0.smtc -## 0:00:00 Checking cover reachability in step 1.. -## 0:00:00 Checking cover reachability in step 2.. -## 0:00:00 Checking cover reachability in step 3.. -## 0:00:00 Checking cover reachability in step 4.. -## 0:00:00 Checking cover reachability in step 5.. -## 0:00:00 Checking cover reachability in step 6.. -## 0:00:00 Checking cover reachability in step 7.. -## 0:00:00 Reached cover statement at cover_ca in step 7. -## 0:00:00 Writing trace to VCD file: engine_0/trace1.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace1_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace1.smtc -## 0:00:00 Checking cover reachability in step 7.. -## 0:00:00 Checking cover reachability in step 8.. -## 0:00:00 Reached cover statement at cover_wait in step 8. -## 0:00:00 Writing trace to VCD file: engine_0/trace2.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace2_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace2.smtc -## 0:00:00 Checking cover reachability in step 8.. -## 0:00:00 Checking cover reachability in step 9.. -## 0:00:00 Checking cover reachability in step 10.. -## 0:00:00 Checking cover reachability in step 11.. -## 0:00:00 Checking cover reachability in step 12.. -## 0:00:00 Checking cover reachability in step 13.. -## 0:00:00 Reached cover statement at cover_write in step 13. -## 0:00:00 Writing trace to VCD file: engine_0/trace3.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace3_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace3.smtc -## 0:00:00 Checking cover reachability in step 13.. -## 0:00:00 Reached cover statement at cover_read in step 13. -## 0:00:00 Writing trace to VCD file: engine_0/trace4.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace4_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace4.smtc -## 0:00:00 Checking cover reachability in step 13.. -## 0:00:00 Checking cover reachability in step 14.. -## 0:00:00 Checking cover reachability in step 15.. -## 0:00:00 Checking cover reachability in step 16.. -## 0:00:00 Checking cover reachability in step 17.. -## 0:00:00 Reached cover statement at cover_done in step 17. -## 0:00:00 Writing trace to VCD file: engine_0/trace5.vcd -## 0:00:00 Writing trace to Verilog testbench: engine_0/trace5_tb.v -## 0:00:00 Writing trace to constraints file: engine_0/trace5.smtc -## 0:00:00 Checking cover reachability in step 17.. -## 0:00:00 Checking cover reachability in step 18.. -## 0:00:00 Checking cover reachability in step 19.. -## 0:00:01 Checking cover reachability in step 20.. -## 0:00:01 Checking cover reachability in step 21.. -## 0:00:01 Checking cover reachability in step 22.. -## 0:00:01 Checking cover reachability in step 23.. -## 0:00:01 Checking cover reachability in step 24.. -## 0:00:01 Checking cover reachability in step 25.. -## 0:00:01 Checking cover reachability in step 26.. -## 0:00:01 Checking cover reachability in step 27.. -## 0:00:01 Checking cover reachability in step 28.. -## 0:00:01 Checking cover reachability in step 29.. -## 0:00:02 Checking cover reachability in step 30.. -## 0:00:02 Checking cover reachability in step 31.. -## 0:00:02 Checking cover reachability in step 32.. -## 0:00:02 Checking cover reachability in step 33.. -## 0:00:02 Checking cover reachability in step 34.. -## 0:00:03 Checking cover reachability in step 35.. -## 0:00:03 Checking cover reachability in step 36.. -## 0:00:03 Checking cover reachability in step 37.. -## 0:00:04 Checking cover reachability in step 38.. -## 0:00:04 Reached cover statement at cover_write_read in step 38. -## 0:00:04 Writing trace to VCD file: engine_0/trace6.vcd -## 0:00:04 Writing trace to Verilog testbench: engine_0/trace6_tb.v -## 0:00:04 Writing trace to constraints file: engine_0/trace6.smtc -## 0:00:04 Checking cover reachability in step 38.. -## 0:00:04 Reached cover statement at cover_write_2 in step 38. -## 0:00:04 Writing trace to VCD file: engine_0/trace7.vcd -## 0:00:05 Writing trace to Verilog testbench: engine_0/trace7_tb.v -## 0:00:05 Writing trace to constraints file: engine_0/trace7.smtc -## 0:00:05 Checking cover reachability in step 38.. -## 0:00:05 Reached cover statement at cover_read_2 in step 38. -## 0:00:05 Writing trace to VCD file: engine_0/trace8.vcd -## 0:00:05 Writing trace to Verilog testbench: engine_0/trace8_tb.v -## 0:00:05 Writing trace to constraints file: engine_0/trace8.smtc -## 0:00:05 Status: passed
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace0.smtc b/verilog/rtl/unit_test/cover/engine_0/trace0.smtc deleted file mode 100644 index f3b364e..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace0.smtc +++ /dev/null
@@ -1,48 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace0_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace0_tb.v deleted file mode 100644 index 90d5790..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace0_tb.v +++ /dev/null
@@ -1,106 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b0; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 1; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace1.smtc b/verilog/rtl/unit_test/cover/engine_0/trace1.smtc deleted file mode 100644 index 60c17c4..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace1.smtc +++ /dev/null
@@ -1,132 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace1_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace1_tb.v deleted file mode 100644 index d00c057..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace1_tb.v +++ /dev/null
@@ -1,196 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 7; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace2.smtc b/verilog/rtl/unit_test/cover/engine_0/trace2.smtc deleted file mode 100644 index 910a05f..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace2.smtc +++ /dev/null
@@ -1,146 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace2_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace2_tb.v deleted file mode 100644 index 4fe1c27..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace2_tb.v +++ /dev/null
@@ -1,211 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 8; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace3.smtc b/verilog/rtl/unit_test/cover/engine_0/trace3.smtc deleted file mode 100644 index abfc206..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace3.smtc +++ /dev/null
@@ -1,216 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace3_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace3_tb.v deleted file mode 100644 index 2ab2105..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace3_tb.v +++ /dev/null
@@ -1,286 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 13; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace4.smtc b/verilog/rtl/unit_test/cover/engine_0/trace4.smtc deleted file mode 100644 index 76921af..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace4.smtc +++ /dev/null
@@ -1,216 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace4_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace4_tb.v deleted file mode 100644 index 513da91..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace4_tb.v +++ /dev/null
@@ -1,286 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 13; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace5.smtc b/verilog/rtl/unit_test/cover/engine_0/trace5.smtc deleted file mode 100644 index 79600d9..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace5.smtc +++ /dev/null
@@ -1,272 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 14 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 15 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 16 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 17 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace5_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace5_tb.v deleted file mode 100644 index ce5ba82..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace5_tb.v +++ /dev/null
@@ -1,346 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 14 - if (cycle == 13) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 15 - if (cycle == 14) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 16 - if (cycle == 15) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 17 - if (cycle == 16) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 17; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace6.smtc b/verilog/rtl/unit_test/cover/engine_0/trace6.smtc deleted file mode 100644 index 2fb5b5f..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace6.smtc +++ /dev/null
@@ -1,566 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 14 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 15 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 16 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 17 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 18 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 19 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 20 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 21 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 22 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 23 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 24 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 25 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 26 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 27 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 28 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 29 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 30 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 31 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 32 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0001) - -state 33 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] true) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 34 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 35 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 36 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 37 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 38 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace6_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace6_tb.v deleted file mode 100644 index 0172369..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace6_tb.v +++ /dev/null
@@ -1,661 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 14 - if (cycle == 13) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 15 - if (cycle == 14) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 16 - if (cycle == 15) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 17 - if (cycle == 16) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 18 - if (cycle == 17) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 19 - if (cycle == 18) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 20 - if (cycle == 19) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 21 - if (cycle == 20) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 22 - if (cycle == 21) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 23 - if (cycle == 22) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 24 - if (cycle == 23) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 25 - if (cycle == 24) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 26 - if (cycle == 25) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 27 - if (cycle == 26) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 28 - if (cycle == 27) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 29 - if (cycle == 28) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 30 - if (cycle == 29) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 31 - if (cycle == 30) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 32 - if (cycle == 31) begin - PI_write_mask <= 4'b0001; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 33 - if (cycle == 32) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b1; - PI_rst <= 1'b0; - end - - // state 34 - if (cycle == 33) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 35 - if (cycle == 34) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 36 - if (cycle == 35) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 37 - if (cycle == 36) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 38 - if (cycle == 37) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 38; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace7.smtc b/verilog/rtl/unit_test/cover/engine_0/trace7.smtc deleted file mode 100644 index dbd2770..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace7.smtc +++ /dev/null
@@ -1,566 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] true) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 14 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 15 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 16 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 17 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] true) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 18 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 19 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 20 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 21 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 22 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 23 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 24 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 25 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 26 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 27 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 28 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 29 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 30 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 31 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 32 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 33 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 34 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11011101) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 35 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 36 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001100) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 37 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 38 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace7_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace7_tb.v deleted file mode 100644 index ac48d03..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace7_tb.v +++ /dev/null
@@ -1,661 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b1; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 14 - if (cycle == 13) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 15 - if (cycle == 14) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 16 - if (cycle == 15) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 17 - if (cycle == 16) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b1; - PI_rst <= 1'b0; - end - - // state 18 - if (cycle == 17) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 19 - if (cycle == 18) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 20 - if (cycle == 19) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 21 - if (cycle == 20) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 22 - if (cycle == 21) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 23 - if (cycle == 22) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 24 - if (cycle == 23) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 25 - if (cycle == 24) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 26 - if (cycle == 25) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 27 - if (cycle == 26) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 28 - if (cycle == 27) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 29 - if (cycle == 28) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 30 - if (cycle == 29) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 31 - if (cycle == 30) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 32 - if (cycle == 31) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 33 - if (cycle == 32) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 34 - if (cycle == 33) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11011101; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 35 - if (cycle == 34) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 36 - if (cycle == 35) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001100; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 37 - if (cycle == 36) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 38 - if (cycle == 37) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 38; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace8.smtc b/verilog/rtl/unit_test/cover/engine_0/trace8.smtc deleted file mode 100644 index b55744d..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace8.smtc +++ /dev/null
@@ -1,566 +0,0 @@ -initial -assume (= [$formal$hyperram.v:296$1_CHECK] false) -assume (= [$formal$hyperram.v:296$1_EN] false) -assume (= [$formal$hyperram.v:297$2_CHECK] false) -assume (= [$formal$hyperram.v:298$3_CHECK] false) -assume (= [$formal$hyperram.v:299$4_CHECK] false) -assume (= [$formal$hyperram.v:300$5_CHECK] false) -assume (= [$formal$hyperram.v:301$6_CHECK] false) -assume (= [$formal$hyperram.v:302$7_CHECK] false) -assume (= [$formal$hyperram.v:303$8_CHECK] false) -assume (= [$formal$hyperram.v:304$9_CHECK] false) -assume (= [ck] false) -assume (= [command_address] #b000000000000000000000000000000000000000000000000) -assume (= [control_state] #b0000000) -assume (= [data_out_register] #b00000000000000000000000000000000) -assume (= [done_counter] #b00000000) -assume (= [read_count] #b000000) -assume (= [wait_counter] #b00000000) -assume (= [write_count] #b000000) -assume (= [write_mask_register] #b0000) - -state 0 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 1 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 2 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 3 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 4 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 5 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 6 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 7 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 8 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 9 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 10 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 11 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 12 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 13 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 14 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 15 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 16 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 17 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 18 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 19 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 20 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 21 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 22 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00100000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 23 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000110) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 24 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b10001010) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 25 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b11001111) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 26 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 27 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 28 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 29 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 30 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] true) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 31 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 32 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] true) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 33 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] true) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 34 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] true) -assume (= [write_mask] #b0000) - -state 35 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 36 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 37 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000) - -state 38 -assume (= [address] #b00010010001101000101011001111000) -assume (= [clk] false) -assume (= [data_out] #b11001100110011001101110111011101) -assume (= [done_latency] #b000000) -assume (= [dq] #b00000000) -assume (= [rst] false) -assume (= [rwds] false) -assume (= [timed_read] false) -assume (= [transaction_begin] false) -assume (= [wait_latency] #b000000) -assume (= [write_enable] false) -assume (= [write_mask] #b0000)
diff --git a/verilog/rtl/unit_test/cover/engine_0/trace8_tb.v b/verilog/rtl/unit_test/cover/engine_0/trace8_tb.v deleted file mode 100644 index 4bf93b2..0000000 --- a/verilog/rtl/unit_test/cover/engine_0/trace8_tb.v +++ /dev/null
@@ -1,661 +0,0 @@ -`ifndef VERILATOR -module testbench; - reg [4095:0] vcdfile; - reg clock; -`else -module testbench(input clock, output reg genclock); - initial genclock = 1; -`endif - reg genclock = 1; - reg [31:0] cycle = 0; - reg [3:0] PI_write_mask; - reg [0:0] PI_transaction_begin; - reg [5:0] PI_wait_latency; - reg [0:0] PI_write_enable; - reg [31:0] PI_address; - reg [5:0] PI_done_latency; - reg [7:0] PI_dq; - reg [31:0] PI_data_out; - reg [0:0] PI_timed_read; - wire [0:0] PI_clk = clock; - reg [0:0] PI_rwds; - reg [0:0] PI_rst; - hyperram UUT ( - .write_mask(PI_write_mask), - .transaction_begin(PI_transaction_begin), - .wait_latency(PI_wait_latency), - .write_enable(PI_write_enable), - .address(PI_address), - .done_latency(PI_done_latency), - .dq(PI_dq), - .data_out(PI_data_out), - .timed_read(PI_timed_read), - .clk(PI_clk), - .rwds(PI_rwds), - .rst(PI_rst) - ); -`ifndef VERILATOR - initial begin - if ($value$plusargs("vcd=%s", vcdfile)) begin - $dumpfile(vcdfile); - $dumpvars(0, testbench); - end - #5 clock = 0; - while (genclock) begin - #5 clock = 0; - #5 clock = 1; - end - end -`endif - initial begin -`ifndef VERILATOR - #1; -`endif - // UUT.$formal$hyperram.\v:296$1_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:296$1_EN = 1'b0; - // UUT.$formal$hyperram.\v:297$2_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:298$3_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:299$4_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:300$5_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:301$6_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:302$7_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:303$8_CHECK = 1'b0; - // UUT.$formal$hyperram.\v:304$9_CHECK = 1'b0; - UUT.ck = 1'b0; - UUT.command_address = 48'b000000000000000000000000000000000000000000000000; - UUT.control_state = 7'b0000000; - UUT.data_out_register = 32'b00000000000000000000000000000000; - UUT.done_counter = 8'b00000000; - UUT.read_count = 6'b000000; - UUT.wait_counter = 8'b00000000; - UUT.write_count = 6'b000000; - UUT.write_mask_register = 4'b0000; - - // state 0 - PI_write_mask = 4'b0000; - PI_transaction_begin = 1'b1; - PI_wait_latency = 6'b000000; - PI_write_enable = 1'b0; - PI_address = 32'b00010010001101000101011001111000; - PI_done_latency = 6'b000000; - PI_dq = 8'b00000000; - PI_data_out = 32'b11001100110011001101110111011101; - PI_timed_read = 1'b0; - PI_rwds = 1'b0; - PI_rst = 1'b0; - end - always @(posedge clock) begin - // state 1 - if (cycle == 0) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 2 - if (cycle == 1) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 3 - if (cycle == 2) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 4 - if (cycle == 3) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 5 - if (cycle == 4) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 6 - if (cycle == 5) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 7 - if (cycle == 6) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 8 - if (cycle == 7) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 9 - if (cycle == 8) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 10 - if (cycle == 9) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 11 - if (cycle == 10) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 12 - if (cycle == 11) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 13 - if (cycle == 12) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 14 - if (cycle == 13) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 15 - if (cycle == 14) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 16 - if (cycle == 15) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 17 - if (cycle == 16) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 18 - if (cycle == 17) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 19 - if (cycle == 18) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 20 - if (cycle == 19) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 21 - if (cycle == 20) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 22 - if (cycle == 21) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00100000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 23 - if (cycle == 22) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000110; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 24 - if (cycle == 23) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b10001010; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 25 - if (cycle == 24) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b11001111; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 26 - if (cycle == 25) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 27 - if (cycle == 26) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 28 - if (cycle == 27) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 29 - if (cycle == 28) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 30 - if (cycle == 29) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b1; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 31 - if (cycle == 30) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 32 - if (cycle == 31) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b1; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 33 - if (cycle == 32) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b1; - PI_rst <= 1'b0; - end - - // state 34 - if (cycle == 33) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b1; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 35 - if (cycle == 34) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 36 - if (cycle == 35) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 37 - if (cycle == 36) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - // state 38 - if (cycle == 37) begin - PI_write_mask <= 4'b0000; - PI_transaction_begin <= 1'b0; - PI_wait_latency <= 6'b000000; - PI_write_enable <= 1'b0; - PI_address <= 32'b00010010001101000101011001111000; - PI_done_latency <= 6'b000000; - PI_dq <= 8'b00000000; - PI_data_out <= 32'b11001100110011001101110111011101; - PI_timed_read <= 1'b0; - PI_rwds <= 1'b0; - PI_rst <= 1'b0; - end - - genclock <= cycle < 38; - cycle <= cycle + 1; - end -endmodule
diff --git a/verilog/rtl/unit_test/cover/logfile.txt b/verilog/rtl/unit_test/cover/logfile.txt deleted file mode 100644 index fb9283e..0000000 --- a/verilog/rtl/unit_test/cover/logfile.txt +++ /dev/null
@@ -1,115 +0,0 @@ -SBY 14:11:51 [cover] Copy '/root/mar20/tool/caravel_tutorial/caravel_example/verilog/rtl/original/hyperram.v' to '/root/mar20/tool/caravel_tutorial/caravel_example/verilog/rtl/unit_test/cover/src/hyperram.v'. -SBY 14:11:51 [cover] engine_0: smtbmc -SBY 14:11:51 [cover] base: starting process "cd cover/src; yosys -ql ../model/design.log ../model/design.ys" -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:51) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:52) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:96) -SBY 14:11:51 [cover] base: Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:97) -SBY 14:11:51 [cover] base: Warning: wire '\transaction_end' is assigned in a block at hyperram.v:98.3-98.22. -SBY 14:11:51 [cover] base: Warning: wire '\transaction_end' is assigned in a block at hyperram.v:106.5-106.24. -SBY 14:11:51 [cover] base: Warning: wire '\rst' is assigned in a block at hyperram.v:281.4-281.11. -SBY 14:11:51 [cover] base: Warning: wire '\address' is assigned in a block at hyperram.v:282.4-282.24. -SBY 14:11:51 [cover] base: Warning: wire '\data_in' is assigned in a block at hyperram.v:287.4-287.24. -SBY 14:11:51 [cover] base: Warning: wire '\data_out' is assigned in a block at hyperram.v:288.4-288.25. -SBY 14:11:51 [cover] base: Warning: wire '\rst' is assigned in a block at hyperram.v:292.4-292.11. -SBY 14:11:51 [cover] base: finished (returncode=0) -SBY 14:11:51 [cover] smt2: starting process "cd cover/model; yosys -ql design_smt2.log design_smt2.ys" -SBY 14:11:51 [cover] smt2: finished (returncode=0) -SBY 14:11:51 [cover] engine_0: starting process "cd cover; yosys-smtbmc --presat --unroll -c --noprogress -t 150 --append 0 --dump-vcd engine_0/trace%.vcd --dump-vlogtb engine_0/trace%_tb.v --dump-smtc engine_0/trace%.smtc model/design_smt2.smt2" -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Solver: yices -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 0.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 1.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_idle in step 1. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace0.vcd -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace0_tb.v -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace0.smtc -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 1.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 2.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 3.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 4.. -SBY 14:11:51 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 5.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 6.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 7.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_ca in step 7. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace1.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace1_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace1.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 7.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 8.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_wait in step 8. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace2.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace2_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace2.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 8.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 9.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 10.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 11.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 12.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_write in step 13. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace3.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace3_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace3.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_read in step 13. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace4.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace4_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace4.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 13.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 14.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 15.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 16.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 17.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Reached cover statement at cover_done in step 17. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to VCD file: engine_0/trace5.vcd -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace5_tb.v -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Writing trace to constraints file: engine_0/trace5.smtc -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 17.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 18.. -SBY 14:11:52 [cover] engine_0: ## 0:00:00 Checking cover reachability in step 19.. -SBY 14:11:52 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 20.. -SBY 14:11:52 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 21.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 22.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 23.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 24.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 25.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 26.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 27.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 28.. -SBY 14:11:53 [cover] engine_0: ## 0:00:01 Checking cover reachability in step 29.. -SBY 14:11:53 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 30.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 31.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 32.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 33.. -SBY 14:11:54 [cover] engine_0: ## 0:00:02 Checking cover reachability in step 34.. -SBY 14:11:54 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 35.. -SBY 14:11:55 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 36.. -SBY 14:11:55 [cover] engine_0: ## 0:00:03 Checking cover reachability in step 37.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Checking cover reachability in step 38.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Reached cover statement at cover_write_read in step 38. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to VCD file: engine_0/trace6.vcd -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to Verilog testbench: engine_0/trace6_tb.v -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to constraints file: engine_0/trace6.smtc -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Checking cover reachability in step 38.. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Reached cover statement at cover_write_2 in step 38. -SBY 14:11:56 [cover] engine_0: ## 0:00:04 Writing trace to VCD file: engine_0/trace7.vcd -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace7_tb.v -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to constraints file: engine_0/trace7.smtc -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Checking cover reachability in step 38.. -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Reached cover statement at cover_read_2 in step 38. -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to VCD file: engine_0/trace8.vcd -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace8_tb.v -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Writing trace to constraints file: engine_0/trace8.smtc -SBY 14:11:57 [cover] engine_0: ## 0:00:05 Status: passed -SBY 14:11:57 [cover] engine_0: finished (returncode=0) -SBY 14:11:57 [cover] engine_0: Status returned by engine: pass -SBY 14:11:57 [cover] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:05 (5) -SBY 14:11:57 [cover] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:05 (5) -SBY 14:11:57 [cover] summary: engine_0 (smtbmc) returned pass -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace0.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace1.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace2.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace3.vcd -SBY 14:11:57 [cover] summary: trace: cover/engine_0/trace4.vcd -SBY 14:11:57 [cover] summary: and 4 further traces -SBY 14:11:57 [cover] DONE (PASS, rc=0)
diff --git a/verilog/rtl/unit_test/cover/model/design.il b/verilog/rtl/unit_test/cover/model/design.il deleted file mode 100644 index 3025470..0000000 --- a/verilog/rtl/unit_test/cover/model/design.il +++ /dev/null
@@ -1,942 +0,0 @@ -# Generated by Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) -autoidx 429 -attribute \keep 1 -attribute \hdlname "\\hyperram" -attribute \top 1 -attribute \src "hyperram.v:1.1-308.10" -module \hyperram - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:296$1_CHECK[0:0]$51 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:297$2_CHECK[0:0]$53 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:298$3_CHECK[0:0]$55 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:299$4_CHECK[0:0]$57 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:300$5_CHECK[0:0]$59 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:301$6_CHECK[0:0]$61 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:302$7_CHECK[0:0]$63 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:303$8_CHECK[0:0]$65 - attribute \src "hyperram.v:295.3-305.6" - wire $0$formal$hyperram.v:304$9_CHECK[0:0]$67 - attribute \src "hyperram.v:32.2-39.5" - wire $0\ck[0:0] - attribute \src "hyperram.v:268.3-275.6" - wire width 6 $0\read_count[5:0] - attribute \src "hyperram.v:268.3-275.6" - wire width 6 $0\write_count[5:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 7 $2\next_control_state[6:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 8 $2\next_done_counter[7:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 8 $2\next_wait_counter[7:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 7 $3\next_control_state[6:0] - wire width 3 $4\next_control_state[6:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 7 $5\next_control_state[6:0] - attribute \src "hyperram.v:0.0-0.0" - wire width 7 $6\next_control_state[6:0] - wire width 7 $add$hyperram.v:109$23_Y - wire width 8 $add$hyperram.v:152$30_Y - wire width 8 $add$hyperram.v:225$40_Y - wire width 6 $add$hyperram.v:270$47_Y - wire width 6 $add$hyperram.v:273$49_Y - wire $auto$opt_reduce.cc:134:opt_pmux$418 - wire $auto$opt_reduce.cc:134:opt_pmux$420 - wire $auto$opt_reduce.cc:134:opt_pmux$422 - attribute \src "hyperram.v:154.8-154.36" - wire $eq$hyperram.v:154$31_Y - attribute \src "hyperram.v:227.8-227.36" - wire $eq$hyperram.v:227$41_Y - attribute \src "hyperram.v:269.7-269.28" - wire $eq$hyperram.v:269$46_Y - attribute \src "hyperram.v:272.7-272.28" - wire $eq$hyperram.v:272$48_Y - attribute \src "hyperram.v:304.29-304.44" - wire $eq$hyperram.v:304$77_Y - attribute \src "hyperram.v:304.48-304.64" - wire $eq$hyperram.v:304$78_Y - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:296$1_CHECK - attribute \init 1'0 - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:296$1_EN - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:297$2_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:298$3_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:299$4_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:300$5_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:301$6_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:302$7_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:303$8_CHECK - attribute \src "hyperram.v:0.0-0.0" - wire $formal$hyperram.v:304$9_CHECK - attribute \src "hyperram.v:201.8-201.26" - wire $logic_or$hyperram.v:201$35_Y - wire $procmux$213_CMP - wire $procmux$214_CMP - wire $procmux$217_CMP - wire $procmux$218_CMP - wire $procmux$222_CMP - wire $procmux$223_CMP - wire $procmux$224_CMP - wire $procmux$225_CMP - wire $procmux$226_CMP - attribute \src "hyperram.v:6.15-6.22" - wire width 32 input 3 \address - attribute \src "hyperram.v:16.9-16.11" - wire output 11 \ck - attribute \src "hyperram.v:17.9-17.15" - wire output 12 \ck_bar - attribute \src "hyperram.v:2.8-2.11" - wire input 1 \clk - attribute \src "hyperram.v:236.13-236.28" - wire width 48 \command_address - attribute \init 7'0000000 - attribute \src "hyperram.v:66.12-66.25" - wire width 7 \control_state - attribute \src "hyperram.v:18.9-18.15" - wire output 13 \cs_bar - attribute \src "hyperram.v:8.16-8.23" - wire width 32 output 5 \data_in - attribute \src "hyperram.v:70.13-70.29" - wire width 32 \data_in_register - attribute \src "hyperram.v:7.15-7.23" - wire width 32 input 4 \data_out - attribute \src "hyperram.v:242.13-242.30" - wire width 32 \data_out_register - attribute \init 8'00000000 - attribute \src "hyperram.v:62.12-62.24" - wire width 8 \done_counter - attribute \src "hyperram.v:24.14-24.26" - wire width 6 input 17 \done_latency - attribute \src "hyperram.v:15.14-15.16" - wire width 8 inout 10 \dq - attribute \src "hyperram.v:47.6-47.11" - wire \dq_oe - attribute \src "hyperram.v:46.12-46.18" - wire width 8 \dq_out - attribute \src "hyperram.v:237.13-237.33" - wire width 48 \next_command_address - attribute \src "hyperram.v:67.12-67.30" - wire width 7 \next_control_state - attribute \src "hyperram.v:243.13-243.35" - wire width 32 \next_data_out_register - attribute \src "hyperram.v:63.12-63.29" - wire width 8 \next_done_counter - attribute \src "hyperram.v:60.12-60.29" - wire width 8 \next_wait_counter - attribute \src "hyperram.v:240.12-240.36" - wire width 4 \next_write_mask_register - attribute \init 6'000000 - attribute \src "hyperram.v:265.13-265.23" - wire width 6 \read_count - attribute \src "hyperram.v:3.8-3.11" - wire input 2 \rst - attribute \src "hyperram.v:19.8-19.12" - wire inout 14 \rwds - attribute \src "hyperram.v:49.6-49.13" - wire \rwds_oe - attribute \src "hyperram.v:48.6-48.14" - wire \rwds_out - attribute \src "hyperram.v:22.8-22.18" - wire input 15 \timed_read - attribute \src "hyperram.v:11.8-11.25" - wire input 8 \transaction_begin - attribute \src "hyperram.v:12.9-12.24" - wire output 9 \transaction_end - attribute \init 8'00000000 - attribute \src "hyperram.v:59.12-59.24" - wire width 8 \wait_counter - attribute \src "hyperram.v:23.14-23.26" - wire width 6 input 16 \wait_latency - attribute \init 6'000000 - attribute \src "hyperram.v:266.13-266.24" - wire width 6 \write_count - attribute \src "hyperram.v:9.8-9.20" - wire input 6 \write_enable - attribute \src "hyperram.v:10.14-10.24" - wire width 4 input 7 \write_mask - attribute \src "hyperram.v:239.12-239.31" - wire width 4 \write_mask_register - attribute \src "hyperram.v:109.27-109.44" - cell $add $add$hyperram.v:109$23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 7 - connect \A \control_state - connect \B 1'1 - connect \Y $add$hyperram.v:109$23_Y - end - attribute \src "hyperram.v:152.25-152.41" - cell $add $add$hyperram.v:152$30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \wait_counter - connect \B 1'1 - connect \Y $add$hyperram.v:152$30_Y - end - attribute \src "hyperram.v:225.25-225.41" - cell $add $add$hyperram.v:225$40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \done_counter - connect \B 1'1 - connect \Y $add$hyperram.v:225$40_Y - end - attribute \src "hyperram.v:270.19-270.33" - cell $add $add$hyperram.v:270$47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \read_count - connect \B 1'1 - connect \Y $add$hyperram.v:270$47_Y - end - attribute \src "hyperram.v:273.20-273.35" - cell $add $add$hyperram.v:273$49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \write_count - connect \B 1'1 - connect \Y $add$hyperram.v:273$49_Y - end - cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \Y_WIDTH 1 - connect \A { $procmux$226_CMP $procmux$225_CMP $procmux$224_CMP $procmux$223_CMP $procmux$222_CMP $procmux$218_CMP $procmux$217_CMP $procmux$214_CMP $procmux$213_CMP $0$formal$hyperram.v:299$4_CHECK[0:0]$57 $0$formal$hyperram.v:297$2_CHECK[0:0]$53 $eq$hyperram.v:269$46_Y } - connect \Y $auto$opt_reduce.cc:134:opt_pmux$418 - end - cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { $procmux$218_CMP $procmux$217_CMP $0$formal$hyperram.v:299$4_CHECK[0:0]$57 $eq$hyperram.v:272$48_Y } - connect \Y $auto$opt_reduce.cc:134:opt_pmux$420 - end - cell $reduce_or $auto$opt_reduce.cc:128:opt_pmux$421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A { $procmux$226_CMP $procmux$225_CMP $procmux$224_CMP $procmux$223_CMP $procmux$222_CMP $procmux$218_CMP $procmux$217_CMP $0$formal$hyperram.v:299$4_CHECK[0:0]$57 $0$formal$hyperram.v:297$2_CHECK[0:0]$53 $eq$hyperram.v:272$48_Y } - connect \Y $auto$opt_reduce.cc:134:opt_pmux$422 - end - attribute \src "hyperram.v:154.8-154.36" - cell $eq $eq$hyperram.v:154$31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \wait_counter - connect \B 3'100 - connect \Y $eq$hyperram.v:154$31_Y - end - attribute \src "hyperram.v:227.8-227.36" - cell $eq $eq$hyperram.v:227$41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \done_counter - connect \B 3'100 - connect \Y $eq$hyperram.v:227$41_Y - end - attribute \src "hyperram.v:269.7-269.28" - cell $eq $eq$hyperram.v:269$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1111 - connect \Y $eq$hyperram.v:269$46_Y - end - attribute \src "hyperram.v:272.7-272.28" - cell $eq $eq$hyperram.v:272$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1011 - connect \Y $eq$hyperram.v:272$48_Y - end - attribute \src "hyperram.v:296.23-296.41" - cell $logic_not $eq$hyperram.v:296$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \Y $0$formal$hyperram.v:296$1_CHECK[0:0]$51 - end - attribute \src "hyperram.v:297.21-297.39" - cell $eq $eq$hyperram.v:297$70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 3'110 - connect \Y $0$formal$hyperram.v:297$2_CHECK[0:0]$53 - end - attribute \src "hyperram.v:298.23-298.41" - cell $eq $eq$hyperram.v:298$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 3'111 - connect \Y $0$formal$hyperram.v:298$3_CHECK[0:0]$55 - end - attribute \src "hyperram.v:299.24-299.42" - cell $eq $eq$hyperram.v:299$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1000 - connect \Y $0$formal$hyperram.v:299$4_CHECK[0:0]$57 - end - attribute \src "hyperram.v:300.23-300.43" - cell $eq $eq$hyperram.v:300$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1100 - connect \Y $0$formal$hyperram.v:300$5_CHECK[0:0]$59 - end - attribute \src "hyperram.v:301.23-301.44" - cell $eq $eq$hyperram.v:301$74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 5'10000 - connect \Y $0$formal$hyperram.v:301$6_CHECK[0:0]$61 - end - attribute \src "hyperram.v:302.26-302.44" - cell $eq $eq$hyperram.v:302$75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \write_count - connect \B 2'10 - connect \Y $0$formal$hyperram.v:302$7_CHECK[0:0]$63 - end - attribute \src "hyperram.v:303.25-303.42" - cell $eq $eq$hyperram.v:303$76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \read_count - connect \B 2'10 - connect \Y $0$formal$hyperram.v:303$8_CHECK[0:0]$65 - end - attribute \src "hyperram.v:304.29-304.44" - cell $eq $eq$hyperram.v:304$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \read_count - connect \B 1'1 - connect \Y $eq$hyperram.v:304$77_Y - end - attribute \src "hyperram.v:304.48-304.64" - cell $eq $eq$hyperram.v:304$78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \write_count - connect \B 1'1 - connect \Y $eq$hyperram.v:304$78_Y - end - attribute \src "hyperram.v:304.29-304.64" - cell $logic_and $logic_and$hyperram.v:304$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$hyperram.v:304$77_Y - connect \B $eq$hyperram.v:304$78_Y - connect \Y $0$formal$hyperram.v:304$9_CHECK[0:0]$67 - end - attribute \src "hyperram.v:253.4-253.17" - cell $logic_not $logic_not$hyperram.v:253$44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \write_enable - connect \Y \next_command_address [47] - end - attribute \src "hyperram.v:37.10-37.13" - cell $logic_not $logic_not$hyperram.v:37$12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ck - connect \Y \ck_bar - end - attribute \src "hyperram.v:201.8-201.26" - cell $logic_or $logic_or$hyperram.v:201$35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rwds - connect \B \timed_read - connect \Y $logic_or$hyperram.v:201$35_Y - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$389 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:296$1_CHECK[0:0]$51 - connect \Q $formal$hyperram.v:296$1_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$390 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D 1'1 - connect \Q $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$391 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:297$2_CHECK[0:0]$53 - connect \Q $formal$hyperram.v:297$2_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$393 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:298$3_CHECK[0:0]$55 - connect \Q $formal$hyperram.v:298$3_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$395 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:299$4_CHECK[0:0]$57 - connect \Q $formal$hyperram.v:299$4_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$397 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:300$5_CHECK[0:0]$59 - connect \Q $formal$hyperram.v:300$5_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$399 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:301$6_CHECK[0:0]$61 - connect \Q $formal$hyperram.v:301$6_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$401 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:302$7_CHECK[0:0]$63 - connect \Q $formal$hyperram.v:302$7_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$403 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:303$8_CHECK[0:0]$65 - connect \Q $formal$hyperram.v:303$8_CHECK - end - attribute \src "hyperram.v:295.3-305.6" - cell $dff $procdff$405 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0$formal$hyperram.v:304$9_CHECK[0:0]$67 - connect \Q $formal$hyperram.v:304$9_CHECK - end - attribute \always_ff 1 - attribute \src "hyperram.v:268.3-275.6" - cell $dff $procdff$407 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 6 - connect \CLK \clk - connect \D $0\read_count[5:0] - connect \Q \read_count - end - attribute \always_ff 1 - attribute \src "hyperram.v:268.3-275.6" - cell $dff $procdff$408 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 6 - connect \CLK \clk - connect \D $0\write_count[5:0] - connect \Q \write_count - end - attribute \always_ff 1 - attribute \src "hyperram.v:245.2-249.5" - cell $dff $procdff$409 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 48 - connect \CLK \transaction_begin - connect \D { \next_command_address [47] 47'01000000000011010001010110011110000000000000000 } - connect \Q \command_address - end - attribute \always_ff 1 - attribute \src "hyperram.v:245.2-249.5" - cell $dff $procdff$410 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 4 - connect \CLK \transaction_begin - connect \D \write_mask - connect \Q \write_mask_register - end - attribute \always_ff 1 - attribute \src "hyperram.v:245.2-249.5" - cell $dff $procdff$411 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 31 - connect \CLK \transaction_begin - connect \D 31'1001100110011001101110111011101 - connect \Q \data_out_register [30:0] - end - attribute \always_ff 1 - attribute \src "hyperram.v:72.2-85.5" - cell $dff $procdff$412 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 8 - connect \CLK \clk - connect \D \next_wait_counter - connect \Q \wait_counter - end - attribute \always_ff 1 - attribute \src "hyperram.v:72.2-85.5" - cell $dff $procdff$413 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 8 - connect \CLK \clk - connect \D \next_done_counter - connect \Q \done_counter - end - attribute \always_ff 1 - attribute \src "hyperram.v:72.2-85.5" - cell $dff $procdff$414 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 7 - connect \CLK \clk - connect \D \next_control_state - connect \Q \control_state - end - attribute \always_ff 1 - attribute \src "hyperram.v:32.2-39.5" - cell $dff $procdff$416 - parameter \CLK_POLARITY 1'1 - parameter \WIDTH 1 - connect \CLK \clk - connect \D $0\ck[0:0] - connect \Q \ck - end - attribute \src "hyperram.v:269.7-269.28|hyperram.v:269.4-271.7" - cell $mux $procmux$101 - parameter \WIDTH 6 - connect \A \read_count - connect \B $add$hyperram.v:270$47_Y - connect \S $eq$hyperram.v:269$46_Y - connect \Y $0\read_count[5:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:227.8-227.36|hyperram.v:227.5-230.8" - cell $mux $procmux$109 - parameter \WIDTH 7 - connect \A \control_state - connect \B 7'0000000 - connect \S $eq$hyperram.v:227$41_Y - connect \Y $6\next_control_state[6:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:227.8-227.36|hyperram.v:227.5-230.8" - cell $mux $procmux$120 - parameter \WIDTH 8 - connect \A $add$hyperram.v:225$40_Y - connect \B 8'00000000 - connect \S $eq$hyperram.v:227$41_Y - connect \Y $2\next_done_counter[7:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:201.8-201.26|hyperram.v:201.5-204.8" - cell $mux $procmux$153 - parameter \WIDTH 7 - connect \A \control_state - connect \B $add$hyperram.v:109$23_Y - connect \S $logic_or$hyperram.v:201$35_Y - connect \Y $5\next_control_state[6:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:154.8-154.36|hyperram.v:154.5-162.8" - cell $mux $procmux$168 - parameter \WIDTH 7 - connect \A \control_state - connect \B { 4'0001 $4\next_control_state[6:0] } - connect \S $eq$hyperram.v:154$31_Y - connect \Y $3\next_control_state[6:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:154.8-154.36|hyperram.v:154.5-162.8" - cell $mux $procmux$183 - parameter \WIDTH 8 - connect \A $add$hyperram.v:152$30_Y - connect \B 8'00000000 - connect \S $eq$hyperram.v:154$31_Y - connect \Y $2\next_wait_counter[7:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:108.8-108.25|hyperram.v:108.5-110.8" - cell $mux $procmux$205 - parameter \WIDTH 7 - connect \A \control_state - connect \B $add$hyperram.v:109$23_Y - connect \S \transaction_begin - connect \Y $2\next_control_state[6:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $pmux $procmux$210 - parameter \S_WIDTH 6 - parameter \WIDTH 7 - connect \A \control_state - connect \B { $2\next_control_state[6:0] $3\next_control_state[6:0] 7'0010000 $5\next_control_state[6:0] $add$hyperram.v:109$23_Y $6\next_control_state[6:0] } - connect \S { $0$formal$hyperram.v:296$1_CHECK[0:0]$51 $0$formal$hyperram.v:298$3_CHECK[0:0]$55 $eq$hyperram.v:272$48_Y $0$formal$hyperram.v:300$5_CHECK[0:0]$59 $auto$opt_reduce.cc:134:opt_pmux$418 $0$formal$hyperram.v:301$6_CHECK[0:0]$61 } - connect \Y \next_control_state - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$213_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1110 - connect \Y $procmux$213_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$214_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1101 - connect \Y $procmux$214_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$217_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1010 - connect \Y $procmux$217_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$218_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 4'1001 - connect \Y $procmux$218_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$222_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 3'101 - connect \Y $procmux$222_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$223_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 3'100 - connect \Y $procmux$223_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$224_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 2'11 - connect \Y $procmux$224_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$225_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 2'10 - connect \Y $procmux$225_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $eq $procmux$226_CMP0 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \control_state - connect \B 1'1 - connect \Y $procmux$226_CMP - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $mux $procmux$245 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S $0$formal$hyperram.v:296$1_CHECK[0:0]$51 - connect \Y \transaction_end - end - attribute \full_case 1 - attribute \src "hyperram.v:156.9-156.30|hyperram.v:156.6-161.9" - cell $mux $procmux$297 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \command_address [47] - connect \Y $4\next_control_state[6:0] - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $mux $procmux$304 - parameter \WIDTH 8 - connect \A \done_counter - connect \B $2\next_done_counter[7:0] - connect \S $0$formal$hyperram.v:301$6_CHECK[0:0]$61 - connect \Y \next_done_counter - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $mux $procmux$316 - parameter \WIDTH 8 - connect \A \wait_counter - connect \B $2\next_wait_counter[7:0] - connect \S $0$formal$hyperram.v:298$3_CHECK[0:0]$55 - connect \Y \next_wait_counter - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $mux $procmux$324 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S $auto$opt_reduce.cc:134:opt_pmux$420 - connect \Y \rwds_oe - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $pmux $procmux$335 - parameter \S_WIDTH 4 - parameter \WIDTH 1 - connect \A 1'x - connect \B { \write_mask_register [0] \write_mask_register [1] \write_mask_register [2] \write_mask_register [3] } - connect \S { $0$formal$hyperram.v:299$4_CHECK[0:0]$57 $procmux$218_CMP $procmux$217_CMP $eq$hyperram.v:272$48_Y } - connect \Y \rwds_out - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $mux $procmux$346 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S $auto$opt_reduce.cc:134:opt_pmux$422 - connect \Y \dq_oe - end - attribute \full_case 1 - attribute \src "hyperram.v:0.0-0.0|hyperram.v:101.3-232.10" - cell $pmux $procmux$363 - parameter \S_WIDTH 10 - parameter \WIDTH 8 - connect \A 8'x - connect \B { \command_address \data_out_register [7:0] \data_out_register [15:8] \data_out_register [23:16] \data_out_register [30] \data_out_register [30:24] } - connect \S { $procmux$226_CMP $procmux$225_CMP $procmux$224_CMP $procmux$223_CMP $procmux$222_CMP $0$formal$hyperram.v:297$2_CHECK[0:0]$53 $0$formal$hyperram.v:299$4_CHECK[0:0]$57 $procmux$218_CMP $procmux$217_CMP $eq$hyperram.v:272$48_Y } - connect \Y \dq_out - end - attribute \full_case 1 - attribute \src "hyperram.v:33.6-33.14|hyperram.v:33.3-38.6" - cell $mux $procmux$387 - parameter \WIDTH 1 - connect \A \ck_bar - connect \B 1'0 - connect \S $0$formal$hyperram.v:296$1_CHECK[0:0]$51 - connect \Y $0\ck[0:0] - end - attribute \src "hyperram.v:272.7-272.28|hyperram.v:272.4-274.7" - cell $mux $procmux$99 - parameter \WIDTH 6 - connect \A \write_count - connect \B $add$hyperram.v:273$49_Y - connect \S $eq$hyperram.v:272$48_Y - connect \Y $0\write_count[5:0] - end - attribute \src "hyperram.v:51.14-51.35" - cell $mux $ternary$hyperram.v:51$16 - parameter \WIDTH 8 - connect \A 8'x - connect \B \dq_out - connect \S \dq_oe - connect \Y \dq - end - attribute \src "hyperram.v:52.16-52.41" - cell $mux $ternary$hyperram.v:52$19 - parameter \WIDTH 1 - connect \A 1'x - connect \B \rwds_out - connect \S \rwds_oe - connect \Y \rwds - end - attribute \src "hyperram.v:297.4-297.40" - cell $cover \cover_ca - connect \A $formal$hyperram.v:297$2_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:301.4-301.45" - cell $cover \cover_done - connect \A $formal$hyperram.v:301$6_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:296.4-296.42" - cell $cover \cover_idle - connect \A $formal$hyperram.v:296$1_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:300.4-300.44" - cell $cover \cover_read - connect \A $formal$hyperram.v:300$5_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:303.4-303.43" - cell $cover \cover_read_2 - connect \A $formal$hyperram.v:303$8_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:298.4-298.42" - cell $cover \cover_wait - connect \A $formal$hyperram.v:298$3_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:299.4-299.43" - cell $cover \cover_write - connect \A $formal$hyperram.v:299$4_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:302.4-302.45" - cell $cover \cover_write_2 - connect \A $formal$hyperram.v:302$7_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - attribute \src "hyperram.v:304.4-304.65" - cell $cover \cover_write_read - connect \A $formal$hyperram.v:304$9_CHECK - connect \EN $formal$hyperram.v:296$1_EN - end - connect \address 305419896 - connect \cs_bar \transaction_end - connect \data_in 32'10101010101010101011101110111011 - connect \data_in_register 32'10101010101010101011101110111011 - connect \data_out 32'11001100110011001101110111011101 - connect \data_out_register [31] \data_out_register [30] - connect \next_command_address [46:0] 47'01000000000011010001010110011110000000000000000 - connect \next_data_out_register 32'11001100110011001101110111011101 - connect \next_write_mask_register \write_mask - connect \rst 1'0 -end
diff --git a/verilog/rtl/unit_test/cover/model/design.json b/verilog/rtl/unit_test/cover/model/design.json deleted file mode 100644 index 1945b1b..0000000 --- a/verilog/rtl/unit_test/cover/model/design.json +++ /dev/null
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diff --git a/verilog/rtl/unit_test/cover/model/design.log b/verilog/rtl/unit_test/cover/model/design.log deleted file mode 100644 index d902d1f..0000000 --- a/verilog/rtl/unit_test/cover/model/design.log +++ /dev/null
@@ -1,453 +0,0 @@ - - /----------------------------------------------------------------------------\ - | | - | yosys -- Yosys Open SYnthesis Suite | - | | - | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | - | | - | Permission to use, copy, modify, and/or distribute this software for any | - | purpose with or without fee is hereby granted, provided that the above | - | copyright notice and this permission notice appear in all copies. | - | | - | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | - | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | - | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | - | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | - | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | - | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | - | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | - | | - \----------------------------------------------------------------------------/ - - Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) - - --- Executing script file `../model/design.ys' -- - -1. Executing Verilog-2005 frontend: hyperram.v -Parsing formal SystemVerilog input from `hyperram.v' to AST representation. -Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:51) -Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:52) -Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:96) -Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:97) -Storing AST representation for module `$abstract\hyperram'. -Successfully finished Verilog frontend. - -2. Executing PREP pass. - -2.1. Executing HIERARCHY pass (managing design hierarchy). - -2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\hyperram'. -Generating RTLIL representation for module `\hyperram'. -Warning: wire '\transaction_end' is assigned in a block at hyperram.v:98.3-98.22. -Warning: wire '\transaction_end' is assigned in a block at hyperram.v:106.5-106.24. -Warning: wire '\rst' is assigned in a block at hyperram.v:281.4-281.11. -Warning: wire '\address' is assigned in a block at hyperram.v:282.4-282.24. -Warning: wire '\data_in' is assigned in a block at hyperram.v:287.4-287.24. -Warning: wire '\data_out' is assigned in a block at hyperram.v:288.4-288.25. -Warning: wire '\rst' is assigned in a block at hyperram.v:292.4-292.11. - -2.2.1. Analyzing design hierarchy.. -Top module: \hyperram - -2.2.2. Analyzing design hierarchy.. -Top module: \hyperram -Removing unused module `$abstract\hyperram'. -Removed 1 unused modules. -Module hyperram directly or indirectly contains formal properties -> setting "keep" attribute. - -2.3. Executing PROC pass (convert processes to netlists). - -2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 6 switch rules as full_case in process $proc$hyperram.v:0$22 in module hyperram. -Marked 1 switch rules as full_case in process $proc$hyperram.v:72$21 in module hyperram. -Marked 1 switch rules as full_case in process $proc$hyperram.v:32$10 in module hyperram. -Removed a total of 0 dead cases. - -2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 5 redundant assignments. -Promoted 53 assignments to connections. - -2.3.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\hyperram.$proc$hyperram.v:0$97'. - Set init value: $formal$hyperram.v:304$9_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$95'. - Set init value: $formal$hyperram.v:303$8_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$93'. - Set init value: $formal$hyperram.v:302$7_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$91'. - Set init value: $formal$hyperram.v:301$6_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$89'. - Set init value: $formal$hyperram.v:300$5_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$87'. - Set init value: $formal$hyperram.v:299$4_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$85'. - Set init value: $formal$hyperram.v:298$3_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$83'. - Set init value: $formal$hyperram.v:297$2_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$81'. - Set init value: $formal$hyperram.v:296$1_EN = 1'0 -Found init rule in `\hyperram.$proc$hyperram.v:0$80'. - Set init value: \wait_counter = 8'00000000 - Set init value: \done_counter = 8'00000000 - Set init value: \control_state = 7'0000000 - Set init value: \read_count = 6'000000 - Set init value: \write_count = 6'000000 - -2.3.5. Executing PROC_ARST pass (detect async resets in processes). - -2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\hyperram.$proc$hyperram.v:0$97'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$95'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$93'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$91'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$89'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$87'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$85'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$83'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$81'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$80'. -Creating decoders for process `\hyperram.$proc$hyperram.v:295$50'. -Creating decoders for process `\hyperram.$proc$hyperram.v:268$45'. - 1/2: $0\write_count[5:0] - 2/2: $0\read_count[5:0] -Creating decoders for process `\hyperram.$proc$hyperram.v:0$43'. -Creating decoders for process `\hyperram.$proc$hyperram.v:245$42'. -Creating decoders for process `\hyperram.$proc$hyperram.v:0$22'. - 1/22: $1\next_data_in[31:0] [31:24] - 2/22: $6\next_control_state[6:0] - 3/22: $1\next_data_in[31:0] [23:16] - 4/22: $2\next_done_counter[7:0] - 5/22: $1\next_data_in[31:0] [15:8] - 6/22: $2\next_data_in[7:0] - 7/22: $1\next_data_in[31:0] [7:0] - 8/22: $5\next_control_state[6:0] - 9/22: $3\next_control_state[6:0] - 10/22: $2\next_wait_counter[7:0] - 11/22: $2\next_control_state[6:0] - 12/22: $1\next_control_state[6:0] - 13/22: $1\transaction_end[0:0] - 14/22: $1\ck_gate[0:0] - 15/22: $1\cs_bar[0:0] - 16/22: $4\next_control_state[6:0] - 17/22: $1\next_done_counter[7:0] - 18/22: $1\next_wait_counter[7:0] - 19/22: $1\rwds_oe[0:0] - 20/22: $1\rwds_out[0:0] - 21/22: $1\dq_oe[0:0] - 22/22: $1\dq_out[7:0] -Creating decoders for process `\hyperram.$proc$hyperram.v:72$21'. - 1/4: $0\done_counter[7:0] - 2/4: $0\wait_counter[7:0] - 3/4: $0\data_in_register[31:0] - 4/4: $0\control_state[6:0] -Creating decoders for process `\hyperram.$proc$hyperram.v:32$10'. - 1/1: $0\ck[0:0] - -2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). -No latch inferred for signal `\hyperram.\rst' from process `\hyperram.$proc$hyperram.v:0$80'. -No latch inferred for signal `\hyperram.\address' from process `\hyperram.$proc$hyperram.v:0$80'. -No latch inferred for signal `\hyperram.\data_out' from process `\hyperram.$proc$hyperram.v:0$80'. -No latch inferred for signal `\hyperram.\data_in_register' from process `\hyperram.$proc$hyperram.v:0$80'. -No latch inferred for signal `\hyperram.\next_command_address' from process `\hyperram.$proc$hyperram.v:0$43'. -No latch inferred for signal `\hyperram.\next_write_mask_register' from process `\hyperram.$proc$hyperram.v:0$43'. -No latch inferred for signal `\hyperram.\next_data_out_register' from process `\hyperram.$proc$hyperram.v:0$43'. -No latch inferred for signal `\hyperram.\transaction_end' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\cs_bar' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\ck_gate' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\dq_out' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\dq_oe' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\rwds_out' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\rwds_oe' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\next_wait_counter' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\next_done_counter' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\next_control_state' from process `\hyperram.$proc$hyperram.v:0$22'. -No latch inferred for signal `\hyperram.\next_data_in' from process `\hyperram.$proc$hyperram.v:0$22'. - -2.3.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\hyperram.$formal$hyperram.v:296$1_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$389' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:296$1_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$390' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:297$2_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$391' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:297$2_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$392' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:298$3_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$393' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:298$3_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$394' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:299$4_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$395' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:299$4_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$396' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:300$5_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$397' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:300$5_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$398' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:301$6_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$399' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:301$6_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$400' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:302$7_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$401' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:302$7_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$402' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:303$8_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$403' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:303$8_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$404' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:304$9_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$405' with positive edge clock. -Creating register for signal `\hyperram.$formal$hyperram.v:304$9_EN' using process `\hyperram.$proc$hyperram.v:295$50'. - created $dff cell `$procdff$406' with positive edge clock. -Creating register for signal `\hyperram.\read_count' using process `\hyperram.$proc$hyperram.v:268$45'. - created $dff cell `$procdff$407' with positive edge clock. -Creating register for signal `\hyperram.\write_count' using process `\hyperram.$proc$hyperram.v:268$45'. - created $dff cell `$procdff$408' with positive edge clock. -Creating register for signal `\hyperram.\command_address' using process `\hyperram.$proc$hyperram.v:245$42'. - created $dff cell `$procdff$409' with positive edge clock. -Creating register for signal `\hyperram.\write_mask_register' using process `\hyperram.$proc$hyperram.v:245$42'. - created $dff cell `$procdff$410' with positive edge clock. -Creating register for signal `\hyperram.\data_out_register' using process `\hyperram.$proc$hyperram.v:245$42'. - created $dff cell `$procdff$411' with positive edge clock. -Creating register for signal `\hyperram.\wait_counter' using process `\hyperram.$proc$hyperram.v:72$21'. - created $dff cell `$procdff$412' with positive edge clock. -Creating register for signal `\hyperram.\done_counter' using process `\hyperram.$proc$hyperram.v:72$21'. - created $dff cell `$procdff$413' with positive edge clock. -Creating register for signal `\hyperram.\control_state' using process `\hyperram.$proc$hyperram.v:72$21'. - created $dff cell `$procdff$414' with positive edge clock. -Creating register for signal `\hyperram.\data_in_register' using process `\hyperram.$proc$hyperram.v:72$21'. - created $dff cell `$procdff$415' with positive edge clock. -Creating register for signal `\hyperram.\ck' using process `\hyperram.$proc$hyperram.v:32$10'. - created $dff cell `$procdff$416' with positive edge clock. - -2.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). - -2.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `hyperram.$proc$hyperram.v:0$97'. -Removing empty process `hyperram.$proc$hyperram.v:0$95'. -Removing empty process `hyperram.$proc$hyperram.v:0$93'. -Removing empty process `hyperram.$proc$hyperram.v:0$91'. -Removing empty process `hyperram.$proc$hyperram.v:0$89'. -Removing empty process `hyperram.$proc$hyperram.v:0$87'. -Removing empty process `hyperram.$proc$hyperram.v:0$85'. -Removing empty process `hyperram.$proc$hyperram.v:0$83'. -Removing empty process `hyperram.$proc$hyperram.v:0$81'. -Removing empty process `hyperram.$proc$hyperram.v:0$80'. -Removing empty process `hyperram.$proc$hyperram.v:295$50'. -Found and cleaned up 2 empty switches in `\hyperram.$proc$hyperram.v:268$45'. -Removing empty process `hyperram.$proc$hyperram.v:268$45'. -Removing empty process `hyperram.$proc$hyperram.v:0$43'. -Removing empty process `hyperram.$proc$hyperram.v:245$42'. -Found and cleaned up 6 empty switches in `\hyperram.$proc$hyperram.v:0$22'. -Removing empty process `hyperram.$proc$hyperram.v:0$22'. -Found and cleaned up 1 empty switch in `\hyperram.$proc$hyperram.v:72$21'. -Removing empty process `hyperram.$proc$hyperram.v:72$21'. -Found and cleaned up 1 empty switch in `\hyperram.$proc$hyperram.v:32$10'. -Removing empty process `hyperram.$proc$hyperram.v:32$10'. -Cleaned up 10 empty switches. - -2.3.11. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. -<suppressed ~14 debug messages> - -2.4. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -2.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. -Removed 16 unused cells and 131 unused wires. -<suppressed ~22 debug messages> - -2.6. Executing CHECK pass (checking for obvious problems). -Checking module hyperram... -Found and reported 0 problems. - -2.7. Executing OPT pass (performing simple optimizations). - -2.7.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -2.7.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -<suppressed ~210 debug messages> -Removed a total of 70 cells. - -2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \hyperram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. - dead port 2/2 on $mux $procmux$155. - dead port 2/2 on $mux $procmux$170. - dead port 2/2 on $mux $procmux$185. - dead port 2/2 on $mux $procmux$207. - dead port 2/2 on $mux $procmux$299. - dead port 2/2 on $mux $procmux$301. - dead port 2/2 on $mux $procmux$111. - dead port 2/2 on $mux $procmux$122. -Removed 8 multiplexer ports. -<suppressed ~12 debug messages> - -2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \hyperram. - New ctrl vector for $pmux cell $procmux$210: { $0$formal$hyperram.v:296$1_CHECK[0:0]$51 $0$formal$hyperram.v:298$3_CHECK[0:0]$55 $eq$hyperram.v:272$48_Y $0$formal$hyperram.v:300$5_CHECK[0:0]$59 $auto$opt_reduce.cc:134:opt_pmux$418 $0$formal$hyperram.v:301$6_CHECK[0:0]$61 } - New ctrl vector for $pmux cell $procmux$324: $auto$opt_reduce.cc:134:opt_pmux$420 - New ctrl vector for $pmux cell $procmux$346: $auto$opt_reduce.cc:134:opt_pmux$422 - Optimizing cells in module \hyperram. -Performed a total of 3 changes. - -2.7.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -<suppressed ~3 debug messages> -Removed a total of 1 cells. - -2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. -Removed 0 unused cells and 78 unused wires. -<suppressed ~1 debug messages> - -2.7.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -2.7.8. Rerunning OPT passes. (Maybe there is more to do..) - -2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \hyperram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. -<suppressed ~11 debug messages> - -2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \hyperram. -Performed a total of 0 changes. - -2.7.11. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -Removed a total of 0 cells. - -2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. - -2.7.13. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -2.7.14. Finished OPT passes. (There is nothing left to do.) - -2.8. Executing WREDUCE pass (reducing word size of cells). -Removed top 24 bits (of 32) from mux cell hyperram.$ternary$hyperram.v:51$16 ($mux). -Removed top 31 bits (of 32) from mux cell hyperram.$ternary$hyperram.v:52$19 ($mux). -Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:109$23 ($add). -Removed top 25 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:109$23 ($add). -Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:152$30 ($add). -Removed top 24 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:152$30 ($add). -Removed top 5 bits (of 8) from port B of cell hyperram.$eq$hyperram.v:154$31 ($eq). -Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:225$40 ($add). -Removed top 24 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:225$40 ($add). -Removed top 5 bits (of 8) from port B of cell hyperram.$eq$hyperram.v:227$41 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:269$46 ($eq). -Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:270$47 ($add). -Removed top 26 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:270$47 ($add). -Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:272$48 ($eq). -Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:273$49 ($add). -Removed top 26 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:273$49 ($add). -Removed top 4 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:297$70 ($eq). -Removed top 4 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:298$71 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:299$72 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:300$73 ($eq). -Removed top 2 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:301$74 ($eq). -Removed top 4 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:302$75 ($eq). -Removed top 4 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:303$76 ($eq). -Removed top 5 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:304$77 ($eq). -Removed top 5 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:304$78 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$213_CMP0 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$214_CMP0 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$217_CMP0 ($eq). -Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$218_CMP0 ($eq). -Removed top 4 bits (of 7) from port B of cell hyperram.$procmux$222_CMP0 ($eq). -Removed top 4 bits (of 7) from port B of cell hyperram.$procmux$223_CMP0 ($eq). -Removed top 5 bits (of 7) from port B of cell hyperram.$procmux$224_CMP0 ($eq). -Removed top 5 bits (of 7) from port B of cell hyperram.$procmux$225_CMP0 ($eq). -Removed top 6 bits (of 7) from port B of cell hyperram.$procmux$226_CMP0 ($eq). -Removed top 4 bits (of 7) from mux cell hyperram.$procmux$297 ($mux). -Removed top 1 bits (of 32) from FF cell hyperram.$procdff$411 ($dff). -Removed top 4 bits (of 7) from wire hyperram.$4\next_control_state[6:0]. -Removed top 25 bits (of 32) from wire hyperram.$add$hyperram.v:109$23_Y. -Removed top 24 bits (of 32) from wire hyperram.$add$hyperram.v:152$30_Y. -Removed top 24 bits (of 32) from wire hyperram.$add$hyperram.v:225$40_Y. -Removed top 26 bits (of 32) from wire hyperram.$add$hyperram.v:270$47_Y. -Removed top 26 bits (of 32) from wire hyperram.$add$hyperram.v:273$49_Y. - -2.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. -Removed 0 unused cells and 8 unused wires. -<suppressed ~1 debug messages> - -2.10. Executing MEMORY_COLLECT pass (generating $mem cells). - -2.11. Executing OPT pass (performing simple optimizations). - -2.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -2.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -Removed a total of 0 cells. - -2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. - -2.11.4. Finished fast OPT passes. - -2.12. Printing statistics. - -=== hyperram === - - Number of wires: 89 - Number of wire bits: 532 - Number of public wires: 36 - Number of public wire bits: 399 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 83 - $add 5 - $cover 9 - $dff 19 - $eq 22 - $logic_and 1 - $logic_not 3 - $logic_or 1 - $mux 17 - $pmux 3 - $reduce_or 3 - -2.13. Executing CHECK pass (checking for obvious problems). -Checking module hyperram... -Found and reported 0 problems. - -3. Executing HIERARCHY pass (managing design hierarchy). - -3.1. Analyzing design hierarchy.. -Top module: \hyperram - -3.2. Analyzing design hierarchy.. -Top module: \hyperram -Removed 0 unused modules. -Module hyperram directly or indirectly contains formal properties -> setting "keep" attribute. - -4. Executing JSON backend. - -5. Executing RTLIL backend. -Output filename: ../model/design.il - -Warnings: 11 unique messages, 11 total -End of script. Logfile hash: 207fb7cd4a, CPU: user 0.11s system 0.00s, MEM: 13.46 MB peak -Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) -Time spent: 21% 5x opt_clean (0 sec), 17% 6x opt_expr (0 sec), ...
diff --git a/verilog/rtl/unit_test/cover/model/design.ys b/verilog/rtl/unit_test/cover/model/design.ys deleted file mode 100644 index f3f87df..0000000 --- a/verilog/rtl/unit_test/cover/model/design.ys +++ /dev/null
@@ -1,7 +0,0 @@ -# running in cover/src/ -read -formal hyperram.v -prep -top hyperram - -hierarchy -simcheck -write_json ../model/design.json -write_rtlil ../model/design.il
diff --git a/verilog/rtl/unit_test/cover/model/design_smt2.log b/verilog/rtl/unit_test/cover/model/design_smt2.log deleted file mode 100644 index ea5300f..0000000 --- a/verilog/rtl/unit_test/cover/model/design_smt2.log +++ /dev/null
@@ -1,132 +0,0 @@ - - /----------------------------------------------------------------------------\ - | | - | yosys -- Yosys Open SYnthesis Suite | - | | - | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | - | | - | Permission to use, copy, modify, and/or distribute this software for any | - | purpose with or without fee is hereby granted, provided that the above | - | copyright notice and this permission notice appear in all copies. | - | | - | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | - | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | - | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | - | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | - | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | - | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | - | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | - | | - \----------------------------------------------------------------------------/ - - Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) - - --- Executing script file `design_smt2.ys' -- - -1. Executing RTLIL frontend. -Input filename: design.il - -2. Executing MEMORY_NORDFF pass (extracting $dff cells from memories). - -3. Executing ASYNC2SYNC pass. - -4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. - -5. Executing SETUNDEF pass (replace undef values with defined constants). - -6. Executing OPT pass (performing simple optimizations). - -6.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. - -6.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -Removed a total of 0 cells. - -6.3. Executing OPT_DFF pass (perform DFF optimizations). -Adding SRST signal on $procdff$416 ($dff) from module hyperram (D = \ck_bar, Q = \ck, rval = 1'0). -Adding EN signal on $procdff$414 ($dff) from module hyperram (D = \next_control_state, Q = \control_state). -Adding EN signal on $procdff$413 ($dff) from module hyperram (D = $2\next_done_counter[7:0], Q = \done_counter). -Adding SRST signal on $auto$ff.cc:262:slice$451 ($dffe) from module hyperram (D = $add$hyperram.v:225$40_Y, Q = \done_counter, rval = 8'00000000). -Adding EN signal on $procdff$412 ($dff) from module hyperram (D = $2\next_wait_counter[7:0], Q = \wait_counter). -Adding SRST signal on $auto$ff.cc:262:slice$453 ($dffe) from module hyperram (D = $add$hyperram.v:152$30_Y, Q = \wait_counter, rval = 8'00000000). -Adding EN signal on $procdff$408 ($dff) from module hyperram (D = $add$hyperram.v:273$49_Y, Q = \write_count). -Adding EN signal on $procdff$407 ($dff) from module hyperram (D = $add$hyperram.v:270$47_Y, Q = \read_count). - -6.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. -Removed 7 unused cells and 7 unused wires. -<suppressed ~10 debug messages> - -6.5. Rerunning OPT passes. (Removed registers in this run.) - -6.6. Executing OPT_EXPR pass (perform const folding). -Optimizing module hyperram. -<suppressed ~1 debug messages> - -6.7. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\hyperram'. -Removed a total of 0 cells. - -6.8. Executing OPT_DFF pass (perform DFF optimizations). - -6.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \hyperram.. - -6.10. Finished fast OPT passes. - -7. Executing CHECK pass (checking for obvious problems). -Checking module hyperram... -Found and reported 0 problems. - -8. Executing HIERARCHY pass (managing design hierarchy). - -8.1. Analyzing design hierarchy.. -Top module: \hyperram - -8.2. Analyzing design hierarchy.. -Top module: \hyperram -Removed 0 unused modules. -Module hyperram directly or indirectly contains formal properties -> setting "keep" attribute. - -9. Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs). - -10. Printing statistics. - -=== hyperram === - - Number of wires: 100 - Number of wire bits: 563 - Number of public wires: 34 - Number of public wire bits: 383 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 94 - $add 5 - $anyseq 4 - $cover 9 - $dff 19 - $eq 22 - $logic_and 1 - $logic_not 3 - $logic_or 1 - $mux 18 - $ne 4 - $pmux 3 - $reduce_and 1 - $reduce_bool 1 - $reduce_or 3 - -11. Executing SMT2 backend. - -11.1. Executing BMUXMAP pass. - -11.2. Executing DEMUXMAP pass. -Creating SMT-LIBv2 representation of module hyperram. - -End of script. Logfile hash: e86ecf84c9, CPU: user 0.03s system 0.01s, MEM: 11.30 MB peak -Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) -Time spent: 27% 3x opt_clean (0 sec), 14% 2x opt_expr (0 sec), ...
diff --git a/verilog/rtl/unit_test/cover/model/design_smt2.smt2 b/verilog/rtl/unit_test/cover/model/design_smt2.smt2 deleted file mode 100644 index 9312282..0000000 --- a/verilog/rtl/unit_test/cover/model/design_smt2.smt2 +++ /dev/null
@@ -1,269 +0,0 @@ -; SMT-LIBv2 description generated by Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os) -; yosys-smt2-module hyperram -(declare-sort |hyperram_s| 0) -(declare-fun |hyperram_is| (|hyperram_s|) Bool) -(declare-fun |hyperram#0| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:296$1_CHECK -; yosys-smt2-register $formal$hyperram.v:296$1_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:296$1_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#0| state)) #b1)) -(declare-fun |hyperram#1| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:296$1_EN -; yosys-smt2-register $formal$hyperram.v:296$1_EN 1 -(define-fun |hyperram_n $formal$hyperram.v:296$1_EN| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#1| state)) #b1)) -(declare-fun |hyperram#2| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:297$2_CHECK -; yosys-smt2-register $formal$hyperram.v:297$2_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:297$2_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#2| state)) #b1)) -(declare-fun |hyperram#3| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:298$3_CHECK -; yosys-smt2-register $formal$hyperram.v:298$3_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:298$3_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#3| state)) #b1)) -(declare-fun |hyperram#4| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:299$4_CHECK -; yosys-smt2-register $formal$hyperram.v:299$4_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:299$4_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#4| state)) #b1)) -(declare-fun |hyperram#5| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:300$5_CHECK -; yosys-smt2-register $formal$hyperram.v:300$5_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:300$5_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#5| state)) #b1)) -(declare-fun |hyperram#6| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:301$6_CHECK -; yosys-smt2-register $formal$hyperram.v:301$6_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:301$6_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#6| state)) #b1)) -(declare-fun |hyperram#7| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:302$7_CHECK -; yosys-smt2-register $formal$hyperram.v:302$7_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:302$7_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#7| state)) #b1)) -(declare-fun |hyperram#8| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:303$8_CHECK -; yosys-smt2-register $formal$hyperram.v:303$8_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:303$8_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#8| state)) #b1)) -(declare-fun |hyperram#9| (|hyperram_s|) (_ BitVec 1)) ; $formal$hyperram.v:304$9_CHECK -; yosys-smt2-register $formal$hyperram.v:304$9_CHECK 1 -(define-fun |hyperram_n $formal$hyperram.v:304$9_CHECK| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#9| state)) #b1)) -; yosys-smt2-input address 32 -; yosys-smt2-wire address 32 -(define-fun |hyperram_n address| ((state |hyperram_s|)) (_ BitVec 32) #b00010010001101000101011001111000) -(declare-fun |hyperram#10| (|hyperram_s|) (_ BitVec 1)) ; \ck -; yosys-smt2-output ck 1 -; yosys-smt2-register ck 1 -; yosys-smt2-wire ck 1 -(define-fun |hyperram_n ck| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#10| state)) #b1)) -(define-fun |hyperram#11| ((state |hyperram_s|)) Bool (not (or (= ((_ extract 0 0) (|hyperram#10| state)) #b1) false))) ; \ck_bar -; yosys-smt2-output ck_bar 1 -; yosys-smt2-wire ck_bar 1 -(define-fun |hyperram_n ck_bar| ((state |hyperram_s|)) Bool (|hyperram#11| state)) -(declare-fun |hyperram#12| (|hyperram_s|) Bool) ; \clk -; yosys-smt2-input clk 1 -; yosys-smt2-wire clk 1 -; yosys-smt2-clock clk posedge -(define-fun |hyperram_n clk| ((state |hyperram_s|)) Bool (|hyperram#12| state)) -(declare-fun |hyperram#13| (|hyperram_s|) (_ BitVec 48)) ; \command_address -; yosys-smt2-register command_address 48 -; yosys-smt2-wire command_address 48 -(define-fun |hyperram_n command_address| ((state |hyperram_s|)) (_ BitVec 48) (|hyperram#13| state)) -(declare-fun |hyperram#14| (|hyperram_s|) (_ BitVec 7)) ; \control_state -; yosys-smt2-register control_state 7 -; yosys-smt2-wire control_state 7 -(define-fun |hyperram_n control_state| ((state |hyperram_s|)) (_ BitVec 7) (|hyperram#14| state)) -(define-fun |hyperram#15| ((state |hyperram_s|)) Bool (not (or (= ((_ extract 0 0) (|hyperram#14| state)) #b1) (= ((_ extract 1 1) (|hyperram#14| state)) #b1) (= ((_ extract 2 2) (|hyperram#14| state)) #b1) (= ((_ extract 3 3) (|hyperram#14| state)) #b1) (= ((_ extract 4 4) (|hyperram#14| state)) #b1) (= ((_ extract 5 5) (|hyperram#14| state)) #b1) (= ((_ extract 6 6) (|hyperram#14| state)) #b1)))) ; $0$formal$hyperram.v:296$1_CHECK[0:0]$51 -(define-fun |hyperram#16| ((state |hyperram_s|)) (_ BitVec 1) (ite (|hyperram#15| state) #b1 #b0)) ; \transaction_end -; yosys-smt2-output cs_bar 1 -; yosys-smt2-wire cs_bar 1 -(define-fun |hyperram_n cs_bar| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#16| state)) #b1)) -; yosys-smt2-output data_in 32 -; yosys-smt2-wire data_in 32 -(define-fun |hyperram_n data_in| ((state |hyperram_s|)) (_ BitVec 32) #b10101010101010101011101110111011) -; yosys-smt2-wire data_in_register 32 -(define-fun |hyperram_n data_in_register| ((state |hyperram_s|)) (_ BitVec 32) #b10101010101010101011101110111011) -; yosys-smt2-input data_out 32 -; yosys-smt2-wire data_out 32 -(define-fun |hyperram_n data_out| ((state |hyperram_s|)) (_ BitVec 32) #b11001100110011001101110111011101) -(declare-fun |hyperram#17| (|hyperram_s|) (_ BitVec 31)) ; \data_out_register [30:0] -; yosys-smt2-register data_out_register 32 -; yosys-smt2-wire data_out_register 32 -(define-fun |hyperram_n data_out_register| ((state |hyperram_s|)) (_ BitVec 32) (concat ((_ extract 30 30) (|hyperram#17| state)) (|hyperram#17| state))) -(declare-fun |hyperram#18| (|hyperram_s|) (_ BitVec 8)) ; \done_counter -; yosys-smt2-register done_counter 8 -; yosys-smt2-wire done_counter 8 -(define-fun |hyperram_n done_counter| ((state |hyperram_s|)) (_ BitVec 8) (|hyperram#18| state)) -(declare-fun |hyperram#19| (|hyperram_s|) (_ BitVec 6)) ; \done_latency -; yosys-smt2-input done_latency 6 -; yosys-smt2-wire done_latency 6 -(define-fun |hyperram_n done_latency| ((state |hyperram_s|)) (_ BitVec 6) (|hyperram#19| state)) -; yosys-smt2-anyseq hyperram#20 8 $auto$setundef.cc:501:execute$433 -(declare-fun |hyperram#20| (|hyperram_s|) (_ BitVec 8)) ; $auto$rtlil.cc:3133:Anyseq$434 -; yosys-smt2-anyseq hyperram#21 8 $auto$setundef.cc:501:execute$431 -(declare-fun |hyperram#21| (|hyperram_s|) (_ BitVec 8)) ; $auto$rtlil.cc:3133:Anyseq$432 -(define-fun |hyperram#22| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001011)) ; $eq$hyperram.v:272$48_Y -(define-fun |hyperram#23| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001010)) ; $procmux$217_CMP -(define-fun |hyperram#24| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001001)) ; $procmux$218_CMP -(define-fun |hyperram#25| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001000)) ; $0$formal$hyperram.v:299$4_CHECK[0:0]$57 -(define-fun |hyperram#26| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000110)) ; $0$formal$hyperram.v:297$2_CHECK[0:0]$53 -(define-fun |hyperram#27| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000101)) ; $procmux$222_CMP -(define-fun |hyperram#28| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000100)) ; $procmux$223_CMP -(define-fun |hyperram#29| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000011)) ; $procmux$224_CMP -(define-fun |hyperram#30| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000010)) ; $procmux$225_CMP -(define-fun |hyperram#31| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000001)) ; $procmux$226_CMP -(define-fun |hyperram#32| ((state |hyperram_s|)) (_ BitVec 8) (ite (|hyperram#31| state) ((_ extract 47 40) (|hyperram#13| state)) (ite (|hyperram#30| state) ((_ extract 39 32) (|hyperram#13| state)) (ite (|hyperram#29| state) ((_ extract 31 24) (|hyperram#13| state)) (ite (|hyperram#28| state) ((_ extract 23 16) (|hyperram#13| state)) (ite (|hyperram#27| state) ((_ extract 15 8) (|hyperram#13| state)) (ite (|hyperram#26| state) ((_ extract 7 0) (|hyperram#13| state)) (ite (|hyperram#25| state) ((_ extract 7 0) (|hyperram#17| state)) (ite (|hyperram#24| state) ((_ extract 15 8) (|hyperram#17| state)) (ite (|hyperram#23| state) ((_ extract 23 16) (|hyperram#17| state)) (ite (|hyperram#22| state) (concat ((_ extract 30 30) (|hyperram#17| state)) ((_ extract 30 24) (|hyperram#17| state))) (|hyperram#21| state)))))))))))) ; \dq_out -(define-fun |hyperram#33| ((state |hyperram_s|)) Bool (or (|hyperram#22| state) (|hyperram#26| state) (|hyperram#25| state) (|hyperram#23| state) (|hyperram#24| state) (|hyperram#27| state) (|hyperram#28| state) (|hyperram#29| state) (|hyperram#30| state) (|hyperram#31| state))) ; $auto$opt_reduce.cc:134:opt_pmux$422 -(define-fun |hyperram#34| ((state |hyperram_s|)) (_ BitVec 1) (ite (|hyperram#33| state) #b1 #b0)) ; \dq_oe -(define-fun |hyperram#35| ((state |hyperram_s|)) (_ BitVec 8) (ite (= ((_ extract 0 0) (|hyperram#34| state)) #b1) (|hyperram#32| state) (|hyperram#20| state))) ; \dq -; yosys-smt2-input dq 8 -; yosys-smt2-output dq 8 -; yosys-smt2-wire dq 8 -(define-fun |hyperram_n dq| ((state |hyperram_s|)) (_ BitVec 8) (|hyperram#35| state)) -; yosys-smt2-wire dq_oe 1 -(define-fun |hyperram_n dq_oe| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#34| state)) #b1)) -; yosys-smt2-wire dq_out 8 -(define-fun |hyperram_n dq_out| ((state |hyperram_s|)) (_ BitVec 8) (|hyperram#32| state)) -(declare-fun |hyperram#36| (|hyperram_s|) Bool) ; \write_enable -(define-fun |hyperram#37| ((state |hyperram_s|)) Bool (not (or (|hyperram#36| state) false))) ; \next_command_address [47] -; yosys-smt2-wire next_command_address 48 -(define-fun |hyperram_n next_command_address| ((state |hyperram_s|)) (_ BitVec 48) (concat (ite (|hyperram#37| state) #b1 #b0) #b01000000000011010001010110011110000000000000000)) -(define-fun |hyperram#38| ((state |hyperram_s|)) Bool (= (|hyperram#18| state) #b00000100)) ; $eq$hyperram.v:227$41_Y -(define-fun |hyperram#39| ((state |hyperram_s|)) (_ BitVec 7) (ite (|hyperram#38| state) #b0000000 #b0000000)) ; $6\next_control_state[6:0] -(define-fun |hyperram#40| ((state |hyperram_s|)) (_ BitVec 7) (bvadd (|hyperram#14| state) #b0000001)) ; $add$hyperram.v:109$23_Y -; yosys-smt2-anyseq hyperram#41 1 $auto$setundef.cc:501:execute$435 -(declare-fun |hyperram#41| (|hyperram_s|) (_ BitVec 1)) ; $auto$rtlil.cc:3133:Anyseq$436 -; yosys-smt2-anyseq hyperram#42 1 $auto$setundef.cc:501:execute$429 -(declare-fun |hyperram#42| (|hyperram_s|) (_ BitVec 1)) ; $auto$rtlil.cc:3133:Anyseq$430 -(declare-fun |hyperram#43| (|hyperram_s|) (_ BitVec 4)) ; \write_mask_register -(define-fun |hyperram#44| ((state |hyperram_s|)) (_ BitVec 1) (ite (|hyperram#25| state) ((_ extract 0 0) (|hyperram#43| state)) (ite (|hyperram#24| state) ((_ extract 1 1) (|hyperram#43| state)) (ite (|hyperram#23| state) ((_ extract 2 2) (|hyperram#43| state)) (ite (|hyperram#22| state) ((_ extract 3 3) (|hyperram#43| state)) (|hyperram#42| state)))))) ; \rwds_out -(define-fun |hyperram#45| ((state |hyperram_s|)) Bool (or (|hyperram#22| state) (|hyperram#25| state) (|hyperram#23| state) (|hyperram#24| state))) ; $auto$opt_reduce.cc:134:opt_pmux$420 -(define-fun |hyperram#46| ((state |hyperram_s|)) (_ BitVec 1) (ite (|hyperram#45| state) #b1 #b0)) ; \rwds_oe -(define-fun |hyperram#47| ((state |hyperram_s|)) (_ BitVec 1) (ite (= ((_ extract 0 0) (|hyperram#46| state)) #b1) (|hyperram#44| state) (|hyperram#41| state))) ; \rwds -(declare-fun |hyperram#48| (|hyperram_s|) Bool) ; \timed_read -(define-fun |hyperram#49| ((state |hyperram_s|)) Bool (or (= ((_ extract 0 0) (|hyperram#47| state)) #b1) false (|hyperram#48| state) false)) ; $logic_or$hyperram.v:201$35_Y -(define-fun |hyperram#50| ((state |hyperram_s|)) (_ BitVec 7) (ite (|hyperram#49| state) (|hyperram#40| state) #b0000000)) ; $5\next_control_state[6:0] -(define-fun |hyperram#51| ((state |hyperram_s|)) (_ BitVec 3) (ite (= ((_ extract 47 47) (|hyperram#13| state)) #b1) #b100 #b000)) ; $4\next_control_state[6:0] -(declare-fun |hyperram#52| (|hyperram_s|) (_ BitVec 8)) ; \wait_counter -(define-fun |hyperram#53| ((state |hyperram_s|)) Bool (= (|hyperram#52| state) #b00000100)) ; $eq$hyperram.v:154$31_Y -(define-fun |hyperram#54| ((state |hyperram_s|)) (_ BitVec 7) (ite (|hyperram#53| state) (concat #b0001 (|hyperram#51| state)) #b0000000)) ; $3\next_control_state[6:0] -(declare-fun |hyperram#55| (|hyperram_s|) (_ BitVec 1)) ; \transaction_begin -(define-fun |hyperram#56| ((state |hyperram_s|)) (_ BitVec 7) (ite (= ((_ extract 0 0) (|hyperram#55| state)) #b1) (|hyperram#40| state) #b0000000)) ; $2\next_control_state[6:0] -(define-fun |hyperram#57| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0010000)) ; $0$formal$hyperram.v:301$6_CHECK[0:0]$61 -(define-fun |hyperram#58| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001111)) ; $eq$hyperram.v:269$46_Y -(define-fun |hyperram#59| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001110)) ; $procmux$213_CMP -(define-fun |hyperram#60| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001101)) ; $procmux$214_CMP -(define-fun |hyperram#61| ((state |hyperram_s|)) Bool (or (|hyperram#58| state) (|hyperram#26| state) (|hyperram#25| state) (|hyperram#59| state) (|hyperram#60| state) (|hyperram#23| state) (|hyperram#24| state) (|hyperram#27| state) (|hyperram#28| state) (|hyperram#29| state) (|hyperram#30| state) (|hyperram#31| state))) ; $auto$opt_reduce.cc:134:opt_pmux$418 -(define-fun |hyperram#62| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0001100)) ; $0$formal$hyperram.v:300$5_CHECK[0:0]$59 -(define-fun |hyperram#63| ((state |hyperram_s|)) Bool (= (|hyperram#14| state) #b0000111)) ; $0$formal$hyperram.v:298$3_CHECK[0:0]$55 -(define-fun |hyperram#64| ((state |hyperram_s|)) (_ BitVec 7) (ite (|hyperram#15| state) (|hyperram#56| state) (ite (|hyperram#63| state) (|hyperram#54| state) (ite (|hyperram#22| state) #b0010000 (ite (|hyperram#62| state) (|hyperram#50| state) (ite (|hyperram#61| state) (|hyperram#40| state) (ite (|hyperram#57| state) (|hyperram#39| state) #b0000000))))))) ; \next_control_state -; yosys-smt2-wire next_control_state 7 -(define-fun |hyperram_n next_control_state| ((state |hyperram_s|)) (_ BitVec 7) (|hyperram#64| state)) -; yosys-smt2-wire next_data_out_register 32 -(define-fun |hyperram_n next_data_out_register| ((state |hyperram_s|)) (_ BitVec 32) #b11001100110011001101110111011101) -(declare-fun |hyperram#65| (|hyperram_s|) (_ BitVec 4)) ; \write_mask -; yosys-smt2-wire next_write_mask_register 4 -(define-fun |hyperram_n next_write_mask_register| ((state |hyperram_s|)) (_ BitVec 4) (|hyperram#65| state)) -(declare-fun |hyperram#66| (|hyperram_s|) (_ BitVec 6)) ; \read_count -; yosys-smt2-register read_count 6 -; yosys-smt2-wire read_count 6 -(define-fun |hyperram_n read_count| ((state |hyperram_s|)) (_ BitVec 6) (|hyperram#66| state)) -; yosys-smt2-input rst 1 -; yosys-smt2-wire rst 1 -(define-fun |hyperram_n rst| ((state |hyperram_s|)) Bool false) -; yosys-smt2-input rwds 1 -; yosys-smt2-output rwds 1 -; yosys-smt2-wire rwds 1 -(define-fun |hyperram_n rwds| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#47| state)) #b1)) -; yosys-smt2-wire rwds_oe 1 -(define-fun |hyperram_n rwds_oe| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#46| state)) #b1)) -; yosys-smt2-wire rwds_out 1 -(define-fun |hyperram_n rwds_out| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#44| state)) #b1)) -; yosys-smt2-input timed_read 1 -; yosys-smt2-wire timed_read 1 -(define-fun |hyperram_n timed_read| ((state |hyperram_s|)) Bool (|hyperram#48| state)) -; yosys-smt2-input transaction_begin 1 -; yosys-smt2-wire transaction_begin 1 -(define-fun |hyperram_n transaction_begin| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#55| state)) #b1)) -; yosys-smt2-output transaction_end 1 -; yosys-smt2-wire transaction_end 1 -(define-fun |hyperram_n transaction_end| ((state |hyperram_s|)) Bool (= ((_ extract 0 0) (|hyperram#16| state)) #b1)) -; yosys-smt2-register wait_counter 8 -; yosys-smt2-wire wait_counter 8 -(define-fun |hyperram_n wait_counter| ((state |hyperram_s|)) (_ BitVec 8) (|hyperram#52| state)) -(declare-fun |hyperram#67| (|hyperram_s|) (_ BitVec 6)) ; \wait_latency -; yosys-smt2-input wait_latency 6 -; yosys-smt2-wire wait_latency 6 -(define-fun |hyperram_n wait_latency| ((state |hyperram_s|)) (_ BitVec 6) (|hyperram#67| state)) -(declare-fun |hyperram#68| (|hyperram_s|) (_ BitVec 6)) ; \write_count -; yosys-smt2-register write_count 6 -; yosys-smt2-wire write_count 6 -(define-fun |hyperram_n write_count| ((state |hyperram_s|)) (_ BitVec 6) (|hyperram#68| state)) -; yosys-smt2-input write_enable 1 -; yosys-smt2-wire write_enable 1 -(define-fun |hyperram_n write_enable| ((state |hyperram_s|)) Bool (|hyperram#36| state)) -; yosys-smt2-input write_mask 4 -; yosys-smt2-wire write_mask 4 -(define-fun |hyperram_n write_mask| ((state |hyperram_s|)) (_ BitVec 4) (|hyperram#65| state)) -; yosys-smt2-register write_mask_register 4 -; yosys-smt2-wire write_mask_register 4 -(define-fun |hyperram_n write_mask_register| ((state |hyperram_s|)) (_ BitVec 4) (|hyperram#43| state)) -; yosys-smt2-cover 0 cover_ca -(define-fun |hyperram_c 0| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#2| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_ca -; yosys-smt2-cover 1 cover_done -(define-fun |hyperram_c 1| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#6| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_done -; yosys-smt2-cover 2 cover_idle -(define-fun |hyperram_c 2| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#0| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_idle -; yosys-smt2-cover 3 cover_read -(define-fun |hyperram_c 3| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#5| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_read -; yosys-smt2-cover 4 cover_read_2 -(define-fun |hyperram_c 4| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#8| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_read_2 -; yosys-smt2-cover 5 cover_wait -(define-fun |hyperram_c 5| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#3| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_wait -; yosys-smt2-cover 6 cover_write -(define-fun |hyperram_c 6| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#4| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_write -; yosys-smt2-cover 7 cover_write_2 -(define-fun |hyperram_c 7| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#7| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_write_2 -; yosys-smt2-cover 8 cover_write_read -(define-fun |hyperram_c 8| ((state |hyperram_s|)) Bool (and (= ((_ extract 0 0) (|hyperram#9| state)) #b1) (= ((_ extract 0 0) (|hyperram#1| state)) #b1))) ; cover_write_read -(define-fun |hyperram#69| ((state |hyperram_s|)) (_ BitVec 6) (bvadd (|hyperram#68| state) #b000001)) ; $add$hyperram.v:273$49_Y -(define-fun |hyperram#70| ((state |hyperram_s|)) (_ BitVec 6) (ite (|hyperram#22| state) (|hyperram#69| state) (|hyperram#68| state))) ; $auto$rtlil.cc:2459:Mux$470 -(define-fun |hyperram#71| ((state |hyperram_s|)) (_ BitVec 6) (bvadd (|hyperram#66| state) #b000001)) ; $add$hyperram.v:270$47_Y -(define-fun |hyperram#72| ((state |hyperram_s|)) (_ BitVec 6) (ite (|hyperram#58| state) (|hyperram#71| state) (|hyperram#66| state))) ; $auto$rtlil.cc:2459:Mux$472 -(define-fun |hyperram#73| ((state |hyperram_s|)) (_ BitVec 8) (bvadd (|hyperram#52| state) #b00000001)) ; $add$hyperram.v:152$30_Y -(define-fun |hyperram#74| ((state |hyperram_s|)) (_ BitVec 8) (ite (|hyperram#53| state) #b00000000 (|hyperram#73| state))) ; $auto$rtlil.cc:2459:Mux$466 -(define-fun |hyperram#75| ((state |hyperram_s|)) (_ BitVec 8) (ite (|hyperram#63| state) (|hyperram#74| state) (|hyperram#52| state))) ; $auto$rtlil.cc:2459:Mux$468 -(define-fun |hyperram#76| ((state |hyperram_s|)) (_ BitVec 8) (bvadd (|hyperram#18| state) #b00000001)) ; $add$hyperram.v:225$40_Y -(define-fun |hyperram#77| ((state |hyperram_s|)) (_ BitVec 8) (ite (|hyperram#38| state) #b00000000 (|hyperram#76| state))) ; $auto$rtlil.cc:2459:Mux$462 -(define-fun |hyperram#78| ((state |hyperram_s|)) (_ BitVec 8) (ite (|hyperram#57| state) (|hyperram#77| state) (|hyperram#18| state))) ; $auto$rtlil.cc:2459:Mux$464 -(define-fun |hyperram#79| ((state |hyperram_s|)) Bool (or (|hyperram#15| state) (|hyperram#63| state) (|hyperram#62| state) (|hyperram#57| state) (|hyperram#61| state) (|hyperram#22| state))) ; $auto$opt_dff.cc:194:make_patterns_logic$439 -(define-fun |hyperram#80| ((state |hyperram_s|)) Bool (distinct (concat (|hyperram#55| state) (ite (|hyperram#15| state) #b1 #b0)) #b01)) ; $auto$opt_dff.cc:194:make_patterns_logic$441 -(define-fun |hyperram#81| ((state |hyperram_s|)) Bool (distinct (concat (ite (|hyperram#53| state) #b1 #b0) (ite (|hyperram#63| state) #b1 #b0)) #b01)) ; $auto$opt_dff.cc:194:make_patterns_logic$443 -(define-fun |hyperram#82| ((state |hyperram_s|)) Bool (distinct (concat (ite (|hyperram#49| state) #b1 #b0) (ite (|hyperram#62| state) #b1 #b0)) #b01)) ; $auto$opt_dff.cc:194:make_patterns_logic$445 -(define-fun |hyperram#83| ((state |hyperram_s|)) Bool (distinct (concat (ite (|hyperram#38| state) #b1 #b0) (ite (|hyperram#57| state) #b1 #b0)) #b01)) ; $auto$opt_dff.cc:194:make_patterns_logic$447 -(define-fun |hyperram#84| ((state |hyperram_s|)) Bool (and (|hyperram#79| state) (|hyperram#80| state) (|hyperram#81| state) (|hyperram#82| state) (|hyperram#83| state))) ; $auto$opt_dff.cc:219:make_patterns_logic$449 -(define-fun |hyperram#85| ((state |hyperram_s|)) (_ BitVec 7) (ite (|hyperram#84| state) (|hyperram#64| state) (|hyperram#14| state))) ; $auto$rtlil.cc:2459:Mux$460 -(define-fun |hyperram#86| ((state |hyperram_s|)) (_ BitVec 1) (ite (|hyperram#15| state) #b0 (ite (|hyperram#11| state) #b1 #b0))) ; $auto$rtlil.cc:2459:Mux$458 -(define-fun |hyperram#87| ((state |hyperram_s|)) Bool (= (|hyperram#66| state) #b000001)) ; $eq$hyperram.v:304$77_Y -(define-fun |hyperram#88| ((state |hyperram_s|)) Bool (= (|hyperram#68| state) #b000001)) ; $eq$hyperram.v:304$78_Y -(define-fun |hyperram#89| ((state |hyperram_s|)) Bool (and (or (|hyperram#87| state) false) (or (|hyperram#88| state) false))) ; $0$formal$hyperram.v:304$9_CHECK[0:0]$67 -(define-fun |hyperram#90| ((state |hyperram_s|)) Bool (= (|hyperram#66| state) #b000010)) ; $0$formal$hyperram.v:303$8_CHECK[0:0]$65 -(define-fun |hyperram#91| ((state |hyperram_s|)) Bool (= (|hyperram#68| state) #b000010)) ; $0$formal$hyperram.v:302$7_CHECK[0:0]$63 -(define-fun |hyperram_a| ((state |hyperram_s|)) Bool true) -(define-fun |hyperram_u| ((state |hyperram_s|)) Bool true) -(define-fun |hyperram_i| ((state |hyperram_s|)) Bool (and - (= (= ((_ extract 0 0) (|hyperram#1| state)) #b1) false) ; $formal$hyperram.v:296$1_EN - (= (|hyperram#14| state) #b0000000) ; control_state - (= (|hyperram#18| state) #b00000000) ; done_counter - (= (|hyperram#66| state) #b000000) ; read_count - (= (|hyperram#52| state) #b00000000) ; wait_counter - (= (|hyperram#68| state) #b000000) ; write_count -)) -(define-fun |hyperram_h| ((state |hyperram_s|)) Bool true) -(define-fun |hyperram_t| ((state |hyperram_s|) (next_state |hyperram_s|)) Bool (and - (= (|hyperram#70| state) (|hyperram#68| next_state)) ; $auto$ff.cc:262:slice$455 \write_count - (= (|hyperram#72| state) (|hyperram#66| next_state)) ; $auto$ff.cc:262:slice$456 \read_count - (= (|hyperram#75| state) (|hyperram#52| next_state)) ; $auto$ff.cc:262:slice$454 \wait_counter - (= (|hyperram#65| state) (|hyperram#43| next_state)) ; $procdff$410 \write_mask_register - (= (|hyperram#78| state) (|hyperram#18| next_state)) ; $auto$ff.cc:262:slice$452 \done_counter - (= #b1001100110011001101110111011101 (|hyperram#17| next_state)) ; $procdff$411 \data_out_register [30:0] - (= (|hyperram#85| state) (|hyperram#14| next_state)) ; $auto$ff.cc:262:slice$438 \control_state - (= (concat (ite (|hyperram#37| state) #b1 #b0) #b01000000000011010001010110011110000000000000000) (|hyperram#13| next_state)) ; $procdff$409 \command_address - (= (|hyperram#86| state) (|hyperram#10| next_state)) ; $auto$ff.cc:262:slice$437 \ck - (= (ite (|hyperram#89| state) #b1 #b0) (|hyperram#9| next_state)) ; $procdff$405 $formal$hyperram.v:304$9_CHECK - (= (ite (|hyperram#90| state) #b1 #b0) (|hyperram#8| next_state)) ; $procdff$403 $formal$hyperram.v:303$8_CHECK - (= (ite (|hyperram#91| state) #b1 #b0) (|hyperram#7| next_state)) ; $procdff$401 $formal$hyperram.v:302$7_CHECK - (= (ite (|hyperram#57| state) #b1 #b0) (|hyperram#6| next_state)) ; $procdff$399 $formal$hyperram.v:301$6_CHECK - (= (ite (|hyperram#62| state) #b1 #b0) (|hyperram#5| next_state)) ; $procdff$397 $formal$hyperram.v:300$5_CHECK - (= (ite (|hyperram#25| state) #b1 #b0) (|hyperram#4| next_state)) ; $procdff$395 $formal$hyperram.v:299$4_CHECK - (= (ite (|hyperram#63| state) #b1 #b0) (|hyperram#3| next_state)) ; $procdff$393 $formal$hyperram.v:298$3_CHECK - (= (ite (|hyperram#26| state) #b1 #b0) (|hyperram#2| next_state)) ; $procdff$391 $formal$hyperram.v:297$2_CHECK - (= #b1 (|hyperram#1| next_state)) ; $procdff$390 $formal$hyperram.v:296$1_EN - (= (ite (|hyperram#15| state) #b1 #b0) (|hyperram#0| next_state)) ; $procdff$389 $formal$hyperram.v:296$1_CHECK -)) ; end of module hyperram -; yosys-smt2-topmod hyperram -; end of yosys output
diff --git a/verilog/rtl/unit_test/cover/model/design_smt2.ys b/verilog/rtl/unit_test/cover/model/design_smt2.ys deleted file mode 100644 index d37d6a8..0000000 --- a/verilog/rtl/unit_test/cover/model/design_smt2.ys +++ /dev/null
@@ -1,14 +0,0 @@ -# running in cover/model/ -read_ilang design.il -memory_nordff -async2sync -chformal -assume -early -chformal -live -fair -remove -opt_clean -setundef -anyseq -opt -keepdc -fast -check -hierarchy -simcheck -dffunmap -stat -write_smt2 -wires design_smt2.smt2
diff --git a/verilog/rtl/unit_test/cover/src/hyperram.v b/verilog/rtl/unit_test/cover/src/hyperram.v deleted file mode 100644 index ac4e915..0000000 --- a/verilog/rtl/unit_test/cover/src/hyperram.v +++ /dev/null
@@ -1,308 +0,0 @@ -module hyperram( - input clk, - input rst, - - // CPU Interface - input [31:0] address, - input [31:0] data_out, - output [31:0] data_in, - input write_enable, - input [3:0] write_mask, - input transaction_begin, - output transaction_end, - - // Hyperram Interface - inout [7:0] dq, - output ck, - output ck_bar, - output cs_bar, - inout rwds, - - // Config - input timed_read, - input [5:0] wait_latency, - input [5:0] done_latency, -); - localparam WAIT_LATENCY = 4; - localparam DONE_LATENCY = 4; - - reg ck_gate; - reg ck; - - always_ff @(posedge clk) begin - if(!ck_gate) begin - ck <= 0; - end - else begin - ck <= !ck; - end - end - - assign ck_bar = !ck; - - - reg cs_bar; - - reg [7:0] dq_out; - reg dq_oe; - reg rwds_out; - reg rwds_oe; - - assign dq = !dq_oe ? 'hz : dq_out; - assign rwds = !rwds_oe ? 'hz : rwds_out; - - wire write_enable_register; - assign write_enable_register = !command_address[47]; - - assign data_in = data_in_register; - - reg [7:0] wait_counter; - reg [7:0] next_wait_counter; - - reg [7:0] done_counter; - reg [7:0] next_done_counter; - - // FSM - reg [6:0] control_state; - reg [6:0] next_control_state; - - reg [31:0] next_data_in; - reg [31:0] data_in_register; - - always_ff @(posedge clk) begin - if(rst) begin - control_state <= 0; - data_in_register <= 0; - wait_counter <= 0; - done_counter <= 0; - end - else begin - control_state <= next_control_state; - data_in_register <= next_data_in; - wait_counter <= next_wait_counter; - done_counter <= next_done_counter; - end - end - - always_comb begin - next_control_state = control_state; - cs_bar = 0; - ck_gate = 1; - dq_oe = 0; - rwds_oe = 0; - next_data_in = data_in_register; - next_wait_counter = wait_counter; - next_done_counter = done_counter; - dq_out = 'hzz; - rwds_out = 'hz; - transaction_end = 0; - - - case(control_state) - // IDLE state - 'h0 : begin - cs_bar = 1; - ck_gate = 0; - transaction_end = 1; - - if(transaction_begin) begin - next_control_state = control_state + 1; - end - end - - // CA0 state - 'h1 : begin - next_control_state = control_state + 1; - dq_out = command_address[47:40]; - dq_oe = 1; - end - // CA1 state - 'h2 : begin - next_control_state = control_state + 1; - dq_out = command_address[39:32]; - dq_oe = 1; - end - // CA2 state - 'h3 : begin - next_control_state = control_state + 1; - dq_out = command_address[31:24]; - dq_oe = 1; - end - // CA3 state - 'h4 : begin - next_control_state = control_state + 1; - dq_out = command_address[23:16]; - dq_oe = 1; - end - // CA4 state - 'h5 : begin - next_control_state = control_state + 1; - dq_out = command_address[15:8]; - dq_oe = 1; - end - // CA5 state - 'h6 : begin - next_control_state = control_state + 1; - dq_out = command_address[7:0]; - dq_oe = 1; - end - - // WAIT state - 'h7 : begin - next_wait_counter = wait_counter + 1; - - if(wait_counter == WAIT_LATENCY) begin - next_wait_counter = 0; - if(write_enable_register) begin - next_control_state = 'h8; - end - else begin - next_control_state = 'hc; - end - end - end - - // WRITE0 state - 'h8 : begin - next_control_state = control_state + 1; - rwds_out = write_mask_register[0]; - rwds_oe = 1; - dq_out = data_out_register[7:0]; - dq_oe = 1; - end - // WRITE1 state - 'h9 : begin - next_control_state = control_state + 1; - rwds_out = write_mask_register[1]; - rwds_oe = 1; - dq_out = data_out_register[15:8]; - dq_oe = 1; - end - // WRITE2 state - 'ha : begin - next_control_state = control_state + 1; - rwds_out = write_mask_register[2]; - rwds_oe = 1; - dq_out = data_out_register[23:16]; - dq_oe = 1; - end - // WRITE3 state - 'hb : begin - next_control_state = 'h10; - rwds_out = write_mask_register[3]; - rwds_oe = 1; - dq_out = data_out_register[31:24]; - dq_oe = 1; - end - - - // READ0 state - wait for rwds strobe - 'hc : begin - if(rwds || timed_read) begin - next_data_in[7:0] = dq; - next_control_state = control_state + 1; - end - end - // READ1 state - 'hd : begin - next_data_in[15:8] = dq; - next_control_state = control_state + 1; - end - // READ2 state - 'he : begin - next_data_in[23:16] = dq; - next_control_state = control_state + 1; - end - // READ3 state - 'hf : begin - next_data_in[31:24] = dq; - next_control_state = control_state + 1; - end - - - // DONE state - 'h10 : begin - next_done_counter = done_counter + 1; - - if(done_counter == DONE_LATENCY) begin - next_control_state = 0; - next_done_counter = 0; - end - end - endcase - end - - - reg [47:0] command_address; - reg [47:0] next_command_address; - - reg [3:0] write_mask_register; - reg [3:0] next_write_mask_register; - - reg [31:0] data_out_register; - reg [31:0] next_data_out_register; - - always_ff @(posedge transaction_begin) begin - command_address <= next_command_address; - write_mask_register <= next_write_mask_register; - data_out_register <= next_data_out_register; - end - - always_comb begin - next_command_address = { - !write_enable, 1'h0, 1'h1, 9'h000, - address[22:9], address[8:3], 13'h0000, address[2:0] - }; - - next_write_mask_register = write_mask; - next_data_out_register = data_out; - end - - - - - `ifdef FORMAL - reg [5:0] read_count; - reg [5:0] write_count; - - always_ff @(posedge clk) begin - if(control_state == 'h0f) begin - read_count <= read_count + 1; - end - if(control_state == 'h0b) begin - write_count <= write_count + 1; - end - end - - initial begin - control_state = 'h0; - read_count = 0; - write_count = 0; - rst = 1; - address = 'h12345678; - - wait_counter = 0; - done_counter = 0; - - data_in = 'haaaabbbb; - data_out = 'hccccdddd; - - #10; - - rst = 0; - end - - always @(posedge clk) begin - cover_idle: cover (control_state == 0); - cover_ca: cover (control_state == 6); - cover_wait: cover (control_state == 7); - cover_write: cover (control_state == 8); - cover_read: cover (control_state == 'hc); - cover_done: cover (control_state == 'h10); - cover_write_2: cover (write_count == 'h2); - cover_read_2: cover (read_count == 'h2); - cover_write_read: cover (read_count == 1 && write_count == 1); - end - - `endif -endmodule
diff --git a/verilog/rtl/unit_test/cover/status b/verilog/rtl/unit_test/cover/status deleted file mode 100644 index 57a85a0..0000000 --- a/verilog/rtl/unit_test/cover/status +++ /dev/null
@@ -1 +0,0 @@ -PASS 0 5