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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-032 / f0f7f38767e21e27ba85908195f2283673ac5482 / . / verilog / rtl / unit_test / cover / model / design.log
blob: d902d1f30095d9e62e277898efe171db111c3855 [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os)
-- Executing script file `../model/design.ys' --
1. Executing Verilog-2005 frontend: hyperram.v
Parsing formal SystemVerilog input from `hyperram.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:51)
Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:52)
Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:96)
Warning: Yosys has only limited support for tri-state logic at the moment. (hyperram.v:97)
Storing AST representation for module `$abstract\hyperram'.
Successfully finished Verilog frontend.
2. Executing PREP pass.
2.1. Executing HIERARCHY pass (managing design hierarchy).
2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\hyperram'.
Generating RTLIL representation for module `\hyperram'.
Warning: wire '\transaction_end' is assigned in a block at hyperram.v:98.3-98.22.
Warning: wire '\transaction_end' is assigned in a block at hyperram.v:106.5-106.24.
Warning: wire '\rst' is assigned in a block at hyperram.v:281.4-281.11.
Warning: wire '\address' is assigned in a block at hyperram.v:282.4-282.24.
Warning: wire '\data_in' is assigned in a block at hyperram.v:287.4-287.24.
Warning: wire '\data_out' is assigned in a block at hyperram.v:288.4-288.25.
Warning: wire '\rst' is assigned in a block at hyperram.v:292.4-292.11.
2.2.1. Analyzing design hierarchy..
Top module: \hyperram
2.2.2. Analyzing design hierarchy..
Top module: \hyperram
Removing unused module `$abstract\hyperram'.
Removed 1 unused modules.
Module hyperram directly or indirectly contains formal properties -> setting "keep" attribute.
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 6 switch rules as full_case in process $proc$hyperram.v:0$22 in module hyperram.
Marked 1 switch rules as full_case in process $proc$hyperram.v:72$21 in module hyperram.
Marked 1 switch rules as full_case in process $proc$hyperram.v:32$10 in module hyperram.
Removed a total of 0 dead cases.
2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 5 redundant assignments.
Promoted 53 assignments to connections.
2.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\hyperram.$proc$hyperram.v:0$97'.
Set init value: $formal$hyperram.v:304$9_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$95'.
Set init value: $formal$hyperram.v:303$8_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$93'.
Set init value: $formal$hyperram.v:302$7_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$91'.
Set init value: $formal$hyperram.v:301$6_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$89'.
Set init value: $formal$hyperram.v:300$5_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$87'.
Set init value: $formal$hyperram.v:299$4_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$85'.
Set init value: $formal$hyperram.v:298$3_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$83'.
Set init value: $formal$hyperram.v:297$2_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$81'.
Set init value: $formal$hyperram.v:296$1_EN = 1'0
Found init rule in `\hyperram.$proc$hyperram.v:0$80'.
Set init value: \wait_counter = 8'00000000
Set init value: \done_counter = 8'00000000
Set init value: \control_state = 7'0000000
Set init value: \read_count = 6'000000
Set init value: \write_count = 6'000000
2.3.5. Executing PROC_ARST pass (detect async resets in processes).
2.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\hyperram.$proc$hyperram.v:0$97'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$95'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$93'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$91'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$89'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$87'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$85'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$83'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$81'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$80'.
Creating decoders for process `\hyperram.$proc$hyperram.v:295$50'.
Creating decoders for process `\hyperram.$proc$hyperram.v:268$45'.
1/2: $0\write_count[5:0]
2/2: $0\read_count[5:0]
Creating decoders for process `\hyperram.$proc$hyperram.v:0$43'.
Creating decoders for process `\hyperram.$proc$hyperram.v:245$42'.
Creating decoders for process `\hyperram.$proc$hyperram.v:0$22'.
1/22: $1\next_data_in[31:0] [31:24]
2/22: $6\next_control_state[6:0]
3/22: $1\next_data_in[31:0] [23:16]
4/22: $2\next_done_counter[7:0]
5/22: $1\next_data_in[31:0] [15:8]
6/22: $2\next_data_in[7:0]
7/22: $1\next_data_in[31:0] [7:0]
8/22: $5\next_control_state[6:0]
9/22: $3\next_control_state[6:0]
10/22: $2\next_wait_counter[7:0]
11/22: $2\next_control_state[6:0]
12/22: $1\next_control_state[6:0]
13/22: $1\transaction_end[0:0]
14/22: $1\ck_gate[0:0]
15/22: $1\cs_bar[0:0]
16/22: $4\next_control_state[6:0]
17/22: $1\next_done_counter[7:0]
18/22: $1\next_wait_counter[7:0]
19/22: $1\rwds_oe[0:0]
20/22: $1\rwds_out[0:0]
21/22: $1\dq_oe[0:0]
22/22: $1\dq_out[7:0]
Creating decoders for process `\hyperram.$proc$hyperram.v:72$21'.
1/4: $0\done_counter[7:0]
2/4: $0\wait_counter[7:0]
3/4: $0\data_in_register[31:0]
4/4: $0\control_state[6:0]
Creating decoders for process `\hyperram.$proc$hyperram.v:32$10'.
1/1: $0\ck[0:0]
2.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\hyperram.\rst' from process `\hyperram.$proc$hyperram.v:0$80'.
No latch inferred for signal `\hyperram.\address' from process `\hyperram.$proc$hyperram.v:0$80'.
No latch inferred for signal `\hyperram.\data_out' from process `\hyperram.$proc$hyperram.v:0$80'.
No latch inferred for signal `\hyperram.\data_in_register' from process `\hyperram.$proc$hyperram.v:0$80'.
No latch inferred for signal `\hyperram.\next_command_address' from process `\hyperram.$proc$hyperram.v:0$43'.
No latch inferred for signal `\hyperram.\next_write_mask_register' from process `\hyperram.$proc$hyperram.v:0$43'.
No latch inferred for signal `\hyperram.\next_data_out_register' from process `\hyperram.$proc$hyperram.v:0$43'.
No latch inferred for signal `\hyperram.\transaction_end' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\cs_bar' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\ck_gate' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\dq_out' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\dq_oe' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\rwds_out' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\rwds_oe' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\next_wait_counter' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\next_done_counter' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\next_control_state' from process `\hyperram.$proc$hyperram.v:0$22'.
No latch inferred for signal `\hyperram.\next_data_in' from process `\hyperram.$proc$hyperram.v:0$22'.
2.3.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\hyperram.$formal$hyperram.v:296$1_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$389' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:296$1_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$390' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:297$2_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$391' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:297$2_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$392' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:298$3_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$393' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:298$3_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$394' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:299$4_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$395' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:299$4_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$396' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:300$5_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$397' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:300$5_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$398' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:301$6_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$399' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:301$6_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$400' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:302$7_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$401' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:302$7_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$402' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:303$8_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$403' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:303$8_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$404' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:304$9_CHECK' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$405' with positive edge clock.
Creating register for signal `\hyperram.$formal$hyperram.v:304$9_EN' using process `\hyperram.$proc$hyperram.v:295$50'.
created $dff cell `$procdff$406' with positive edge clock.
Creating register for signal `\hyperram.\read_count' using process `\hyperram.$proc$hyperram.v:268$45'.
created $dff cell `$procdff$407' with positive edge clock.
Creating register for signal `\hyperram.\write_count' using process `\hyperram.$proc$hyperram.v:268$45'.
created $dff cell `$procdff$408' with positive edge clock.
Creating register for signal `\hyperram.\command_address' using process `\hyperram.$proc$hyperram.v:245$42'.
created $dff cell `$procdff$409' with positive edge clock.
Creating register for signal `\hyperram.\write_mask_register' using process `\hyperram.$proc$hyperram.v:245$42'.
created $dff cell `$procdff$410' with positive edge clock.
Creating register for signal `\hyperram.\data_out_register' using process `\hyperram.$proc$hyperram.v:245$42'.
created $dff cell `$procdff$411' with positive edge clock.
Creating register for signal `\hyperram.\wait_counter' using process `\hyperram.$proc$hyperram.v:72$21'.
created $dff cell `$procdff$412' with positive edge clock.
Creating register for signal `\hyperram.\done_counter' using process `\hyperram.$proc$hyperram.v:72$21'.
created $dff cell `$procdff$413' with positive edge clock.
Creating register for signal `\hyperram.\control_state' using process `\hyperram.$proc$hyperram.v:72$21'.
created $dff cell `$procdff$414' with positive edge clock.
Creating register for signal `\hyperram.\data_in_register' using process `\hyperram.$proc$hyperram.v:72$21'.
created $dff cell `$procdff$415' with positive edge clock.
Creating register for signal `\hyperram.\ck' using process `\hyperram.$proc$hyperram.v:32$10'.
created $dff cell `$procdff$416' with positive edge clock.
2.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).
2.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `hyperram.$proc$hyperram.v:0$97'.
Removing empty process `hyperram.$proc$hyperram.v:0$95'.
Removing empty process `hyperram.$proc$hyperram.v:0$93'.
Removing empty process `hyperram.$proc$hyperram.v:0$91'.
Removing empty process `hyperram.$proc$hyperram.v:0$89'.
Removing empty process `hyperram.$proc$hyperram.v:0$87'.
Removing empty process `hyperram.$proc$hyperram.v:0$85'.
Removing empty process `hyperram.$proc$hyperram.v:0$83'.
Removing empty process `hyperram.$proc$hyperram.v:0$81'.
Removing empty process `hyperram.$proc$hyperram.v:0$80'.
Removing empty process `hyperram.$proc$hyperram.v:295$50'.
Found and cleaned up 2 empty switches in `\hyperram.$proc$hyperram.v:268$45'.
Removing empty process `hyperram.$proc$hyperram.v:268$45'.
Removing empty process `hyperram.$proc$hyperram.v:0$43'.
Removing empty process `hyperram.$proc$hyperram.v:245$42'.
Found and cleaned up 6 empty switches in `\hyperram.$proc$hyperram.v:0$22'.
Removing empty process `hyperram.$proc$hyperram.v:0$22'.
Found and cleaned up 1 empty switch in `\hyperram.$proc$hyperram.v:72$21'.
Removing empty process `hyperram.$proc$hyperram.v:72$21'.
Found and cleaned up 1 empty switch in `\hyperram.$proc$hyperram.v:32$10'.
Removing empty process `hyperram.$proc$hyperram.v:32$10'.
Cleaned up 10 empty switches.
2.3.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
<suppressed ~14 debug messages>
2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hyperram..
Removed 16 unused cells and 131 unused wires.
<suppressed ~22 debug messages>
2.6. Executing CHECK pass (checking for obvious problems).
Checking module hyperram...
Found and reported 0 problems.
2.7. Executing OPT pass (performing simple optimizations).
2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\hyperram'.
<suppressed ~210 debug messages>
Removed a total of 70 cells.
2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \hyperram..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$155.
dead port 2/2 on $mux $procmux$170.
dead port 2/2 on $mux $procmux$185.
dead port 2/2 on $mux $procmux$207.
dead port 2/2 on $mux $procmux$299.
dead port 2/2 on $mux $procmux$301.
dead port 2/2 on $mux $procmux$111.
dead port 2/2 on $mux $procmux$122.
Removed 8 multiplexer ports.
<suppressed ~12 debug messages>
2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \hyperram.
New ctrl vector for $pmux cell $procmux$210: { $0$formal$hyperram.v:296$1_CHECK[0:0]$51 $0$formal$hyperram.v:298$3_CHECK[0:0]$55 $eq$hyperram.v:272$48_Y $0$formal$hyperram.v:300$5_CHECK[0:0]$59 $auto$opt_reduce.cc:134:opt_pmux$418 $0$formal$hyperram.v:301$6_CHECK[0:0]$61 }
New ctrl vector for $pmux cell $procmux$324: $auto$opt_reduce.cc:134:opt_pmux$420
New ctrl vector for $pmux cell $procmux$346: $auto$opt_reduce.cc:134:opt_pmux$422
Optimizing cells in module \hyperram.
Performed a total of 3 changes.
2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\hyperram'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hyperram..
Removed 0 unused cells and 78 unused wires.
<suppressed ~1 debug messages>
2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
2.7.8. Rerunning OPT passes. (Maybe there is more to do..)
2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \hyperram..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~11 debug messages>
2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \hyperram.
Performed a total of 0 changes.
2.7.11. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\hyperram'.
Removed a total of 0 cells.
2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hyperram..
2.7.13. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
2.7.14. Finished OPT passes. (There is nothing left to do.)
2.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 bits (of 32) from mux cell hyperram.$ternary$hyperram.v:51$16 ($mux).
Removed top 31 bits (of 32) from mux cell hyperram.$ternary$hyperram.v:52$19 ($mux).
Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:109$23 ($add).
Removed top 25 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:109$23 ($add).
Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:152$30 ($add).
Removed top 24 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:152$30 ($add).
Removed top 5 bits (of 8) from port B of cell hyperram.$eq$hyperram.v:154$31 ($eq).
Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:225$40 ($add).
Removed top 24 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:225$40 ($add).
Removed top 5 bits (of 8) from port B of cell hyperram.$eq$hyperram.v:227$41 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:269$46 ($eq).
Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:270$47 ($add).
Removed top 26 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:270$47 ($add).
Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:272$48 ($eq).
Removed top 31 bits (of 32) from port B of cell hyperram.$add$hyperram.v:273$49 ($add).
Removed top 26 bits (of 32) from port Y of cell hyperram.$add$hyperram.v:273$49 ($add).
Removed top 4 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:297$70 ($eq).
Removed top 4 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:298$71 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:299$72 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:300$73 ($eq).
Removed top 2 bits (of 7) from port B of cell hyperram.$eq$hyperram.v:301$74 ($eq).
Removed top 4 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:302$75 ($eq).
Removed top 4 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:303$76 ($eq).
Removed top 5 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:304$77 ($eq).
Removed top 5 bits (of 6) from port B of cell hyperram.$eq$hyperram.v:304$78 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$213_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$214_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$217_CMP0 ($eq).
Removed top 3 bits (of 7) from port B of cell hyperram.$procmux$218_CMP0 ($eq).
Removed top 4 bits (of 7) from port B of cell hyperram.$procmux$222_CMP0 ($eq).
Removed top 4 bits (of 7) from port B of cell hyperram.$procmux$223_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell hyperram.$procmux$224_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell hyperram.$procmux$225_CMP0 ($eq).
Removed top 6 bits (of 7) from port B of cell hyperram.$procmux$226_CMP0 ($eq).
Removed top 4 bits (of 7) from mux cell hyperram.$procmux$297 ($mux).
Removed top 1 bits (of 32) from FF cell hyperram.$procdff$411 ($dff).
Removed top 4 bits (of 7) from wire hyperram.$4\next_control_state[6:0].
Removed top 25 bits (of 32) from wire hyperram.$add$hyperram.v:109$23_Y.
Removed top 24 bits (of 32) from wire hyperram.$add$hyperram.v:152$30_Y.
Removed top 24 bits (of 32) from wire hyperram.$add$hyperram.v:225$40_Y.
Removed top 26 bits (of 32) from wire hyperram.$add$hyperram.v:270$47_Y.
Removed top 26 bits (of 32) from wire hyperram.$add$hyperram.v:273$49_Y.
2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hyperram..
Removed 0 unused cells and 8 unused wires.
<suppressed ~1 debug messages>
2.10. Executing MEMORY_COLLECT pass (generating $mem cells).
2.11. Executing OPT pass (performing simple optimizations).
2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module hyperram.
2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\hyperram'.
Removed a total of 0 cells.
2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \hyperram..
2.11.4. Finished fast OPT passes.
2.12. Printing statistics.
=== hyperram ===
Number of wires: 89
Number of wire bits: 532
Number of public wires: 36
Number of public wire bits: 399
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 83
$add 5
$cover 9
$dff 19
$eq 22
$logic_and 1
$logic_not 3
$logic_or 1
$mux 17
$pmux 3
$reduce_or 3
2.13. Executing CHECK pass (checking for obvious problems).
Checking module hyperram...
Found and reported 0 problems.
3. Executing HIERARCHY pass (managing design hierarchy).
3.1. Analyzing design hierarchy..
Top module: \hyperram
3.2. Analyzing design hierarchy..
Top module: \hyperram
Removed 0 unused modules.
Module hyperram directly or indirectly contains formal properties -> setting "keep" attribute.
4. Executing JSON backend.
5. Executing RTLIL backend.
Output filename: ../model/design.il
Warnings: 11 unique messages, 11 total
End of script. Logfile hash: 207fb7cd4a, CPU: user 0.11s system 0.00s, MEM: 13.46 MB peak
Yosys 0.15+11 (git sha1 cbece4af0, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 21% 5x opt_clean (0 sec), 17% 6x opt_expr (0 sec), ...