| ## 0:00:00 Solver: yices |
| ## 0:00:00 Checking cover reachability in step 0.. |
| ## 0:00:00 Checking cover reachability in step 1.. |
| ## 0:00:00 Reached cover statement at cover_idle in step 1. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace0.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace0_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace0.smtc |
| ## 0:00:00 Checking cover reachability in step 1.. |
| ## 0:00:00 Checking cover reachability in step 2.. |
| ## 0:00:00 Checking cover reachability in step 3.. |
| ## 0:00:00 Checking cover reachability in step 4.. |
| ## 0:00:00 Checking cover reachability in step 5.. |
| ## 0:00:00 Checking cover reachability in step 6.. |
| ## 0:00:00 Checking cover reachability in step 7.. |
| ## 0:00:00 Reached cover statement at cover_ca in step 7. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace1.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace1_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace1.smtc |
| ## 0:00:00 Checking cover reachability in step 7.. |
| ## 0:00:00 Checking cover reachability in step 8.. |
| ## 0:00:00 Reached cover statement at cover_wait in step 8. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace2.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace2_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace2.smtc |
| ## 0:00:00 Checking cover reachability in step 8.. |
| ## 0:00:00 Checking cover reachability in step 9.. |
| ## 0:00:00 Checking cover reachability in step 10.. |
| ## 0:00:00 Checking cover reachability in step 11.. |
| ## 0:00:00 Checking cover reachability in step 12.. |
| ## 0:00:00 Checking cover reachability in step 13.. |
| ## 0:00:00 Reached cover statement at cover_write in step 13. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace3.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace3_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace3.smtc |
| ## 0:00:00 Checking cover reachability in step 13.. |
| ## 0:00:00 Reached cover statement at cover_read in step 13. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace4.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace4_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace4.smtc |
| ## 0:00:00 Checking cover reachability in step 13.. |
| ## 0:00:00 Checking cover reachability in step 14.. |
| ## 0:00:00 Checking cover reachability in step 15.. |
| ## 0:00:00 Checking cover reachability in step 16.. |
| ## 0:00:00 Checking cover reachability in step 17.. |
| ## 0:00:00 Reached cover statement at cover_done in step 17. |
| ## 0:00:00 Writing trace to VCD file: engine_0/trace5.vcd |
| ## 0:00:00 Writing trace to Verilog testbench: engine_0/trace5_tb.v |
| ## 0:00:00 Writing trace to constraints file: engine_0/trace5.smtc |
| ## 0:00:00 Checking cover reachability in step 17.. |
| ## 0:00:00 Checking cover reachability in step 18.. |
| ## 0:00:00 Checking cover reachability in step 19.. |
| ## 0:00:01 Checking cover reachability in step 20.. |
| ## 0:00:01 Checking cover reachability in step 21.. |
| ## 0:00:01 Checking cover reachability in step 22.. |
| ## 0:00:01 Checking cover reachability in step 23.. |
| ## 0:00:01 Checking cover reachability in step 24.. |
| ## 0:00:01 Checking cover reachability in step 25.. |
| ## 0:00:01 Checking cover reachability in step 26.. |
| ## 0:00:01 Checking cover reachability in step 27.. |
| ## 0:00:01 Checking cover reachability in step 28.. |
| ## 0:00:01 Checking cover reachability in step 29.. |
| ## 0:00:02 Checking cover reachability in step 30.. |
| ## 0:00:02 Checking cover reachability in step 31.. |
| ## 0:00:02 Checking cover reachability in step 32.. |
| ## 0:00:02 Checking cover reachability in step 33.. |
| ## 0:00:02 Checking cover reachability in step 34.. |
| ## 0:00:03 Checking cover reachability in step 35.. |
| ## 0:00:03 Checking cover reachability in step 36.. |
| ## 0:00:03 Checking cover reachability in step 37.. |
| ## 0:00:04 Checking cover reachability in step 38.. |
| ## 0:00:04 Reached cover statement at cover_write_read in step 38. |
| ## 0:00:04 Writing trace to VCD file: engine_0/trace6.vcd |
| ## 0:00:04 Writing trace to Verilog testbench: engine_0/trace6_tb.v |
| ## 0:00:04 Writing trace to constraints file: engine_0/trace6.smtc |
| ## 0:00:04 Checking cover reachability in step 38.. |
| ## 0:00:04 Reached cover statement at cover_write_2 in step 38. |
| ## 0:00:04 Writing trace to VCD file: engine_0/trace7.vcd |
| ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace7_tb.v |
| ## 0:00:05 Writing trace to constraints file: engine_0/trace7.smtc |
| ## 0:00:05 Checking cover reachability in step 38.. |
| ## 0:00:05 Reached cover statement at cover_read_2 in step 38. |
| ## 0:00:05 Writing trace to VCD file: engine_0/trace8.vcd |
| ## 0:00:05 Writing trace to Verilog testbench: engine_0/trace8_tb.v |
| ## 0:00:05 Writing trace to constraints file: engine_0/trace8.smtc |
| ## 0:00:05 Status: passed |
