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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / ebc597893de34ad22c6a708a8deb2b1d1d2c76bd / verilog / rtl
  1. d180822 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 4 years, 4 months ago
  2. 16a6403 Correct instance names that iverilog doesn't like by Ahmed Ghazy · 4 years, 4 months ago
  3. 32f18ac Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years, 4 months ago
  4. 9ba3e59 Added GL simulations by manarabdelaty · 4 years, 4 months ago
  5. 4d0d957 Wrap lsbufhv2lv to eliminate li1 pins at the top by Ahmed Ghazy · 4 years, 4 months ago
  6. e87140d Merge branch 'develop' into new_wrapper by ax3ghazy · 4 years, 4 months ago
  7. 2d313b4 Merge pull request #9 from ax3ghazy/develop-fork by ax3ghazy · 4 years, 4 months ago
  8. d19e86d Add two more missing USE_POWER_PINS guards by Ahmed Ghazy · 4 years, 4 months ago
  9. b3eca4c Add more missing USE_POWER_PINS by Ahmed Ghazy · 4 years, 4 months ago
  10. 02b06a9 Minor RTL fixes, switching to wrapped GPIOV2 by Ahmed Ghazy · 4 years, 4 months ago
  11. 1b349ac Split the high voltage part of the mgmt_protect.v module into its own by Tim Edwards · 4 years, 4 months ago
  12. f9fef50 Added ngspice netlist and testbenches for the power-on-reset circuit. by Tim Edwards · 4 years, 4 months ago
  13. f084de3 Corrected the logic in mgmt_protect; also corrected a problem in the la_test2 by Tim Edwards · 4 years, 4 months ago
  14. 5b7e875 Corrections to the management protection buffer block, and a couple of corrections by Tim Edwards · 4 years, 4 months ago
  15. aa491d4 Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
  16. 800ea8a Add missing USE_POWER_PINS in other modules by Ahmed Ghazy · 4 years, 4 months ago
  17. 910bdc7 Eliminate the two inverters at the top level by Ahmed Ghazy · 4 years, 4 months ago
  18. 82a2e68 add missing signals by Matt Venn · 4 years, 4 months ago
  19. 86ec7cd add default nettype none by Matt Venn · 4 years, 4 months ago
  20. a089bfc Updated custom memory by Manar · 4 years, 5 months ago
  21. afb08a3 Renamed lvs guard to use_power_pins by Manar · 4 years, 5 months ago
  22. 8f81142 Updated storage area by Manar · 4 years, 5 months ago
  23. 9c822c6 Merge pull request #33 from Manarabdelaty/custom_mem by R. Timothy Edwards · 4 years, 5 months ago
  24. 009f0d4 Merge pull request #32 from dan-rodrigues/user_proj_wb_ack by R. Timothy Edwards · 4 years, 5 months ago
  25. 2a12630 Added power pins to the custom memory cells by Manar · 4 years, 5 months ago
  26. a5a2b0a Add USE_CUSTOM_DFFRAM guard by Ahmed Ghazy · 4 years, 5 months ago
  27. f328311 user_proj_example: fix wbs_ack_o wiring by Dan Rodrigues · 4 years, 5 months ago
  28. 6a910c7 Add the custom DFF RAM by Ahmed Ghazy · 4 years, 5 months ago
  29. 07a8a05 Connected WB MI A port outputs to the wb bus by Manar · 4 years, 5 months ago
  30. c923c13 Added localparam for calculating mem address bits by Manar · 4 years, 5 months ago
  31. ff52415 Updated default number of sram blocks for the user area by Manar · 4 years, 5 months ago
  32. d855783 Merge pull request #27 from ax3ghazy/conflict_warnings_fix by R. Timothy Edwards · 4 years, 5 months ago
  33. 75bd878 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 5 months ago
  34. c1e11f8 Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 5 months ago
  35. b3e8dca Connected storage area to mgmt_core by Manar · 4 years, 5 months ago
  36. 42d2411 Seperated mgmt and user storage blocks base addresses by Manar · 4 years, 5 months ago
  37. 3a6aaab Added storage area standalone rtl by Manar · 4 years, 5 months ago
  38. a922b7c Removed storage area from mgmt_core by Manar · 4 years, 5 months ago
  39. 206b575 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
  40. 7e67b42 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
  41. 4d7d01b Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
  42. f1eb121 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
  43. 9481c1f Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 5 months ago
  44. 25d253a Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 5 months ago
  45. b9d1e7d Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
  46. 739eb6e Made a number of modifications to the counter-timer to correctly pipeline by Tim Edwards · 4 years, 5 months ago
  47. c5bf3ec Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
  48. d92863b Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 5 months ago
  49. 5169896 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 5 months ago
  50. 4814a40 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
  51. c6ccc4e Removed cross bar switch port from mgmt core by Manar · 4 years, 5 months ago
  52. 7828bfe Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
  53. aef447b Merge pull request #18 from ax3ghazy/params by R. Timothy Edwards · 4 years, 5 months ago
  54. 066015b Merge pull request #15 from ax3ghazy/release by R. Timothy Edwards · 4 years, 5 months ago
  55. 367241e Fix typos in parameter names by Ahmed Ghazy · 4 years, 5 months ago
  56. 1deae09 Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 5 months ago
  57. b702e56 Move wire declarations before they're first used by Ahmed Ghazy · 4 years, 5 months ago
  58. fb6eaee (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 5 months ago
  59. 47ff6e7 Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 5 months ago
  60. 16ae382 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 5 months ago
  61. c2258f0 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 5 months ago
  62. 4236bdc Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 6 months ago
  63. 6bee2ad Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 6 months ago
  64. 2101031 Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
  65. 53bee22 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 6 months ago
  66. 514dfd8 Finalized the voltage clamp arrangement and the total number of pads. by Tim Edwards · 4 years, 6 months ago
  67. 66322fd Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 6 months ago
  68. c196378 Added a behavioral model for the ring oscillator, and a testbench by Tim Edwards · 4 years, 6 months ago
  69. dd19d6d Modified code to let SPI master control the housekeeping SPI through by Tim Edwards · 4 years, 6 months ago
  70. c47465c Corrected the counter/timer and made an enhancement to respond to a by Tim Edwards · 4 years, 6 months ago
  71. d418fdd Added management flash SPI pass-through mode testbench and debugged it. by Tim Edwards · 4 years, 6 months ago
  72. e2aa7eb Removed temporary file. by Tim Edwards · 4 years, 6 months ago
  73. d31b918 Corrected the error causing the failure of the GPIO testbench. by Tim Edwards · 4 years, 6 months ago
  74. a239c56 Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
  75. 65f571d Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago
  76. 22a7435 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
  77. e8fb9ff Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 6 months ago
  78. 46f5025 Made corrections; GPIO testbench now passes. by Tim Edwards · 4 years, 6 months ago
  79. 68338d5 Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
  80. 19ddfd0 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
  81. c5c7ed1 Corrected the primary issue with simulation, which was the failure by Tim Edwards · 4 years, 6 months ago
  82. c1b1895 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
  83. b5d5b27 Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
  84. dcf18eb Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 4 years, 6 months ago
  85. 9f38569 Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 6 months ago
  86. b25102e harness phase1 initial commit by shalan · 4 years, 7 months ago
  87. 114091e initial commit by shalan · 4 years, 7 months ago
  88. b19394a Started adding RTL for the Caravel project by Tim Edwards · 4 years, 8 months ago