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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / c196378ea9725e767685b012e06a2229d9c3cede
commitc196378ea9725e767685b012e06a2229d9c3cede[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 22:00:23 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 22:00:23 2020 -0400
treeb81451f1f1495e75a21ad4ae4f38ed4f69268c21
parentdd19d6ded606bca2f40b755bff21882d9d5eec0c [diff]
Added a behavioral model for the ring oscillator, and a testbench
for running the PLL (in behavioral mode), specifically for switching
to and from PLL bypass mode from the processor itself.
7 files changed
tree: b81451f1f1495e75a21ad4ae4f38ed4f69268c21
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.