| commit | 66322fde7057afb93f91b7d1f0720d72c431761e | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Sat Oct 10 14:02:11 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Sat Oct 10 14:02:11 2020 -0400 |
| tree | cdef30cc5919104cb0c3a6f8bf7941deb9df2dd4 | |
| parent | 5ba0cc240cc6357e6916b212ae4df491feddad38 [diff] |
Revised the clocking scheme in several ways: (1) Removed the output clock divider from the PLL to the clocking module; (2) changed the clock divider from a power-of-2 divider to an integer-N divider; (3) added an enable to the PLL separate from the bypass, so that the PLL can be started and have time to settle before being switched in. (4) Made some attempts at glitch-free clock switching when changing to and from the PLL, and when changing output divider values.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: