| commit | 5ba0cc240cc6357e6916b212ae4df491feddad38 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 09 22:21:30 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 09 22:21:30 2020 -0400 |
| tree | 910aede28610700cf6d460db044bb15471e580cf | |
| parent | a09499e695322e1449d17e17f0020c58c3a521d8 [diff] |
Solved the trap issue by not driving the PLL clock so fast (not sure why that happens in a behavioral simulation, though). PLL still needs glitch- free switching and needs to be able to run the PLL and let it settle before switching the core clock.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: