)]}'
{
  "commit": "66322fde7057afb93f91b7d1f0720d72c431761e",
  "tree": "cdef30cc5919104cb0c3a6f8bf7941deb9df2dd4",
  "parents": [
    "5ba0cc240cc6357e6916b212ae4df491feddad38"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 10 14:02:11 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 10 14:02:11 2020 -0400"
  },
  "message": "Revised the clocking scheme in several ways:  (1) Removed the output\nclock divider from the PLL to the clocking module;  (2) changed the\nclock divider from a power-of-2 divider to an integer-N divider;\n(3) added an enable to the PLL separate from the bypass, so that the\nPLL can be started and have time to settle before being switched in.\n(4) Made some attempts at glitch-free clock switching when changing\nto and from the PLL, and when changing output divider values.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "dd8e0d6bc3bafc19bd846b5451b60b3cb42cfb35",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c",
      "new_id": "b74860b58acd9304cbe1d9f61f064bde92190423",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c"
    },
    {
      "type": "modify",
      "old_id": "5fc90d43ce6e561142bf1e7f8d6bbf97f79d8f73",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "79830be9fefbe098c9f033eb112094bb2ceb6b1e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "delete",
      "old_id": "af40b8f6fd160b8c9d310408190e0e93e12acaf0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_clkrst.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "db249d2b1d7e0dad3174e11eee7be4b40f910d2b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel_clocking.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "01d03a8266ed98f5983c060d824d4300b6879c33",
      "new_mode": 33188,
      "new_path": "verilog/rtl/clock_div.v"
    },
    {
      "type": "modify",
      "old_id": "d4fe6ff3866982699f0cba5969e7efa4401abde7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/digital_pll.v",
      "new_id": "77cce426039ecf4deaf93f3667ff2dfe76b3f17e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/digital_pll.v"
    },
    {
      "type": "modify",
      "old_id": "42677d4f6dd436ff31909154b4fe6294794dfc6f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/housekeeping_spi.v",
      "new_id": "879aff8f53064c566a293af7997e076adbf585c7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "297b76ae8d9039359c52026fe8553016b93dd21a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "8435a5e5d1059f5ff69a6c4d59360fa0a322c73f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "5f1050d40ca9ed4069bb8e4cdafc7f36428b748f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "91dfbd5d58579a7a1c39c8a88edc26fccdcaeba9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    }
  ]
}