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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 458aedcf173b17423939e005183f62530560872a / . / sky130 / magic / sky130.tech
blob: ba24557ebe267656d7abba7643361b65d2f904e4 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]66# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v5 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]144 dwell isosubstrate,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]163 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]167 -active mvnmosesd,mvntransistoresd,mvnfetesd
168 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]169 active varactor,varact,var
170 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]171
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]172 active pmoslvt,pfetlvt
173 active pmosmvt,pfetmvt
174 active pmoshvt,pfethvt
175 active nmoslvt,nfetlvt
176 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]177 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]178 -active sramnvar,corenvar,corenvaractor
179 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]180
181# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]182 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]183 active ndiff,ndiffusion,ndif
184 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]185 active mvndiff,mvndiffusion,mvndif
186 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]187 active ndiffc,ndcontact,ndc
188 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]189 active mvndiffc,mvndcontact,mvndc
190 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]191 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
192 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
193 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
194 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
195 active psubdiffcont,psubstratepcontact,psc,ptapc
196 active nsubdiffcont,nsubstratencontact,nsc,ntapc
197 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
198 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]199 -active obsactive
200 -active mvobsactive
201
202# Poly
203 active poly,p,polysilicon
204 active polycont,pc,pcontact,polycut,polyc
205 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]206 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]207
208# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]209 active npolyres,npres,mrp1
210 active ppolyres,ppres,xhrpoly
211 active xpolyres,xpres,xres,uhrpoly
212 active ndiffres,rnd,rdn,rndiff
213 active pdiffres,rpd,rdp,rpdiff
214 active mvndiffres,mvrnd,mvrdn,mvrndiff
215 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
216 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]217
218# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]219 active pdiode,pdi
220 active ndiode,ndi
221 active nndiode,nndi
222 active pdiodec,pdic
223 active ndiodec,ndic
224 active nndiodec,nndic
225 active mvpdiode,mvpdi
226 active mvndiode,mvndi
227 active mvpdiodec,mvpdic
228 active mvndiodec,mvndic
229 active pdiodelvt,pdilvt
230 active pdiodehvt,pdihvt
231 active ndiodelvt,ndilvt
232 active pdiodelvtc,pdilvtc
233 active pdiodehvtc,pdihvtc
234 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235
236# Local Interconnect
237 locali locali,li1,li
238 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]239 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]240 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]243 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]244
245# Metal 1
246 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]248 metal1 via1,m2contact,m2cut,m2c,via,v,v1
249 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]250 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 2
254 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 metal2 via2,m3contact,m3cut,m3c,v2
257 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]258 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259
260# Metal 3
261 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]263 -metal3 obsm3
264#ifdef METAL5
265 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]266 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]267
268#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]269 cap1 mimcap,mim,capm
270 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]271#endif
272
273# Metal 4
274 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276 -metal4 obsm4
277 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]278 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]279
280#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 cap2 mimcap2,mim2,capm2
282 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif
284
285# Metal 5
286 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]289 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]290#endif (METAL5)
291
292#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]293 metal5 mrdlcontact,mrdlc,pi1
294 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]296 metali pi2
297 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]298#endif (REDISTRIBUTION)
299
300# Miscellaneous
301 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]302 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]303 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]305# fixed resistor width identifiers
306 -comment res0p35
307 -comment res0p69
308 -comment res1p41
309 -comment res2p85
310 -comment res5p73
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]311# fixed bipolar area identifiers
312 -comment pnp0p68
313 -comment pnp3p40
314 -comment npn1p00
315 -comment npn2p00
316 -comment npn11p0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]317
318end
319
320#-----------------------------------------------------
321# Magic contact types
322#-----------------------------------------------------
323
324contact
325 pc poly locali
326 ndc ndiff locali
327 pdc pdiff locali
328 nsc nsd locali
329 psc psd locali
330 ndic ndiode locali
331 ndilvtc ndiodelvt locali
332 nndic nndiode locali
333 pdic pdiode locali
334 pdilvtc pdiodelvt locali
335 pdihvtc pdiodehvt locali
336 xpc xpc locali
337
338 mvndc mvndiff locali
339 mvpdc mvpdiff locali
340 mvnsc mvnsd locali
341 mvpsc mvpsd locali
342 mvndic mvndiode locali
343 mvpdic mvpdiode locali
344
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]345 mcon locali metal1
346 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]347
348 via1 metal1 metal2
349 via2 metal2 metal3
350#ifdef METAL5
351 via3 metal3 metal4
352 via4 metal4 metal5
353#endif (METAL5)
354 stackable
355
356#ifdef METAL5
357#ifdef MIM
358 # MiM cap contacts are not stackable!
359 mimcc mimcap metal4
360 mim2cc mimcap2 metal5
361#endif (MIM)
362
363 padl m1 m2 m3 m4 m5 glass
364#else
365 padl m1 m2 m3 glass
366#endif (!METAL5)
367
368#ifdef REDISTRIBUTION
369 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]370 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]371#endif (REDISTRIBUTION)
372end
373
374#-----------------------------------------------------
375# Layer aliases
376#-----------------------------------------------------
377
378aliases
379
380 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]381 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]382
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]383 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]384 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]385 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]386 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allfetsspecial scnfet,scpfet,scpfethvt
388 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]389 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]390
391 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
392 allnactive allnactivenonfet,allnfets
393 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]394 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]395
396 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
397 allpactive allpactivenonfet,allpfets
398 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]399 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]400
401 allactivenonfet allnactivenonfet,allpactivenonfet
402 allactive allactivenonfet,allfets
403
404 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
405
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]406 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]407 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]408 alldifflv allndifflv,allpdifflv
409 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
410 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
411 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
412
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]413 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]414 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]415 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]416 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]417 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]418 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
419 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
420 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
421 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
422
423 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]424 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]425
426 allpolyres mrp1,xhrpoly,uhrpoly,rmp
427 allpolynonfet *poly,allpolyres,xpc
428 allpolynonres *poly,allfets,xpc
429
430 allpoly allpolynonfet,allfets
431 allpolynoncap *poly,xpc,allfets,allpolyres
432
433 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
434 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
435 allndiffcontmv mvndc,mvnsc,mvndic
436 allpdiffcontmv mvpdc,mvpsc,mvpdic
437 allndiffcont allndiffcontlv,allndiffcontmv
438 allpdiffcont allpdiffcontlv,allpdiffcontmv
439 alldiffcontlv allndiffcontlv,allpdiffcontlv
440 alldiffcontmv allndiffcontmv,allpdiffcontmv
441 alldiffcont alldiffcontlv,alldiffcontmv
442
443 allcont alldiffcont,pc
444
445 allres allpolyres,allactiveres
446
447 allli *locali,coreli,rli
448 allm1 *m1,rm1
449 allm2 *m2,rm2
450 allm3 *m3,rm3
451#ifdef METAL5
452 allm4 *m4,rm4
453 allm5 *m5,rm5
454#endif (METAL5)
455
456 allpad padl
457
458 psub pwell
459
460end
461
462#-----------------------------------------------------
463# Layer drawing styles
464#-----------------------------------------------------
465
466styles
467 styletype mos
468 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]469 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]470 nwell nwell
471 pwell pwell
472 rpwell pwell ptransistor_stripes
473 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]474 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]475 pdiff pdiffusion
476 nsd ndiff_in_nwell
477 psd pdiff_in_pwell
478 nfet ntransistor ntransistor_stripes
479 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]480 npass ntransistor ntransistor_stripes
481 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]482 pfet ptransistor ptransistor_stripes
483 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]484 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]485 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 var polysilicon ndiff_in_nwell
487 ndc ndiffusion metal1 contact_X'es
488 pdc pdiffusion metal1 contact_X'es
489 nsc ndiff_in_nwell metal1 contact_X'es
490 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]491 corenvar polysilicon ndiff_in_nwell
492 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]493
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]494 pnp nwell ntransistor_stripes
495 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]496
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]498 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]499 pfethvt ptransistor ptransistor_stripes implant2
500 nfetlvt ntransistor ntransistor_stripes implant1
501 nsonos ntransistor implant3
502 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]503 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]504
505 mvndiff ndiffusion hvndiff_mask
506 mvpdiff pdiffusion hvpdiff_mask
507 mvnsd ndiff_in_nwell hvndiff_mask
508 mvpsd pdiff_in_pwell hvpdiff_mask
509 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]510 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]511 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
512 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]513 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]514 mvvar polysilicon ndiff_in_nwell hvndiff_mask
515 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
516 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
517 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
518 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
519
520 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]521 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]522 pc polysilicon metal1 contact_X'es
523 npolyres polysilicon silicide_block nselect2
524 ppolyres polysilicon silicide_block pselect2
525 xpc polysilicon pselect2 metal1 contact_X'es
526 rmp polysilicon poly_resist_stripes
527
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]528 res0p35 implant1
529 res0p69 implant1
530 res1p41 implant1
531 res2p85 implant1
532 res5p73 implant1
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]533 pnp0p68 implant1
534 pnp3p40 implant1
535 npn1p00 implant1
536 npn2p00 implant1
537 npn11p0 implant1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]538
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]539 pdiode pdiffusion pselect2
540 ndiode ndiffusion nselect2
541 pdiodec pdiffusion pselect2 metal1 contact_X'es
542 ndiodec ndiffusion nselect2 metal1 contact_X'es
543
544 nndiode ndiffusion nselect2 implant3
545 ndiodelvt ndiffusion nselect2 implant1
546 pdiodelvt pdiffusion pselect2 implant1
547 pdiodehvt pdiffusion pselect2 implant2
548 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
549 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
550 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
551
552 mvpdiode pdiffusion pselect2 hvpdiff_mask
553 mvndiode ndiffusion nselect2 hvndiff_mask
554 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
555 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
556 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
557
558 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]559 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]560 coreli metal1
561 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]562 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]563 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]564 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]565
566 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]567 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]568 rm1 metal2 poly_resist_stripes
569 obsm1 metal2
570 m2c metal2 metal3 via2arrow
571 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]572 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]573 rm2 metal3 poly_resist_stripes
574 obsm2 metal3
575 m3c metal3 metal4 via3alt
576 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]577 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]578 rm3 metal4 poly_resist_stripes
579 obsm3 metal4
580#ifdef METAL5
581#ifdef MIM
582 mimcap metal3 mems
583 mimcc metal3 contact_X'es mems
584 mimcap2 metal4 mems
585 mim2cc metal4 contact_X'es mems
586#endif (MIM)
587 via3 metal4 metal5 via4
588 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]589 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]590 rm4 metal5 poly_resist_stripes
591 obsm4 metal5
592 via4 metal5 metal6 via5
593 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]594 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]595 rm5 metal6 poly_resist_stripes
596 obsm5 metal6
597#endif (METAL5)
598#ifdef REDISTRIBUTION
599 mrdlc metal6 metal7 via6
600 metalrdl metal7
601 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]602 ubm metal8
603 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]604#endif (REDISTRIBUTION)
605
606 glass overglass
607 mrp1 poly_resist poly_resist_stripes
608 xhrpoly poly_resist silicide_block
609 uhrpoly poly_resist
610 ndiffres ndiffusion ndop_stripes
611 pdiffres pdiffusion pdop_stripes
612 mvndiffres ndiffusion hvndiff_mask ndop_stripes
613 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
614 comment comment
615 error_p error_waffle
616 error_s error_waffle
617 error_ps error_waffle
618 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]619 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]620
621 obswell cwell
622 obsactive implant4
623
624#ifndef METAL5
625 padl metal4 via4 overglass
626#else
627 padl metal6 via6 overglass
628#endif
629
630 magnet substrate_field_implant
631 rotate via3alt
632 fence via5
633end
634
635#-----------------------------------------------------
636# Special paint/erase rules
637#-----------------------------------------------------
638
639compose
640 compose nfet poly ndiff
641 compose pfet poly pdiff
642 compose var poly nsd
643
644 compose mvnfet poly mvndiff
645 compose mvpfet poly mvpdiff
646 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]647
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]648 paint obsmcon locali via1
649 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]650
651 paint ndc nwell pdc
652 paint nfet nwell pfet
653 paint scnfet nwell scpfet
654 paint ndiff nwell pdiff
655 paint psd nwell nsd
656 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]657 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]658
659 paint pdc pwell ndc
660 paint pfet pwell nfet
661 paint scpfet pwell scnfet
662 paint pdiff pwell ndiff
663 paint nsd pwell psd
664 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]665 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]666
667 paint pdc coreli pdc
668 paint ndc coreli ndc
669 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]670 paint nsc coreli nsc
671 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]672 paint viali coreli viali
673
674 paint coreli pdc pdc
675 paint coreli ndc ndc
676 paint coreli pc pc
677 paint coreli nsc nsc
678 paint coreli psc psc
679 paint coreli viali viali
680
681#ifdef METAL5
682 paint m4 obsm4 m4
683 paint m5 obsm5 m5
684#endif (METAL5)
685end
686
687#-----------------------------------------------------
688# Electrical connectivity
689#-----------------------------------------------------
690
691connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]692 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
693 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]694 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]695 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]696 *m2,m2fill *m2,m2fill
697 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]698#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]699 *m4,m4fill *m4,m4fill
700 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]701#ifdef MIM
702 *mimcap *mimcap
703 *mimcap2 *mimcap2
704#endif (MIM)
705#endif (METAL5)
706 allnactivenonfet allnactivenonfet
707 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]708 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]709#ifdef REDISTRIBUTION
710 # RDL connects to m5 (i.e., padl) through glass cut
711 *mrdl *mrdl
712 glass metrdl
713#endif (REDISTRIBUTION)
714end
715
716#-----------------------------------------------------
717# CIF/GDS output layer definitions
718#-----------------------------------------------------
719# NOTE: All values in this section MUST be multiples of 25
720# or else magic will scale below the allowed layout grid size
721
722cifoutput
723
724#----------------------------------------------------------------
725style gdsii
726# NOTE: This section is used for actual GDS output
727#----------------------------------------------------------------
728 scalefactor 10 nanometers
729 options calma-permissive-labels
730 gridlimit 5
731
732#----------------------------------------------------------------
733# Create a temp layer from the cell bounding box for use in
734# generating ID layers. Note that "boundary", unlike "bbox",
735# requires the FIXED_BBOX property (abutment box) in the cell.
736#----------------------------------------------------------------
737 templayer CELLBOUND
738 boundary
739
740#----------------------------------------------------------------
741# BOUND
742#----------------------------------------------------------------
743 layer BOUND CELLBOUND
744 calma 235 4
745
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]746#----------------------------------------------------------------
747# DNWELL
748#----------------------------------------------------------------
749
Tim Edwards4d579412021-06-01 15:59:24 -0400[diff] [blame]750 layer DNWELL dnwell,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]751 calma 64 18
752
753 layer PWRES rpw
754 and dnwell
755 calma 64 13
756
757#----------------------------------------------------------------
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]758# SUBCUT
759#----------------------------------------------------------------
760
761 layer SUBCUT isosub
762 calma 81 53
763
764#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]765# NWELL
766#----------------------------------------------------------------
767
768 layer NWELL allnwell
769 bloat-all rpw dnwell
770 and-not rpw,pwell
771 calma 64 20
772
773 layer WELLTXT
774 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]775 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]776
777 layer WELLPIN
778 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]779 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]780
781#----------------------------------------------------------------
782# SUB (text/port only)
783#----------------------------------------------------------------
784
785 layer SUBTXT
786 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]787 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]788
789 layer SUBPIN
790 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]791 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]792
793#----------------------------------------------------------------
794# DIFF
795#----------------------------------------------------------------
796
797 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]798 calma 65 20
799
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]800 layer DIFFTXT
801 labels allnactivenontap,allpactivenontap noport
802 calma 65 6
803
804 layer DIFFPIN
805 labels allnactivenontap,allpactivenontap port
806 calma 65 16
807
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]808#----------------------------------------------------------------
809# TAP
810#----------------------------------------------------------------
811
812 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]813 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]814 calma 65 44
815
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]816 layer TAPTXT
817 labels allnactivetap,allpactivetap noport
818 calma 65 5
819
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]820#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]821# FOM
822#----------------------------------------------------------------
823
824 layer FOMFILL fomfill
825 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]826 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]827
828#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]829# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]830#----------------------------------------------------------------
831
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]832 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]833 grow 15
834 or xhrpoly,uhrpoly,xpc
835 grow 110
836 bloat-or allpactivetap * 125 allnactivenontap 0
837 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]838
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]839 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]840 grow 125
841 bloat-or allnactivetap * 125 allpactivenontap 0
842 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]843
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]844 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]845 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]846 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]847
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]848 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]849 grow 185
850 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]851 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]852 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]853 calma 94 20
854
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]855 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]856 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]857 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]858
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]859 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]860 grow 185
861 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]862 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]863 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]864 calma 93 44
865
866#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]867# LVID
868#----------------------------------------------------------------
869
870 layer LVID nnfet
871 grow 100
872 calma 81 60
873
874#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]875# LVTN
876#----------------------------------------------------------------
877
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]878 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]879 grow 180
880 bridge 380 380
881 grow 185
882 shrink 185
883 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]884 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]885 calma 125 44
886
887#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]888# HVTR
889#----------------------------------------------------------------
890
891 layer HVTR pfetmvt
892 grow 180
893 bridge 380 380
894 grow 185
895 shrink 185
896 close 265000
897 calma 18 20
898
899#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]900# HVTP
901#----------------------------------------------------------------
902
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]903 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]904 grow 180
905 bridge 380 380
906 grow 185
907 shrink 185
908 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]909 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]910 calma 78 44
911
912#----------------------------------------------------------------
913# SONOS
914#----------------------------------------------------------------
915
916 layer SONOS nsonos
917 grow 100
918 grow-min 410
919 bridge 500 410
920 grow 250
921 shrink 250
922 calma 80 20
923
924#----------------------------------------------------------------
925# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]926# coreli layer indicates a cell needing COREID. Also, devices
927# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]928#----------------------------------------------------------------
929
930 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]931 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]932 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]933 calma 81 2
934
935#----------------------------------------------------------------
936# STDCELL applies to all cells containing scnfet or scpfet.
937#----------------------------------------------------------------
938
939 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]940 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]941 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]942 calma 81 4
943
944#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]945# ESDID is a marker layer for ESD devices in the padframe I/O.
946#----------------------------------------------------------------
947
948 layer ESDID
949 bloat-all mvnfetesd *mvndiff,*poly
950 bloat-all mvpfetesd *mvpdiff,*poly
951 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]952 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]953 calma 81 19
954
955#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]956# NPNID and PNPID apply to bipolar transistors
957#----------------------------------------------------------------
958
959 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]960 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]961 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]962 calma 82 20
963
964 templayer pnparea pnp
965 grow 400
966
967 layer PNPID
968 bloat-all pnparea *psd
969 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]970 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]971 calma 82 44
972
973#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]974# RPM
975#----------------------------------------------------------------
976
977 layer RPM
978 bloat-all xhrpoly xpc
979 grow 200
980 grow-min 1270
981 grow 420
982 shrink 420
983 calma 86 20
984
985#----------------------------------------------------------------
986# URPM (2kOhms/sq. poly implant)
987#----------------------------------------------------------------
988
989 layer URPM
990 bloat-all uhrpoly xpc
991 grow 200
992 grow-min 1270
993 grow 420
994 shrink 420
995 calma 79 20
996
997#----------------------------------------------------------------
998# LDNTM (Tip implant for SONOS FETs)
999#----------------------------------------------------------------
1000
1001 layer LDNTM
1002 bloat-all nsonos *ndiff
1003 grow 185
1004 grow 345
1005 shrink 345
1006 calma 11 44
1007
1008#----------------------------------------------------------------
1009# HVNTM (Tip implant for MV ndiff devices)
1010#----------------------------------------------------------------
1011
1012 templayer hvntm_block *mvpsd
1013 grow 185
1014
1015 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1016 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1017 bloat-all mvvaractor *mvnsd
1018 and-not hvntm_block
1019 grow 185
1020 grow 345
1021 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1022 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1023 calma 125 20
1024
1025#----------------------------------------------------------------
1026# POLY
1027#----------------------------------------------------------------
1028
1029 layer POLY allpoly
1030 calma 66 20
1031
1032 layer POLYTXT
1033 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1034 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1035
1036 layer POLYPIN
1037 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1038 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1039
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1040 layer POLYFILL polyfill
1041 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1042 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1043
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1044#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1045# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1046#----------------------------------------------------------------
1047
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1048 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1049 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1050 bloat-all alldiffmv nwell
1051 grow 345
1052 shrink 345
1053
1054 templayer large_ptap_mv thkox_area
1055 shrink 420
1056 grow 420
1057
1058 templayer small_ptap_mv thkox_area
1059 and-not large_ptap_mv
1060 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1061 grow-min 840
1062
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1063 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1064 bridge 700 600
1065 grow 345
1066 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1067 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1068 calma 75 20
1069
1070#----------------------------------------------------------------
1071# CONT (LICON)
1072#----------------------------------------------------------------
1073
1074 layer CONT allcont
1075 squares-grid 0 170 170
1076 calma 66 44
1077
1078 # Contact for pres is different than other LICON contacts
1079 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1080 templayer xpc_horiz xpc
1081 shrink 1007
1082 grow 1007
1083
1084 layer CONT xpc
1085 and-not xpc_horiz
1086 # Force long edge vertical for contacts narrower than 2um
1087 # Minimum space is 350 but 520 satisfies no. of contacts rule
1088 slots 80 190 520 80 2000 350
1089 calma 66 44
1090
1091 layer CONT xpc
1092 and xpc_horiz
1093 # Force long edge vertical for contacts wider than 2um
1094 # Minimum space is 350 but 520 satisfies no. of contacts rule
1095 slots 80 2000 350 80 190 520
1096 calma 66 44
1097
1098#----------------------------------------------------------------
1099# NPC (Nitride poly cut)
1100# surrounds CONT (LICON) on poly only (i.e., pc)
1101#----------------------------------------------------------------
1102
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1103 # Avoids a common case of NPC bridges too close to other LICON shapes.
1104 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1105 grow 90
1106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1107 layer NPC pc
1108 squares-grid 0 170 170
1109 grow 100
1110 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1111 and-not diffcutarea
1112 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1113 grow 130
1114 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1115 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1116 calma 95 20
1117
1118 # NPC is also generated on xhrpoly and uhrpoly resistors
1119
1120 layer NPC xpc,xhrpoly,uhrpoly
1121 # xpc surrounds precision_resistor by 0.095um
1122 grow 95
1123 grow 130
1124 shrink 130
1125 calma 95 20
1126
1127#----------------------------------------------------------------
1128# Device markers
1129#----------------------------------------------------------------
1130
1131 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1132 calma 65 13
1133
1134 layer POLYRES mrp1
1135 calma 66 13
1136
1137 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1138 layer POLYSHORT rmp
1139 calma 66 15
1140
1141 # POLYRES extends to edge of contact cut
1142 layer POLYRES xhrpoly,uhrpoly
1143 grow 60
1144 and xpc
1145 or xhrpoly,uhrpoly
1146 calma 66 13
1147
1148 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1149 # To be done: Expand to include anode, cathode, and guard ring
1150 calma 81 23
1151
1152#----------------------------------------------------------------
1153# LI
1154#----------------------------------------------------------------
1155 layer LI allli
1156 calma 67 20
1157
1158 layer LITXT
1159 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1160 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1161
1162 layer LIPIN
1163 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1164 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1165
1166 layer LIRES rli
1167 labels rli
1168 calma 67 13
1169
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1170 layer LIFILL lifill
1171 labels lifill
1172 calma 56 28
1173
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1174#----------------------------------------------------------------
1175# MCON
1176#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1177 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1178 squares-grid 0 170 190
1179 calma 67 44
1180
1181#----------------------------------------------------------------
1182# MET1
1183#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1184 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1185 calma 68 20
1186
1187 layer MET1TXT
1188 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1189 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1190
1191 layer MET1PIN
1192 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1193 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1194
1195 layer MET1RES rm1
1196 labels rm1
1197 calma 68 13
1198
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1199 layer MET1FILL m1fill
1200 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1201 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1202
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1203#----------------------------------------------------------------
1204# VIA1
1205#----------------------------------------------------------------
1206 layer VIA1 via1
1207 squares-grid 55 150 170
1208 calma 68 44
1209
1210#----------------------------------------------------------------
1211# MET2
1212#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1213 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1214 calma 69 20
1215
1216 layer MET2TXT
1217 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1218 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1219
1220 layer MET2PIN
1221 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1222 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1223
1224 layer MET2RES rm2
1225 labels rm2
1226 calma 69 13
1227
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1228 layer MET2FILL m2fill
1229 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1230 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1231
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1232#----------------------------------------------------------------
1233# VIA2
1234#----------------------------------------------------------------
1235 layer VIA2 via2
1236 squares-grid 40 200 200
1237 calma 69 44
1238
1239#----------------------------------------------------------------
1240# MET3
1241#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1242 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1243 calma 70 20
1244
1245 layer MET3TXT
1246 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1247 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1248
1249 layer MET3PIN
1250 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1251 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1252
1253 layer MET3RES rm3
1254 labels rm3
1255 calma 70 13
1256
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1257 layer MET3FILL m3fill
1258 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1259 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1260
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1261#ifdef METAL5
1262#----------------------------------------------------------------
1263# VIA3
1264#----------------------------------------------------------------
1265 layer VIA3 via3
1266#ifdef MIM
1267 or mimcc
1268#endif (MIM)
1269 squares-grid 60 200 200
1270 calma 70 44
1271
1272#----------------------------------------------------------------
1273# MET4
1274#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1275 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1276 calma 71 20
1277
1278 layer MET4TXT
1279 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1280 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1281
1282 layer MET4PIN
1283 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1284 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1285
1286 layer MET4RES rm4
1287 labels rm4
1288 calma 71 13
1289
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1290 layer MET4FILL m4fill
1291 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1292 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1293
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1294#----------------------------------------------------------------
1295# VIA4
1296#----------------------------------------------------------------
1297 layer VIA4 via4
1298#ifdef MIM
1299 or mim2cc
1300#endif (MIM)
1301 squares-grid 190 800 800
1302 calma 71 44
1303
1304#----------------------------------------------------------------
1305# MET5
1306#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1307 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1308 calma 72 20
1309
1310 layer MET5TXT
1311 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1312 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1313
1314 layer MET5PIN
1315 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1316 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1317
1318 layer MET5RES rm5
1319 labels rm5
1320 calma 72 13
1321
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1322 layer MET5FILL m5fill
1323 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1324 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1325
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1326#endif (METAL5)
1327
1328#ifdef REDISTRIBUTION
1329#----------------------------------------------------------------
1330# RDL
1331#----------------------------------------------------------------
1332 layer RDL *metrdl
1333 calma 74 20
1334
1335 layer RDLTXT
1336 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1337 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1338
1339 layer RDLPIN
1340 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1341 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1342
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1343 layer PI1 *metrdl
1344 and padl,glass
1345 # Test only---needs GDS layer number
1346
1347 layer UBM *metrdl
1348 shrink 50000
1349 grow 40000
1350 # Test only---needs GDS layer number
1351
1352 layer PI2 *metrdl
1353 shrink 50000
1354 grow 25000
1355 # Test only---needs GDS layer number
1356
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1357#endif REDISTRIBUTION
1358
1359#----------------------------------------------------------------
1360# GLASS
1361#----------------------------------------------------------------
1362 layer GLASS glass
1363 calma 76 20
1364
1365#ifdef MIM
1366#----------------------------------------------------------------
1367# CAPM
1368#----------------------------------------------------------------
1369 layer CAPM *mimcap
1370 labels mimcap
1371 calma 89 44
1372
1373 layer CAPM2 *mimcap2
1374 labels mimcap2
1375 calma 97 44
1376#endif (MIM)
1377
1378#----------------------------------------------------------------
1379# Chip top level marker for DRC latchup rules to check 15um
1380# distance to taps (otherwise 6um is used)
1381#----------------------------------------------------------------
1382
1383 layer LOWTAPDENSITY
1384 bbox top
1385 # Clear 200um for pads + 50um for required high tap density
1386 # in critical area.
1387 shrink 250000
1388 calma 81 14
1389
1390#----------------------------------------------------------------
1391# FILLBLOCK
1392#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1393 layer FILLOBSFOM obsactive
1394 calma 22 24
1395
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1396 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1397 calma 62 24
1398
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1399 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1400 calma 105 52
1401
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1402 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1403 calma 107 24
1404
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1405 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1406 calma 112 4
1407
1408 render DNWELL cwell -0.1 0.1
1409 render NWELL nwell 0.0 0.2062
1410 render DIFF ndiffusion 0.2062 0.12
1411 render TAP pdiffusion 0.2062 0.12
1412 render POLY polysilicon 0.3262 0.18
1413 render CONT via 0.5062 0.43
1414 render LI metal1 0.9361 0.10
1415 render MCON via 1.0361 0.34
1416 render MET1 metal2 1.3761 0.36
1417 render VIA1 via 1.7361 0.27
1418 render MET2 metal3 2.0061 0.36
1419 render VIA2 via 2.3661 0.42
1420 render MET3 metal4 2.7861 0.845
1421#ifdef METAL5
1422 render VIA3 via 3.6311 0.39
1423 render MET4 metal5 4.0211 0.845
1424 render VIA4 via 4.8661 0.505
1425 render MET5 metal6 5.3711 1.26
1426 render CAPM metal8 2.4661 0.2
1427 render CAPM2 metal9 3.7311 0.2
1428#ifdef REDISTRIBUTION
1429 render RDL metal7 11.8834 4.0
1430#endif (!REDISTRIBUTION)
1431#endif (!METAL5)
1432
1433#----------------------------------------------------------------
1434style drc
1435#----------------------------------------------------------------
1436# NOTE: This style is used for DRC only, not for GDS output
1437#----------------------------------------------------------------
1438 scalefactor 10 nanometers
1439 options calma-permissive-labels
1440
1441 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1442 templayer dnwell_shrink dnwell
1443 shrink 1030
1444
1445 templayer nwell_missing dnwell
1446 grow 400
1447 and-not dnwell_shrink
1448 and-not nwell
1449
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1450 templayer pwell_in_dnwell dnwell
1451 and-not nwell
1452
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1453 # SONOS nFET devices must be in deep nwell
1454 templayer dnwell_missing nsonos
1455 and-not dnwell
1456
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1457 # SONOS nFET devices must be in cell with abutment box
1458 templayer abutment_box
1459 boundary
1460
1461 templayer bbox_missing nsonos
1462 and-not abutment_box
1463
1464 # Make sure nwell covers varactor poly
1465 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1466 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1467 grow 150
1468 and-not nwell
1469
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1470 # Define MiM cap bottom plate for spacing rule
1471 templayer mim_bottom
1472 bloat-all *mimcap *metal3
1473
1474 # Define MiM2 cap bottom plate for spacing rule
1475 templayer mim2_bottom
1476 bloat-all *mimcap2 *metal4
1477
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]1478 # Define areas where mim2cc is inside the boundary of mimcc
1479 # by more than the contact surround
1480 templayer mim2_contact_overlap
1481 bloat-all *mimcap2 mimcc
1482 shrink 60
1483 and-not *mimcap2
1484
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1485 # Note that metal fill is performed by the foundry and so is not
1486 # an option for a cifoutput style.
1487
1488 # Check latchup rule (15um minimum from tap LICON center to any
1489 # non-tap diffusion. Note that to count as a tap, the diffusion
1490 # must be contacted to LI
1491
1492 templayer ptap_reach psc,mvpsc
1493 and-not dnwell
1494 # grow total is 15um. grow in 0.84um increments to ensure that
1495 # no nwell ring is crossed
1496 grow 840
1497 and-not nwell,dnwell
1498 grow 840
1499 and-not nwell,dnwell
1500 grow 840
1501 and-not nwell,dnwell
1502 grow 840
1503 and-not nwell,dnwell
1504 grow 840
1505 and-not nwell,dnwell
1506 grow 840
1507 and-not nwell,dnwell
1508 grow 840
1509 and-not nwell,dnwell
1510 grow 840
1511 and-not nwell,dnwell
1512 grow 840
1513 and-not nwell,dnwell
1514 grow 840
1515 and-not nwell,dnwell
1516 grow 840
1517 and-not nwell,dnwell
1518 grow 840
1519 and-not nwell,dnwell
1520 grow 840
1521 and-not nwell,dnwell
1522 grow 840
1523 and-not nwell,dnwell
1524 grow 840
1525 and-not nwell,dnwell
1526 grow 840
1527 and-not nwell,dnwell
1528 grow 840
1529 and-not nwell,dnwell
1530 grow 635
1531 and-not nwell,dnwell
1532
1533 templayer ptap_missing *ndiff,*mvndiff
1534 and-not dnwell
1535 and-not ptap_reach
1536
1537 templayer ntap_reach nsc,mvnsc
1538 # grow total is 15um. grow in 1.27um increments to ensure that
1539 # no nwell ring is crossed. There is no difference between
1540 # ntaps in and out of deep nwell.
1541 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1542 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1543 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1544 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1545 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1546 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1547 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1548 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1549 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1550 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1551 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1552 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1553 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1554 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1555 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1556 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1557 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1558 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1559 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1560 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1561 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1562 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1563 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1564 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1565
1566 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1567 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1568 and-not ntap_reach
1569
1570 templayer dptap_reach psc,mvpsc
1571 and dnwell
1572 grow 840
1573 and-not nwell
1574 and dnwell
1575 grow 840
1576 and-not nwell
1577 and dnwell
1578 grow 840
1579 and-not nwell
1580 and dnwell
1581 grow 840
1582 and-not nwell
1583 and dnwell
1584 grow 840
1585 and-not nwell
1586 and dnwell
1587 grow 840
1588 and-not nwell
1589 and dnwell
1590 grow 840
1591 and-not nwell
1592 and dnwell
1593 grow 840
1594 and-not nwell
1595 and dnwell
1596 grow 840
1597 and-not nwell
1598 and dnwell
1599 grow 840
1600 and-not nwell
1601 and dnwell
1602 grow 840
1603 and-not nwell
1604 and dnwell
1605 grow 840
1606 and-not nwell
1607 and dnwell
1608 grow 840
1609 and-not nwell
1610 and dnwell
1611 grow 840
1612 and-not nwell
1613 and dnwell
1614 grow 840
1615 and-not nwell
1616 and dnwell
1617 grow 840
1618 and-not nwell
1619 and dnwell
1620 grow 840
1621 and-not nwell
1622 and dnwell
1623 grow 635
1624 and-not nwell
1625 and dnwell
1626
1627 templayer dptap_missing *ndiff,*mvndiff
1628 and dnwell
1629 and-not dptap_reach
1630
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1631 templayer pdiff_crosses_dnwell dnwell
1632 grow 20
1633 and-not dnwell
1634 and allpdifflv,allpdiffmv
1635
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1636 # MV nwell must be 2um from any other nwell
1637 templayer mvnwell
1638 bloat-all alldiffmv nwell
1639 grow-min 840
1640 bridge 700 600
1641
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1642 # Simple spacing checks to lvnwell must use CIF-DRC rule
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1643 # Note that HVI may *abut* lvnwell; this can only be handled
1644 # with mask-hints layers.
1645
1646 templayer drawn_hvi
1647 mask-hints HVI
1648
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1649 templayer allmvdiffnowell *mvndiff,*mvpsd
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1650 and-not drawn_hvi
1651
1652 templayer nwell_or_hvi nwell,drawn_hvi
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1653
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1654 templayer lvnwell nwell
1655 and-not mvnwell
1656
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1657 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1658 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1659
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1660 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1661 and-not nwell_with_tap
1662
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1663 templayer tap_with_licon
1664 bloat-all psc,mvpsc psd,mvpsd
1665 bloat-all nsc,mvnsc nsd,mvnsd
1666
1667 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1668 and-not tap_with_licon
1669
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1670 # Make sure varactor nwell contains no P diffusion
1671 templayer pdiff_in_varactor_well
1672 bloat-all varactor,mvvaractor nwell
1673 and allpactive
1674
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1675 # HVNTM spacing requires recreating HVNTM
1676 templayer hvntm_block *mvpsd
1677 grow 185
1678
1679 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1680 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1681 bloat-all mvvaractor *mvnsd
1682 and-not hvntm_block
1683 grow 185
1684 grow 345
1685 shrink 345
1686 and-not hvntm_block
1687
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1688 # RPM spacing checks require recreating RPM
1689 templayer rpm_generate
1690 bloat-all xhrpoly,uhrpoly xpc
1691 grow 200
1692 grow-min 1270
1693 grow 420
1694 shrink 420
1695
1696 # Check distance RPM to NSDM
1697 templayer rpm_nsd_check rpm_generate
1698 grow 325
1699 and allndifflv,allndiffmv
1700
1701 # Check distance RPM to (unrelated) POLY
1702 templayer rpm_poly_check rpm_generate
1703 grow 200
1704 and-not xhrpoly,uhrpoly,xpc
1705 and allpoly
1706
1707 # Check distance RPM to HVNTM
1708 templayer rpm_hvntm_check rpm_generate
1709 grow 385
1710 and allndiffmvnontap
1711
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1712 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1713 close 140000
1714
1715 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1716 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1717
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1718 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1719 close 140000
1720
1721 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1722 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1723
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1724 templayer m1_huge allm1
1725 shrink 1500
1726 grow 1500
1727
1728 templayer m1_large_halo m1_huge
1729 grow 280
1730 and-not m1_huge
1731 and allm1
1732
1733 templayer m2_huge allm2
1734 shrink 1500
1735 grow 1500
1736
1737 templayer m2_large_halo m2_huge
1738 grow 280
1739 and-not m2_huge
1740 and allm2
1741
1742 templayer m3_huge allm3
1743 shrink 1500
1744 grow 1500
1745
1746 templayer m3_large_halo m3_huge
1747 grow 400
1748 and-not m3_huge
1749 and allm3
1750
1751 templayer m4_huge allm4
1752 shrink 1500
1753 grow 1500
1754
1755 templayer m4_large_halo m4_huge
1756 grow 400
1757 and-not m4_huge
1758 and allm4
1759
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1760#ifdef EXPERIMENTAL
1761#----------------------------------------------------------------
1762style paint
1763#----------------------------------------------------------------
1764# NOTE: This style is used for database manipulations only via
1765# the "cif paint" command.
1766#----------------------------------------------------------------
1767
1768 scalefactor 10 nanometers
1769
1770 templayer m1grow *m1
1771 grow 290
1772
1773 # layer listrap: Use the following set of commands to strap local
1774 # interconnect wires with metal1 (inside the cursor box) to satisfy
1775 # the maximum aspect ratio rule for local interconnect:
1776 #
1777 # tech unlock *
1778 # cif ostyle paint
1779 # cif paint m1strap comment
1780 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1781 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1782 # erase comment
1783
1784 templayer m1strap *li
1785 and-not m1grow
1786 grow 30
1787
1788 templayer listrap comment
1789 slots 30 170 170 60
1790
1791#endif (EXPERIMENTAL)
1792
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1793#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1794style density
1795#----------------------------------------------------------------
1796# Style used by scripts to check for fill density
1797#----------------------------------------------------------------
1798 scalefactor 10 nanometers
1799 options calma-permissive-labels
1800 gridlimit 5
1801
1802 templayer fom_all alldiff,fomfill
1803
1804 templayer poly_all allpoly,polyfill
1805
1806 templayer li_all allli,lifill
1807
1808 templayer m1_all allm1,m1fill
1809
1810 templayer m2_all allm2,m2fill
1811
1812 templayer m3_all allm3,m3fill
1813
1814 templayer m4_all allm4,m4fill
1815
1816 templayer m5_all allm5,m5fill
1817
1818#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1819style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1820#----------------------------------------------------------------
1821# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1822# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1823#----------------------------------------------------------------
1824 scalefactor 10 nanometers
1825 options calma-permissive-labels
1826 gridlimit 5
1827
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1828#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1829# Generate and retain a layer representing the bounding box.
1830#
1831# For variant ():
1832# The bounding box is the full extent of geometry on the top level
1833# cell.
1834#
1835# For variant (tiled):
1836# Use with a script that breaks layout into flattened tiles and runs
1837# fill individually on each. The tiles should be larger than the
1838# step size, and each should draw a layer "comment" the size of the
1839# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1840#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1841
1842 variants ()
1843 templayer topbox
1844 bbox top
1845
1846 variants (tiled)
1847 templayer topbox comment
1848 # Each tile imposes the full keepout distance rule of
1849 # 3um on all sides.
1850 shrink 1500
1851
1852 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1853
1854#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1855# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1856# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1857# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1858# Enclosure by nwell = Diff/Tap 8 = 0.18um
1859#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1860
1861 templayer mvnwell
1862 bloat-all alldiffmv nwell
1863
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1864 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1865 and-not mvnwell
1866
1867 templayer well_shrink mvnwell
1868 shrink 250
1869 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1870 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1871 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1872 grow 340
1873 and-not well_shrink
1874
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1875#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1876# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1877#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1878 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1879 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1880 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1881 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1882
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1883 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1884 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1885 grow 1000
1886
1887#---------------------------------------------------
1888# FOM and POLY fill
1889#---------------------------------------------------
1890 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1891 # slots 0 4080 1320 0 4080 1320 1360 0
1892 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1893 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1894 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1895 shrink 2035
1896 grow 2035
1897
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1898#---------------------------------------------------
1899
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1900 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1901 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1902 or obstruct_poly
1903 templayer polyfill_pass1 topbox
1904 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1905 and-not obstruct_poly_pass1
1906 and topbox
1907 shrink 355
1908 grow 355
1909
1910#---------------------------------------------------
1911
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1912 templayer obstruct_fom_pass2 fomfill_pass1
1913 grow 1290
1914 or polyfill_pass1
1915 grow 300
1916 or obstruct_fom
1917 templayer fomfill_pass2 topbox
1918 slots 0 2500 1320 0 2500 1320 1360 0
1919 and-not obstruct_fom_pass2
1920 and topbox
1921 shrink 1245
1922 grow 1245
1923
1924#---------------------------------------------------
1925
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1926 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1927 grow 60
1928 or fomfill_pass1,fomfill_pass2
1929 grow 300
1930 or obstruct_poly
1931 templayer polyfill_coarse topbox
1932 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1933 and-not obstruct_poly_coarse
1934 and topbox
1935 shrink 355
1936 grow 355
1937
1938#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1939 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1940 grow 60
1941 or fomfill_pass1,fomfill_pass2
1942 grow 300
1943 or obstruct_poly
1944 templayer polyfill_medium topbox
1945 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1946 and-not obstruct_poly_medium
1947 and topbox
1948 shrink 265
1949 grow 265
1950
1951#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1952 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1953 grow 60
1954 or fomfill_pass1,fomfill_pass2
1955 grow 300
1956 or obstruct_poly
1957 templayer polyfill_fine topbox
1958 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1959 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1960 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1961 shrink 235
1962 grow 235
1963
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1964#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1965
1966 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1967 grow 1290
1968 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1969 grow 300
1970 or obstruct_fom
1971 templayer fomfill_coarse topbox
1972 slots 0 1500 1320 0 1500 1320 1360 0
1973 and-not obstruct_fom_coarse
1974 and topbox
1975 shrink 745
1976 grow 745
1977
1978#---------------------------------------------------
1979
1980 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1981 grow 1290
1982 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1983 grow 300
1984 or obstruct_fom
1985 templayer fomfill_fine topbox
1986 slots 0 500 400 0 500 400 160 0
1987 and-not obstruct_fom_fine
1988 and topbox
1989 shrink 245
1990 grow 245
1991
1992#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1993 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1994 or fomfill_pass2
1995 or fomfill_coarse
1996 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1997 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1998
1999 layer POLYFILL polyfill_pass1
2000 or polyfill_coarse
2001 or polyfill_medium
2002 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2003 calma 28 28
2004
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2005#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2006# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2007# Note requirement that LI fill may not overlap (non-fill)
2008# diff or poly.
2009#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2010
2011 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2012 grow 2800
2013 or alldiff,allpoly
2014 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2015 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]2016 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]2017 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2018 and-not obstruct_li_coarse
2019 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2020 shrink 1495
2021 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2022
2023 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2024 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2025 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2026 grow 300
2027 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2028 grow 200
2029 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2030 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2031 and-not obstruct_li_medium
2032 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2033 shrink 745
2034 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2035
2036 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2037 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2038 grow 300
2039 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2040 grow 200
2041 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2042 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2043 and-not obstruct_li_fine
2044 and topbox
2045 shrink 285
2046 grow 285
2047
2048 layer LIFILL lifill_coarse
2049 or lifill_medium
2050 or lifill_fine
2051 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2052
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2053#---------------------------------------------------
2054# MET1 fill
2055#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2056
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2057 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2058 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2059 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2060 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2061 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2062 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2063 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2064 shrink 995
2065 grow 995
2066
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2067 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2068 grow 2800
2069 or met1fill_coarse
2070 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2071 templayer met1fill_medium topbox
2072 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2073 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2074 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2075 shrink 495
2076 grow 495
2077
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2078 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2079 grow 300
2080 or met1fill_coarse,met1fill_medium
2081 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2082 templayer met1fill_fine topbox
2083 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2084 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2085 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2086 shrink 285
2087 grow 285
2088
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2089 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2090 grow 100
2091 or met1fill_coarse,met1fill_medium,met1fill_fine
2092 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2093 templayer met1fill_veryfine topbox
2094 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2095 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2096 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2097 shrink 145
2098 grow 145
2099
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2100 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2101 or met1fill_medium
2102 or met1fill_fine
2103 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2104 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2105
2106#---------------------------------------------------
2107# MET2 fill
2108#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2109 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2110 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2111 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2112 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2113 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2114 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2115 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2116 shrink 995
2117 grow 995
2118
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2119 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2120 grow 2800
2121 or met2fill_coarse
2122 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2123 templayer met2fill_medium topbox
2124 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2125 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2126 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2127 shrink 495
2128 grow 495
2129
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2130 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2131 grow 300
2132 or met2fill_coarse,met2fill_medium
2133 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2134 templayer met2fill_fine topbox
2135 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2136 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2137 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2138 shrink 285
2139 grow 285
2140
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2141 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2142 grow 100
2143 or met2fill_coarse,met2fill_medium,met2fill_fine
2144 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2145 templayer met2fill_veryfine topbox
2146 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2147 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2148 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2149 shrink 145
2150 grow 145
2151
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2152 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2153 or met2fill_medium
2154 or met2fill_fine
2155 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2156 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2157
2158#---------------------------------------------------
2159# MET3 fill
2160#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2161 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2162 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2163 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2164 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2165 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2166 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2167 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2168 shrink 995
2169 grow 995
2170
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2171 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2172 grow 2700
2173 or met3fill_coarse
2174 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2175 templayer met3fill_medium topbox
2176 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2177 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2178 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2179 shrink 495
2180 grow 495
2181
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2182 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2183 grow 200
2184 or met3fill_coarse,met3fill_medium
2185 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2186 templayer met3fill_fine topbox
2187 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2188 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2189 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2190 shrink 285
2191 grow 285
2192
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2193 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2194 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2195 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2196 or met3fill_coarse,met3fill_medium,met3fill_fine
2197 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2198 templayer met3fill_veryfine topbox
2199 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2200 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2201 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2202 shrink 195
2203 grow 195
2204
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2205 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2206 or met3fill_medium
2207 or met3fill_fine
2208 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2209 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2210
2211#ifdef METAL5
2212#---------------------------------------------------
2213# MET4 fill
2214#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2215 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2216 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2217 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2218 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2219 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2220 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2221 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2222 shrink 995
2223 grow 995
2224
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2225 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2226 grow 2700
2227 or met4fill_coarse
2228 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2229 templayer met4fill_medium topbox
2230 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2231 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2232 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2233 shrink 495
2234 grow 495
2235
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2236 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2237 grow 200
2238 or met4fill_coarse,met4fill_medium
2239 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2240 templayer met4fill_fine topbox
2241 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2242 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2243 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2244 shrink 285
2245 grow 285
2246
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2247 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2248 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2249 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2250 or met4fill_coarse,met4fill_medium,met4fill_fine
2251 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2252 templayer met4fill_veryfine topbox
2253 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2254 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2255 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2256 shrink 195
2257 grow 195
2258
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2259 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2260 or met4fill_medium
2261 or met4fill_fine
2262 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2263 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2264
2265#---------------------------------------------------
2266# MET5 fill
2267#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2268 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2269 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2270 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2271 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2272 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2273 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2274 shrink 2495
2275 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2276
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2277 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2278 grow 1400
2279 or met5fill_coarse
2280 grow 1600
2281 templayer met5fill_medium topbox
2282 slots 0 3000 1600 0 3000 1600 1000 100
2283 and-not obstruct_m5_medium
2284 and topbox
2285 shrink 1495
2286 grow 1495
2287
2288 layer MET5FILL met5fill_coarse
2289 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2290 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2291#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2292
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2293end
2294
2295#-----------------------------------------------------------------------
2296cifinput
2297#-----------------------------------------------------------------------
2298# NOTE: All values in this section MUST be multiples of 25
2299# or else magic will scale below the allowed layout grid size
2300#-----------------------------------------------------------------------
2301
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2302style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2303 scalefactor 10 nanometers
2304 gridlimit 5
2305
2306 options ignore-unknown-layer-labels no-reconnect-labels
2307
2308#ifndef MIM
2309 ignore CAPM
2310 ignore CAPM2
2311#endif (!MIM)
2312#ifndef METAL5
2313 ignore MET4,VIA3
2314 ignore MET5,VIA4
2315#endif
2316 ignore NPC
2317 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2318 ignore CAPID
2319 ignore LDNTM
2320 ignore HVNTM
2321 ignore POLYMOD
2322 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2323 ignore FILLOBSPOLY
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2324 ignore OUTLINE
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2325
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2326 layer pnp NWELL,WELLTXT,WELLPIN
2327 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2328 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2329 variants (vendor)
2330 labels WELLTXT port
2331 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2332 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2333 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2334 labels WELLPIN port
2335
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2336 layer nwell NWELL,WELLTXT,WELLPIN
2337 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2338 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2339 variants (vendor)
2340 labels WELLTXT port
2341 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2342 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2343 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2344 labels WELLPIN port
2345
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2346 templayer nwellarea NWELL
2347 copyup nwelcheck
2348
2349 # Copy nwell areas up for diffusion checks
2350 templayer xnwelcheck nwelcheck
2351 copyup nwelcheck
2352
2353 templayer hvarea HVI
2354 copyup hvcheck
2355
2356 # Copy high-voltage (HVI) areas up for diffusion checks
2357 templayer xhvcheck hvcheck
2358 copyup hvcheck
2359
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2360 # Always draw pwell under p-tap and n-diff. This is not always
2361 # necessary but works better with deep nwell for correct extraction.
2362 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2363 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2364 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2365 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2366 grow 420
2367 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2368 variants (vendor)
2369 labels SUBTXT port
2370 variants ()
2371 labels SUBTXT text
2372 variants *
2373 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2374
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2375 layer dnwell DNWELL
2376 labels DNWELL
2377
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]2378 layer isosub SUBCUT
2379 labels SUBCUT
2380
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2381 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2382 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2383 and NPNID
2384
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2385 layer rpw PWRES
2386 and DNWELL
2387 labels PWRES
2388
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2389 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2390 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2391 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2392 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2393 and-not DIODE
2394 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2395 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2396 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2397 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2398 copyup ndifcheck
2399 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2400 variants (vendor)
2401 labels DIFFTXT port
2402 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2403 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2404 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2405 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2406
2407 layer ndiff ndiffarea
2408
2409 # Copy ndiff areas up for contact checks
2410 templayer xndifcheck ndifcheck
2411 copyup ndifcheck
2412
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2413 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2414 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2415 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2416 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2417 and-not DIODE
2418 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2419 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2420 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2421 copyup ndifcheck
2422 labels DIFF
2423 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2424 variants (vendor)
2425 labels DIFFTXT port
2426 variants ()
2427 labels DIFFTXT text
2428 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2429 labels DIFFPIN port
2430
2431 layer mvndiff mvndiffarea
2432
2433 # Copy ndiff areas up for contact checks
2434 templayer mvxndifcheck mvndifcheck
2435 copyup mvndifcheck
2436
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2437 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2438 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2439 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2440 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2441 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2442 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2443 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2444 and-not LVTN
2445 labels DIFF
2446
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2447 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2448 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2449 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2450 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2451 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2452 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2453 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2454 and LVTN
2455 labels DIFF
2456
2457 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2458 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2459 and-not HVI,hvcheck
2460 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2461 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2462
2463 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2464 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2465 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2466 labels DIFF
2467
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2468 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2469 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2470 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2471 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2472 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2473 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2474 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2475 copyup pdifcheck
2476 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2477 variants (vendor)
2478 labels DIFFTXT port
2479 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2480 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2481 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2482 labels DIFFPIN port
2483
2484 layer pdiff pdiffarea
2485
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2486 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2487 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2488 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2489 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2490 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2491 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2492 and-not LVTN
2493 labels DIFF
2494
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2495 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2496 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2497 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2498 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2499 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2500 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2501 and LVTN
2502 labels DIFF
2503
2504 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2505 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2506 and HVI,hvcheck
2507 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2508 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2509
2510 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2511 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2512 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2513 labels DIFF
2514
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2515 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2516 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2517 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2518 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2519 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2520 and-not DIODE
2521 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2522 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2523 copyup mvpdifcheck
2524 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2525 variants (vendor)
2526 labels DIFFTXT port
2527 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2528 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2529 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2530 labels DIFFPIN port
2531
2532 layer mvpdiff mvpdiffarea
2533
2534 # Copy pdiff areas up for contact checks
2535 templayer xpdifcheck pdifcheck
2536 copyup pdifcheck
2537
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2538 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2539 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2540 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2541 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2542 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2543 and-not LVTN
2544 and-not HVTP
2545 and DIODE
2546 labels DIFF
2547
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2548 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2549 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2550 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2551 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2552 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2553 and LVTN
2554 and-not HVTP
2555 and DIODE
2556 labels DIFF
2557
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2558 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2559 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2560 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2561 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2562 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2563 and-not LVTN
2564 and HVTP
2565 and DIODE
2566 labels DIFF
2567
2568 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2569 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2570 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2571 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2572
2573 # Define pfet areas as known pdiff, regardless of the presence of a well.
2574
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2575 templayer pfetarea DIFF,barediff
2576 and POLY
2577 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2578 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2579 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2580
2581 layer pfet pfetarea
2582 and-not LVTN
2583 and-not HVTP
2584 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2585 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2586 labels DIFF
2587
2588 layer scpfet pfetarea
2589 and-not LVTN
2590 and-not HVTP
2591 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2592 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2593 labels DIFF
2594
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2595 layer scpfethvt pfetarea
2596 and-not LVTN
2597 and HVTP
2598 and STDCELL
2599 labels DIFF
2600
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2601 layer ppu pfetarea
2602 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2603 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2604 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2605 # Shrink-grow operation eliminates the smaller parasitie device
2606 # shrink 70
2607 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2608 labels DIFF
2609
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2610 layer pfetlvt pfetarea
2611 and LVTN
2612 labels DIFF
2613
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2614 layer pfetmvt pfetarea
2615 and HVTR
2616 labels DIFF
2617
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2618 layer pfethvt pfetarea
2619 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2620 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2621 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2622 labels DIFF
2623
2624 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2625 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2626 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2627 grow 180
2628
2629 # Copy mvpdiff areas up for contact checks
2630 templayer mvxpdifcheck mvpdifcheck
2631 copyup mvpdifcheck
2632
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2633 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2634 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2635 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2636 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2637 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2638 and DIODE
2639 labels DIFF
2640
2641 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2642 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2643 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2644 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2645
2646 # Define pfet areas as known pdiff,
2647 # regardless of the presence of a
2648 # well.
2649
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2650 templayer mvpfetarea DIFF,barediff
2651 and POLY
2652 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2653 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2654 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2655
2656 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2657 and-not ESDID
2658 labels DIFF
2659
2660 layer mvpfetesd mvpfetarea
2661 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2662 labels DIFF
2663
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2664 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2665 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2666 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2667 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2668 and-not DIODE
2669 and-not DIFFRES
2670 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2671 variants (vendor)
2672 labels DIFFTXT port
2673 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2674 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2675 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2676 labels DIFFPIN port
2677
2678 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2679 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2680 and NWELL,nwelcheck
2681 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2682 labels DIFF
2683
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2684 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2685 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2686 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2687 and-not PSDM
2688 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2689 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2690 and-not LVTN
2691 and-not SONOS
2692 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2693 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2694 labels DIFF
2695
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2696 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2697 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2698 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2699 and-not PSDM
2700 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2701 and-not NWELL,nwelcheck
2702 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2703 and-not LVTN
2704 and-not SONOS
2705 and STDCELL
2706 labels DIFF
2707
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2708 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2709 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2710 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2711 and-not PSDM
2712 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2713 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2714 and COREID
2715 labels DIFF
2716
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2717 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2718 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2719 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2720 and-not PSDM
2721 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2722 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2723 and COREID
2724 # Shrink-grow operation eliminates the smaller npass device
2725 shrink 70
2726 grow 70
2727 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2728
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2729 # Devices abutting tap under gate are officially npd, not npass
2730 layer npd TAP
2731 grow 100
2732 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2733 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2734 and-not PSDM
2735 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2736 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2737 and COREID
2738 labels DIFF
2739
2740 layer nfetlvt DIFF,barediff
2741 and POLY
2742 or baretrans
2743 and-not PSDM
2744 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2745 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2746 and LVTN
2747 and-not SONOS
2748 labels DIFF
2749
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2750 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2751 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2752 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2753 and-not PSDM
2754 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2755 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2756 and LVTN
2757 and SONOS
2758 labels DIFF
2759
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2760 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2761 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2762 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2763 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2764 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2765 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2766 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2767 copyup nsubcheck
2768
2769 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2770 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2771
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2772 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2773 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2774 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2775 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2776 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2777 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2778
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2779 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2780 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2781 and POLY
2782 and COREID
2783 labels TAP
2784
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2785 templayer nsdexpand nsdarea
2786 grow 500
2787
2788 # Copy nsub areas up for contact checks
2789 templayer xnsubcheck nsubcheck
2790 copyup nsubcheck
2791
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2792 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2793 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2794 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2795 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2796 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2797 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2798 and-not pfetexpand
2799 copyup psubcheck
2800
2801 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2802 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2803
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2804 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2805 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2806 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2807 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2809 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2810
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2811 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2812 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2813 and POLY
2814 and COREID
2815 labels TAP
2816
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2817 templayer psdexpand psdarea
2818 grow 500
2819
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2820 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2821 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2822 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2823 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2824 and mvpfetexpand
2825 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2826 variants (vendor)
2827 labels DIFFTXT port
2828 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2829 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2830 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2831 labels DIFFPIN port
2832
2833 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2834 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2835 and NWELL,nwelcheck
2836 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2837 and-not mvrdpioedge
2838 labels DIFF
2839
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2840 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2841 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2842 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2843 and-not PSDM
2844 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2845 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2846 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2847 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2848
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2849 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2850 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2851 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2852 and-not PSDM
2853 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2854 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2855 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2856 and-not mvnfetarea
2857
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2858 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2859 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2860 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2861 and-not PSDM
2862 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2863 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2864 and ESDID
2865 and-not mvnnfetarea
2866 labels DIFF
2867
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2868 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2869 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2870 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2871 and-not PSDM
2872 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2873 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2874 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2875 and-not mvnnfetarea
2876 labels DIFF
2877
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2878 layer nnfet mvnnfetarea
2879 and LVID
2880 labels DIFF
2881
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2882 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2883 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2884 labels DIFF
2885
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2886 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2887 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2888 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2889 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2890 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2891 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2892 copyup mvnsubcheck
2893
2894 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2895 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2896
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2897 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2898 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2899 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2900 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2901 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2902
2903 templayer mvnsdexpand mvnsdarea
2904 grow 500
2905
2906 # Copy nsub areas up for contact checks
2907 templayer mvxnsubcheck mvnsubcheck
2908 copyup mvnsubcheck
2909
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2910 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2911 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2912 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2913 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2914 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2915 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2916 and-not mvpfetexpand
2917 copyup mvpsubcheck
2918
2919 layer mvpsd mvpsdarea
2920 labels DIFF
2921
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2922 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2923 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2924 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2925 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2926 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2927
2928 templayer mvpsdexpand mvpsdarea
2929 grow 500
2930
2931 # Copy psub areas up for contact checks
2932 templayer xpsubcheck psubcheck
2933 copyup psubcheck
2934
2935 templayer mvxpsubcheck mvpsubcheck
2936 copyup mvpsubcheck
2937
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2938 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2939 and-not PSDM
2940 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2941 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2942 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2943 and-not pfetexpand
2944 and psdexpand
2945
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2946 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2947 and-not PSDM
2948 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2949 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2950 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2951 and nsdexpand
2952
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2953 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2954 and-not PSDM
2955 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2956 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2957 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2958 and-not mvpfetexpand
2959 and mvpsdexpand
2960
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2961 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2962 and-not PSDM
2963 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2964 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2965 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2966 and mvnsdexpand
2967
2968 templayer hresarea POLY
2969 and RPM
2970 grow 3000
2971
2972 templayer uresarea POLY
2973 and URPM
2974 grow 3000
2975
2976 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2977 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2978 grow 3000
2979
2980 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2981 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2982 grow 3000
2983
2984 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2985
2986 layer pfet POLY
2987 and DIFF
2988 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2989 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2990 and-not STDCELL
2991
2992 layer scpfet POLY
2993 and DIFF
2994 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2995 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2996 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2997 and STDCELL
2998
2999 layer scpfethvt POLY
3000 and DIFF
3001 and diffresarea
3002 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3003 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3004 and STDCELL
3005
3006 templayer xpolyterm RPM,URPM
3007 and POLY
3008 and-not POLYRES
3009 # add back the 0.06um contact surround in the direction of the resistor
3010 grow 60
3011 and POLY
3012
3013 layer xpc xpolyterm
3014
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3015 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3016 and-not POLYRES
3017 and-not POLYSHORT
3018 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3019 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3020 and-not RPM
3021 and-not URPM
3022 copyup polycheck
3023
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3024 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3025 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3026 variants (vendor)
3027 labels POLYTXT port
3028 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3029 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3030 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3031 labels POLYPIN port
3032
3033 # Copy (non-resistor) poly areas up for contact checks
3034 templayer xpolycheck polycheck
3035 copyup polycheck
3036
3037 layer mrp1 POLY
3038 and POLYRES
3039 and-not RPM
3040 and-not URPM
3041 labels POLY
3042
3043 layer rmp POLY
3044 and POLYSHORT
3045 labels POLY
3046
3047 layer xhrpoly POLY
3048 and POLYRES
3049 and RPM
3050 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3051 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3052 and NPC
3053 and-not xpolyterm
3054 labels POLY
3055
3056 layer uhrpoly POLY
3057 and POLYRES
3058 and URPM
3059 and-not RPM
3060 and NPC
3061 and-not xpolyterm
3062 labels POLY
3063
3064 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3065 or barecont
3066 and LI
3067 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3068 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3069 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3070 and-not NWELL,nwelcheck
3071 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3072
3073 layer ndc ndcbase
3074 grow 85
3075 shrink 85
3076 shrink 85
3077 grow 85
3078 or ndcbase
3079 labels CONT
3080
3081 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3082 or barecont
3083 and LI
3084 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3085 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3086 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3087 and NWELL,nwelcheck
3088 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3089
3090 layer nsc nscbase
3091 grow 85
3092 shrink 85
3093 shrink 85
3094 grow 85
3095 or nscbase
3096 labels CONT
3097
3098 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3099 or barecont
3100 and LI
3101 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3102 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3103 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3104 and NWELL,nwelcheck
3105 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3106
3107 layer pdc pdcbase
3108 grow 85
3109 shrink 85
3110 shrink 85
3111 grow 85
3112 or pdcbase
3113 labels CONT
3114
3115 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3116 or barecont
3117 and LI
3118 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3119 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3120 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3121 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3122 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3123
3124 layer pdc pdcnowell
3125 grow 85
3126 shrink 85
3127 shrink 85
3128 grow 85
3129 or pdcnowell
3130 labels CONT
3131
3132 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3133 or barecont
3134 and LI
3135 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3136 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3137 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3138 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3139 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3140 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3141
3142 layer psc pscbase
3143 grow 85
3144 shrink 85
3145 shrink 85
3146 grow 85
3147 or pscbase
3148 labels CONT
3149
3150 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3151 or barecont
3152 and LI
3153 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3154 and POLY
3155 and-not DIFF
3156 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3157
3158 layer pc pcbase
3159 grow 85
3160 shrink 85
3161 shrink 85
3162 grow 85
3163 or pcbase
3164 labels CONT
3165
3166 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3167 or barecont
3168 and LI
3169 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3170 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3171 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3172 and DIODE
3173 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3174 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3175 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3176 and-not LVTN
3177
3178 layer ndic ndicbase
3179 grow 85
3180 shrink 85
3181 shrink 85
3182 grow 85
3183 or ndicbase
3184 labels CONT
3185
3186 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3187 or barecont
3188 and LI
3189 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3190 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3191 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3192 and DIODE
3193 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3194 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3195 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3196 and LVTN
3197
3198 layer ndilvtc ndilvtcbase
3199 grow 85
3200 shrink 85
3201 shrink 85
3202 grow 85
3203 or ndilvtcbase
3204 labels CONT
3205
3206 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3207 or barecont
3208 and LI
3209 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3210 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3211 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3212 and DIODE
3213 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3214 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3215 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3216 and-not LVTN
3217 and-not HVTP
3218
3219 layer pdic pdicbase
3220 grow 85
3221 shrink 85
3222 shrink 85
3223 grow 85
3224 or pdicbase
3225 labels CONT
3226
3227 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3228 or barecont
3229 and LI
3230 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3231 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3232 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3233 and DIODE
3234 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3235 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3236 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3237 and LVTN
3238 and-not HVTP
3239
3240 layer pdilvtc pdilvtcbase
3241 grow 85
3242 shrink 85
3243 shrink 85
3244 grow 85
3245 or pdilvtcbase
3246 labels CONT
3247
3248 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3249 or barecont
3250 and LI
3251 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3252 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3253 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3254 and DIODE
3255 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3256 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3257 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3258 and-not LVTN
3259 and HVTP
3260
3261 layer pdihvtc pdihvtcbase
3262 grow 85
3263 shrink 85
3264 shrink 85
3265 grow 85
3266 or pdihvtcbase
3267 labels CONT
3268
3269 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3270 or barecont
3271 and LI
3272 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3273 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3274 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3275 and-not NWELL,nwelcheck
3276 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3277
3278 layer mvndc mvndcbase
3279 grow 85
3280 shrink 85
3281 shrink 85
3282 grow 85
3283 or mvndcbase
3284 labels CONT
3285
3286 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3287 or barecont
3288 and LI
3289 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3290 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3291 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3292 and NWELL,nwelcheck
3293 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3294
3295 layer mvnsc mvnscbase
3296 grow 85
3297 shrink 85
3298 shrink 85
3299 grow 85
3300 or mvnscbase
3301 labels CONT
3302
3303 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3304 or barecont
3305 and LI
3306 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3307 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3308 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3309 and NWELL,nwelcheck
3310 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3311
3312 layer mvpdc mvpdcbase
3313 grow 85
3314 shrink 85
3315 shrink 85
3316 grow 85
3317 or mvpdcbase
3318 labels CONT
3319
3320 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3321 or barecont
3322 and LI
3323 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3324 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3325 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3326 and mvpfetexpand
3327 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3328 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3329
3330 layer mvpdc mvpdcnowell
3331 grow 85
3332 shrink 85
3333 shrink 85
3334 grow 85
3335 or mvpdcnowell
3336 labels CONT
3337
3338 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3339 or barecont
3340 and LI
3341 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3342 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3343 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3344 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3345 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3346 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3347
3348 layer mvpsc mvpscbase
3349 grow 85
3350 shrink 85
3351 shrink 85
3352 grow 85
3353 or mvpscbase
3354 labels CONT
3355
3356 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3357 or barecont
3358 and LI
3359 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3360 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3361 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3362 and DIODE
3363 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3364 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3365 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3366 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3367
3368 layer mvndic mvndicbase
3369 grow 85
3370 shrink 85
3371 shrink 85
3372 grow 85
3373 or mvndicbase
3374 labels CONT
3375
3376 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3377 or barecont
3378 and LI
3379 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3380 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3381 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3382 and DIODE
3383 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3384 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3385 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3386 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3387
3388 layer nndic nndicbase
3389 grow 85
3390 shrink 85
3391 shrink 85
3392 grow 85
3393 or nndicbase
3394 labels CONT
3395
3396 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3397 or barecont
3398 and LI
3399 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3400 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3401 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3402 and DIODE
3403 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3404 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3405 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3406
3407 layer mvpdic mvpdicbase
3408 grow 85
3409 shrink 85
3410 shrink 85
3411 grow 85
3412 or mvpdicbase
3413 labels CONT
3414
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3415 layer fomfill FOMFILL
3416 labels FOMFILL
3417
3418 layer polyfill POLYFILL
3419 labels POLYFILL
3420
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3421 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3422 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3423 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3424 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3425 variants (vendor)
3426 labels LITXT port
3427 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3428 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3429 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3430 labels LIPIN port
3431
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3432 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3433 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3434 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3435 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3436 variants (vendor)
3437 labels LITXT port
3438 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3439 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3440 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3441 labels LIPIN port
3442
3443 layer rli LI
3444 and LIRES,LISHORT
3445 labels LIRES,LISHORT
3446
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3447 layer lifill LIFILL
3448 labels LIFILL
3449
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3450 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3451 grow 95
3452 shrink 95
3453 shrink 85
3454 grow 85
3455 or MCON
3456 labels MCON
3457
3458 layer m1 MET1,MET1TXT,MET1PIN
3459 and-not MET1RES,MET1SHORT
3460 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3461 variants (vendor)
3462 labels MET1TXT port
3463 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3464 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3465 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3466 labels MET1PIN port
3467
3468 layer rm1 MET1
3469 and MET1RES,MET1SHORT
3470 labels MET1RES,MET1SHORT
3471
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3472 layer m1fill MET1FILL
3473 labels MET1FILL
3474
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3475#ifdef MIM
3476 layer mimcap MET3
3477 and CAPM
3478 labels CAPM
3479
3480 layer mimcc VIA3
3481 and CAPM
3482 grow 60
3483 grow 40
3484 shrink 40
3485 labels CAPM
3486
3487 layer mimcap2 MET4
3488 and CAPM2
3489 labels CAPM2
3490
3491 layer mim2cc VIA4
3492 and CAPM2
3493 grow 190
3494 grow 210
3495 shrink 210
3496 labels CAPM2
3497
3498#endif (MIM)
3499
3500 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3501 and-not COREID
3502 grow 5
3503 or VIA1
3504 grow 50
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3505
3506 layer m2c m2cbase
3507 grow 30
3508 shrink 30
3509 shrink 130
3510 grow 130
3511 or m2cbase
3512
3513 layer m2 MET2,MET2TXT,MET2PIN
3514 and-not MET2RES,MET2SHORT
3515 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3516 variants (vendor)
3517 labels MET2TXT port
3518 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3519 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3520 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3521 labels MET2PIN port
3522
3523 layer rm2 MET2
3524 and MET2RES,MET2SHORT
3525 labels MET2RES,MET2SHORT
3526
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3527 layer m2fill MET2FILL
3528 labels MET2FILL
3529
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3530 templayer m3cbase VIA2
3531 grow 40
3532
3533 layer m3c m3cbase
3534 grow 60
3535 shrink 60
3536 shrink 140
3537 grow 140
3538 or m3cbase
3539
3540 layer m3 MET3,MET3TXT,MET3PIN
3541 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3542 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3543 variants (vendor)
3544 labels MET3TXT port
3545 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3546 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3547 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3548 labels MET3PIN port
3549
3550 layer rm3 MET3
3551 and MET3RES,MET3SHORT
3552 labels MET3RES,MET3SHORT
3553
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3554 layer m3fill MET3FILL
3555 labels MET3FILL
3556
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3557#ifdef (METAL5)
3558
3559 templayer via3base VIA3
3560#ifdef MIM
3561 and-not CAPM
3562#endif (MIM)
3563 grow 60
3564
3565 layer via3 via3base
3566 grow 40
3567 shrink 40
3568 shrink 160
3569 grow 160
3570 or via3base
3571
3572 layer m4 MET4,MET4TXT,MET4PIN
3573 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3574 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3575 variants (vendor)
3576 labels MET4TXT port
3577 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3578 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3579 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3580 labels MET4PIN port
3581
3582 layer rm4 MET4
3583 and MET4RES,MET4SHORT
3584 labels MET4RES,MET4SHORT
3585
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3586 layer m4fill MET4FILL
3587 labels MET4FILL
3588
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3589 layer m5 MET5,MET5TXT,MET5PIN
3590 and-not MET5RES,MET5SHORT
3591 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3592 variants (vendor)
3593 labels MET5TXT port
3594 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3595 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3596 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3597 labels MET5PIN port
3598
3599 layer rm5 MET5
3600 and MET5RES,MET5SHORT
3601 labels MET5RES,MET5SHORT
3602
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3603 layer m5fill MET5FILL
3604 labels MET5FILL
3605
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3606 templayer via4base VIA4
3607#ifdef MIM
3608 and-not CAPM2
3609#endif (MIM)
3610 grow 190
3611
3612 layer via4 via4base
3613 grow 210
3614 shrink 210
3615 shrink 590
3616 grow 590
3617 or via4base
3618#endif (METAL5)
3619
3620#ifdef REDISTRIBUTION
3621 layer metrdl RDL,RDLTXT,RDLPIN
3622 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3623 variants (vendor)
3624 labels RDLTXT port
3625 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3626 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3627 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3628 labels RDLPIN port
3629#endif
3630
3631 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3632 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3633 # the next layer up
3634
3635 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3636 and-not PSDM
3637 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3638 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3639 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3640
3641 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3642 and-not PSDM
3643 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3644 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3645 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3646 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3647
3648 # Handle contacts found by copyup
3649
3650 templayer ndiccopy CONT
3651 and LI
3652 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3653 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3654 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3655
3656 layer ndic ndiccopy
3657 grow 85
3658 shrink 85
3659 shrink 85
3660 grow 85
3661 or ndiccopy
3662 labels CONT
3663
3664 templayer mvndiccopy CONT
3665 and LI
3666 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3667 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3668 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3669
3670 layer mvndic mvndiccopy
3671 grow 85
3672 shrink 85
3673 shrink 85
3674 grow 85
3675 or mvndiccopy
3676 labels CONT
3677
3678 templayer pdiccopy CONT
3679 and LI
3680 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3681 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3682 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3683
3684 layer pdic pdiccopy
3685 grow 85
3686 shrink 85
3687 shrink 85
3688 grow 85
3689 or pdiccopy
3690 labels CONT
3691
3692 templayer mvpdiccopy CONT
3693 and LI
3694 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3695 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3696 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3697
3698 layer mvpdic mvpdiccopy
3699 grow 85
3700 shrink 85
3701 shrink 85
3702 grow 85
3703 or mvpdiccopy
3704 labels CONT
3705
3706 templayer ndccopy CONT
3707 and ndifcheck
3708
3709 layer ndc ndccopy
3710 grow 85
3711 shrink 85
3712 shrink 85
3713 grow 85
3714 or ndccopy
3715 labels CONT
3716
3717 templayer mvndccopy CONT
3718 and mvndifcheck
3719
3720 layer mvndc mvndccopy
3721 grow 85
3722 shrink 85
3723 shrink 85
3724 grow 85
3725 or mvndccopy
3726 labels CONT
3727
3728 templayer pdccopy CONT
3729 and pdifcheck
3730
3731 layer pdc pdccopy
3732 grow 85
3733 shrink 85
3734 shrink 85
3735 grow 85
3736 or pdccopy
3737 labels CONT
3738
3739 templayer mvpdccopy CONT
3740 and mvpdifcheck
3741
3742 layer mvpdc mvpdccopy
3743 grow 85
3744 shrink 85
3745 shrink 85
3746 grow 85
3747 or mvpdccopy
3748 labels CONT
3749
3750 templayer pccopy CONT
3751 and polycheck
3752
3753 layer pc pccopy
3754 grow 85
3755 shrink 85
3756 shrink 85
3757 grow 85
3758 or pccopy
3759 labels CONT
3760
3761 templayer nsccopy CONT
3762 and nsubcheck
3763
3764 layer nsc nsccopy
3765 grow 85
3766 shrink 85
3767 shrink 85
3768 grow 85
3769 or nsccopy
3770 labels CONT
3771
3772 templayer mvnsccopy CONT
3773 and mvnsubcheck
3774
3775 layer mvnsc mvnsccopy
3776 grow 85
3777 shrink 85
3778 shrink 85
3779 grow 85
3780 or mvnsccopy
3781 labels CONT
3782
3783 templayer psccopy CONT
3784 and psubcheck
3785
3786 layer psc psccopy
3787 grow 85
3788 shrink 85
3789 shrink 85
3790 grow 85
3791 or psccopy
3792 labels CONT
3793
3794 templayer mvpsccopy CONT
3795 and mvpsubcheck
3796
3797 layer mvpsc mvpsccopy
3798 grow 85
3799 shrink 85
3800 shrink 85
3801 grow 85
3802 or mvpsccopy
3803 labels CONT
3804
3805 # Find contacts not covered in
3806 # metal and pull them into the
3807 # next layer up
3808
3809 templayer gencont CONT
3810 and LI
3811 and-not DIFF,TAP
3812 and-not POLY
3813 and-not DIODE
3814 and-not nsubcheck
3815 and-not psubcheck
3816 and-not mvnsubcheck
3817 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3818 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3819 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3820
3821 templayer barecont CONT
3822 and-not LI
3823 and-not nsubcheck
3824 and-not psubcheck
3825 and-not mvnsubcheck
3826 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3827 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3828 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3829
3830 layer glass GLASS,PADTXT,PADPIN
3831 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3832 variants (vendor)
3833 labels PADTXT port
3834 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3835 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3836 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3837 labels PADPIN port
3838
3839 templayer boundary BOUND,STDCELL,PADCELL
3840 boundary
3841
3842 layer comment LVSTEXT
3843 labels LVSTEXT text
3844
3845 layer comment TTEXT
3846 labels TTEXT text
3847
3848 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3849 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3850
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3851 layer obsactive FILLOBSFOM
3852
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3853# MOS Varactor
3854
3855 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3856 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3857 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3858 and NWELL,nwelcheck
3859 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3860 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3861 # NOTE: Else forms a varactor that is not in the vendor netlist.
3862 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3863 labels POLY
3864
3865 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3866 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3867 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3868 and NWELL,nwelcheck
3869 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3870 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3871 labels POLY
3872
3873 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3874 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3875 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3876 and NWELL,nwelcheck
3877 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3878 labels POLY
3879
3880 calma NWELL 64 20
3881 calma DIFF 65 20
3882 calma DNWELL 64 18
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]3883 calma SUBCUT 81 53
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3884 calma PWRES 64 13
3885 calma TAP 65 44
3886 # LVTN
3887 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3888 # HVTR
3889 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3890 # HVTP
3891 calma HVTP 78 44
3892 # SONOS (TUNM)
3893 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3894 # NSDM (NPLUS)
3895 calma NSDM 93 44
3896 # PSDM (PPLUS)
3897 calma PSDM 94 20
3898 # HVI (THKOX)
3899 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3900 # NPC
3901 calma NPC 95 20
3902 # P+ POLY MASK
3903 calma RPM 86 20
3904 calma URPM 79 20
3905 calma LDNTM 11 44
3906 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3907 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3908 calma POLYRES 66 13
3909 # Diffusion resistor ID mark
3910 calma DIFFRES 65 13
3911 calma POLY 66 20
3912 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]3913 # 3.3V native FET ID mark
3914 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3915 # Diode ID mark
3916 calma DIODE 81 23
3917 # Bipolar NPN mark
3918 calma NPNID 82 20
3919 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3920 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3921 # Capacitor ID
3922 calma CAPID 82 64
3923 # Core area ID mark
3924 calma COREID 81 2
3925 # Standard cell ID mark
3926 calma STDCELL 81 4
3927 # Padframe cell ID mark
3928 calma PADCELL 81 3
3929 # Seal ring ID mark
3930 calma SEALID 81 1
3931 # Low tap density ID mark
3932 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3933 # ESD area ID
3934 calma ESDID 81 19
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]3935 calma OUTLINE 236 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3936
3937 # LICON
3938 calma CONT 66 44
3939 calma LI 67 20
3940 calma MCON 67 44
3941
3942 calma MET1 68 20
3943 calma VIA1 68 44
3944 calma MET2 69 20
3945 calma VIA2 69 44
3946 calma MET3 70 20
3947#ifdef METAL5
3948 calma VIA3 70 44
3949 calma MET4 71 20
3950 calma VIA4 71 44
3951 calma MET5 72 20
3952#endif
3953#ifdef REDISTRIBUTION
3954 calma RDL 74 20
3955#endif
3956 calma GLASS 76 20
3957
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3958 calma SUBTXT 64 59
3959 calma PADTXT 76 5
3960 calma DIFFTXT 65 6
3961 calma TAPTXT 65 5
3962 calma WELLTXT 64 5
3963 calma LITXT 67 5
3964 calma POLYTXT 66 5
3965 calma MET1TXT 68 5
3966 calma MET2TXT 69 5
3967 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3968#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3969 calma MET4TXT 71 5
3970 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3971#endif
3972#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3973 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3974#endif
3975
3976 calma LIRES 67 13
3977 calma MET1RES 68 13
3978 calma MET2RES 69 13
3979 calma MET3RES 70 13
3980#ifdef METAL5
3981 calma MET4RES 71 13
3982 calma MET5RES 72 13
3983#endif
3984
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3985 calma LIFILL 56 28
3986 calma MET1FILL 36 28
3987 calma MET2FILL 41 28
3988 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3989#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3990 calma MET4FILL 51 28
3991 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3992#endif
3993
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3994 calma POLYSHORT 66 15
3995 calma LISHORT 67 15
3996 calma MET1SHORT 68 15
3997 calma MET2SHORT 69 15
3998 calma MET3SHORT 70 15
3999#ifdef METAL5
4000 calma MET4SHORT 71 15
4001 calma MET5SHORT 72 15
4002#endif
4003
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4004 calma SUBPIN 122 16
4005 calma PADPIN 76 16
4006 calma DIFFPIN 65 16
4007 calma POLYPIN 66 16
4008 calma WELLPIN 64 16
4009 calma LIPIN 67 16
4010 calma MET1PIN 68 16
4011 calma MET2PIN 69 16
4012 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4013#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4014 calma MET4PIN 71 16
4015 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4016#endif
4017#ifdef REDISTRIBUTION
4018 calma RDLPIN 74 16
4019#endif
4020
4021 calma BOUND 235 4
4022
4023 calma LVSTEXT 83 44
4024
4025#ifdef (MIM)
4026 calma CAPM 89 44
4027 calma CAPM2 97 44
4028#endif (MIM)
4029
4030 calma FILLOBSM1 62 24
4031 calma FILLOBSM2 105 52
4032 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]4033 calma FILLOBSM4 112 4
4034 calma FILLOBSFOM 22 24
4035 calma FILLOBSPOLY 33 24
4036
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4037 calma FOMFILL 23 28
4038 calma POLYFILL 28 28
4039 calma LIFILL 56 28
4040 calma MET1FILL 36 28
4041 calma MET2FILL 41 28
4042 calma MET3FILL 34 28
4043 calma MET4FILL 51 28
4044 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4045
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4046#-----------------------------------------------------------------------
4047
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4048style rdlimport
4049 # This style is for reading shapes generated with the RDL layers
4050
4051 scalefactor 10 nanometers
4052 gridlimit 5
4053
4054 options ignore-unknown-layer-labels no-reconnect-labels
4055
4056 layer mrdl RDL
4057 layer mrdlc RDLC
4058
4059 calma RDL 10 0
4060 calma RDLC 20 0
4061
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4062end
4063
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4064#-----------------------------------------------------
4065# Digital flow maze router cost parameters
4066#-----------------------------------------------------
4067
4068mzrouter
4069end
4070
4071#-----------------------------------------------------
4072# Vendor DRC rules
4073#-----------------------------------------------------
4074
4075drc
4076
4077 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4078 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4079 cifstyle drc
4080
4081 variants (fast),(full)
4082
4083#-----------------------------
4084# DNWELL
4085#-----------------------------
4086
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4087 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4088 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4089 spacing allnwell dnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4090 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4091
4092 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4093 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4094 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4095 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4096 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4097
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4098 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4099 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4100 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4101
4102#-----------------------------
4103# NWELL
4104#-----------------------------
4105
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4106 width allnwell 840 "N-well width < %d (nwell.1)"
4107 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4108
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4109 variants (full)
4110 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4111 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4112
4113 cifspacing mvnwell lvnwell 2000 touching_illegal \
4114 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4115 cifspacing mvnwell mvnwell 2000 touching_ok \
4116 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4117 variants (fast),(full)
4118
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4119#-----------------------------
4120# DIFF
4121#-----------------------------
4122
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4123 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4124 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4125 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4126 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4127
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4128 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4129 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4130 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4131 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4132 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4133 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4134 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4135 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4136 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4137 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4138 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4139 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4140 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4141 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4142 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4143 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4144 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4145 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4146 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4147 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4148 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4149 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4150 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4151 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4152 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4153 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4154 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4155 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4156 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4157 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4158 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4159 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4160 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4161 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4162 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4163 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4164
4165variants (full)
4166 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4167 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]4168 cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
4169 "HVI to HVI or LV nwell spacing < %d (hvi.5)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4170variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4171
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4172 spacing allnfets allpactivenonfet 270 touching_illegal \
4173 "nFET cannot abut P-diffusion (diff/tap.3)"
4174 spacing allpfets allnactivenonfet 270 touching_illegal \
4175 "pFET cannot abut N-diffusion (diff/tap.3)"
4176
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4177 # Butting junction rules
4178 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4179 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4180 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4181 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4182 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4183 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4184 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4185 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4186
4187 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4188 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4189 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4190 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4191 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4192 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4193 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4194 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4195
4196 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4197 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4198 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4199
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4200 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4201 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4202
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4203 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4204
4205 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4206 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4207
4208 # Latchup rules
4209 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4210 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4211 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4212 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4213 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4214 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4215
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4216 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4217
4218#-----------------------------
4219# POLY
4220#-----------------------------
4221
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4222 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4223 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4224
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4225 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4226 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4227 75 corner_ok allfets \
4228 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4229 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4230 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4231 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4232 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4233 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4234 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4235 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4236 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4237 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4238 rect_only allfets "No bends in transistors (poly.11)"
4239 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4240 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4241 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4242 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4243 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4244
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4245 variants (fast)
4246
4247 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4248 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4249 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4250 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4251 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4252 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4253
4254 # Minimum width requirement means actual spacing from res to ndiff has to be
4255 # constructed from mask rules. These supercede the simpler checks.
4256
4257 variants (full)
4258
4259 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4260 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4261 cifmaxwidth rpm_poly_check 0 bend_illegal \
4262 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4263 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4264 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4265
Tim Edwards75dea452021-05-08 15:55:26 -0400[diff] [blame]4266 variants (fast),(full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4267
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4268 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4269
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4270#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4271# HVTP
4272#--------------------------------------------------------------------
4273
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4274 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4275 360 touching_illegal \
4276 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4277
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4278 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4279 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4280
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4281#--------------------------------------------------------------------
4282# LVTN
4283#--------------------------------------------------------------------
4284
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4285 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4286 allfetsnolvt 360 touching_illegal \
4287 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4288
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4289 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4290 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4291 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4292
4293 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4294 edge4way allfetsnolvt allactivenonfet 415 \
4295 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4296 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4297
4298#--------------------------------------------------------------------
4299# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4300#--------------------------------------------------------------------
4301
4302# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4303
4304#--------------------------------------------------------------------
4305# CONT (LICON, contact between poly/diff and LI)
4306#--------------------------------------------------------------------
4307
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4308 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4309 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4310 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4311 width psc/li 170 "P-tap contact width < %d (licon.1)"
4312 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4313 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4314 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4315
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4316 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4317 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4318 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4319
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4320 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4321 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4322 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4323 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4324 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4325 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4326
4327 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4328 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4329 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4330 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4331 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4332 "Diffusion contact spacing < %d (licon.2)"
4333 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4334
4335 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4336 "poly contact spacing to diffusion < %d (licon.14)"
4337 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4338 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4339
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4340 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4341 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4342 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4343 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4344 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4345 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4346 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4347 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4348 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4349 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4350 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4351 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4352
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4353 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4354 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4355 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4356 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4357 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4358 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4359 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4360 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4361 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4362
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4363 spacing psc/a allnactivenontap 60 touching_illegal \
4364 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4365 spacing nsc/a allpactivenontap 60 touching_illegal \
4366 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4367
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4368 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4369 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4370 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4371 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4372 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4373 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4374 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4375 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4376 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4377
4378 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4379 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4380 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4381 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4382
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4383 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4384 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4385 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4386 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4387 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4388 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4389 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4390 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4391
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4392 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4393 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4394 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4395 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4396
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4397 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4398 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4399 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4400 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4401 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4402 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4403 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4404 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4405
4406 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4407 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4408 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4409 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4410
4411 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4412 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4413 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4414 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4415
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4416 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4417
4418#-------------------------------------------------------------
4419# LI - Local interconnect layer
4420#-------------------------------------------------------------
4421
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4422variants *
4423
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4424 width *li 170 "Local interconnect width < %d (li.1)"
4425 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4426
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4427 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4428 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4429
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4430 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4431 # no special layers for the contacts in core cells, so they must be included
4432 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4433 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4434 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4435
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4436 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4437 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4438
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4439 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4440 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4441
4442 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4443 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4444 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4445
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4446 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4447
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4448 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4449 angles coreli 45 \
4450 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4451
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4452#-------------------------------------------------------------
4453# MCON - Contact between local interconnect and metal1
4454#-------------------------------------------------------------
4455
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4456 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4457 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4458
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4459 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4460
4461#-------------------------------------------------------------
4462# METAL1 -
4463#-------------------------------------------------------------
4464
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4465 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4466 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4467 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4468
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4469 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4470 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4471 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4472 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4473
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4474 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4475
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4476variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4477 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4478 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4479 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4480 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4481
4482variants (full)
4483 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4484 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4485
4486 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4487 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4488variants *
4489
4490#--------------------------------------------------
4491# VIA1
4492#--------------------------------------------------
4493
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4494 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4495 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4496 surround v1/m1 *m1,rm1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4497 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4498 surround v1/m2 *m2,rm2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4499 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4500
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4501 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4502
4503#--------------------------------------------------
4504# METAL2 -
4505#--------------------------------------------------
4506
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4507 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4508 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4509 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4510
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4511 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4512
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4513variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4514 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4515 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4516 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4517 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4518
4519variants (full)
4520 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4521 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4522
4523 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4524 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4525variants *
4526
4527#--------------------------------------------------
4528# VIA2
4529#--------------------------------------------------
4530
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4531 width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4532
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4533 spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4534
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4535 surround v2/m2 *m2,rm2 45 directional \
4536 "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
4537 surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4538
4539 exact_overlap v2/m2
4540
4541#--------------------------------------------------
4542# METAL3 -
4543#--------------------------------------------------
4544
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4545 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4546 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4547 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4548
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4549 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4550
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4551variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4552 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4553 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4554 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4555 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4556variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4557 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4558 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4559variants *
4560
4561
4562#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4563#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4564#--------------------------------------------------
4565# VIA3 - Requires METAL5 Module
4566#--------------------------------------------------
4567
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4568 width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
4569 spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
4570 surround v3/m3 *m3,rm3 30 directional \
4571 "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
4572 surround v3/m4 *m4,rm4 5 absence_illegal \
4573 "Metal4 overlap of via3 < %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4574
4575 exact_overlap v3/m3
4576
4577#-----------------------------
4578# METAL4 - METAL4 Module
4579#-----------------------------
4580
4581variants *
4582
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4583 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4584 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4585 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4586
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4587 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4588
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4589variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4590 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4591 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4592 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4593 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4594variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4595 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4596 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4597variants *
4598
4599#--------------------------------------------------
4600# VIA4 - Requires METAL5 Module
4601#--------------------------------------------------
4602
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4603 width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
4604 spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
4605 surround v4/m5 *m5,rm5 120 absence_illegal \
4606 "Metal5 overlap of via4 < %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4607
4608 exact_overlap v4/m4
4609
4610#-----------------------------
4611# METAL5 - METAL5 Module
4612#-----------------------------
4613
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4614 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4615 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4616 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4617
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4618 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4619
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4620#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4621#endif (METAL5)
4622
4623#ifdef REDISTRIBUTION
4624
4625variants (full)
4626
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4627 width metrdl 10000 "RDL width < %d (rdl.1)"
4628 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4629 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4630 spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4631
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4632variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4633
4634#endif (REDISTRIBUTION)
4635
4636#--------------------------------------------------
4637# NMOS, PMOS
4638#--------------------------------------------------
4639
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4640 edge4way *poly allfetsstd 420 allfets 0 0 \
4641 "Transistor width < %d (diff/tap.2)"
4642 edge4way *poly allfetsspecial 360 allfets 0 0 \
4643 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4644 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4645 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4646 edge4way *poly ppu 140 allfets 0 0 \
4647 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4648
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4649 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4650 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4651
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4652 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4653 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4654 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4655 "poly spacing to diffusion tap < %d (poly.5)"
4656 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4657 "poly spacing to diffusion tap < %d (poly.5)"
4658 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4659 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4660
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4661 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4662 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4663 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4664 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4665 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4666 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4667 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4668 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4669
4670 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4671 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4672 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4673
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4674 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4675 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4676
4677 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4678 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4679 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4680
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4681 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4682 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4683
4684 # Minimum length of MV FETs. Note that this is larger than the minimum
4685 # width (0.29um), so an edge rule is required
4686
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4687 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4688 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4689
4690 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4691 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4692
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4693 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4694 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4695
4696#--------------------------------------------------
4697# mrp1 (N+ poly resistor)
4698#--------------------------------------------------
4699
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4700 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4701
4702#--------------------------------------------------
4703# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4704# uhrpoly (P+ poly resistor, 2kOhm/sq)
4705#--------------------------------------------------
4706
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4707 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4708 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4709 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4710
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4711 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4712 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4713
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4714 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4715 "Poly resistor spacing to poly < %d (poly.9)"
4716
4717 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4718 "Poly resistor spacing to poly < %d (poly.9)"
4719
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4720 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4721 "Poly resistor spacing to poly < %d (poly.9)"
4722
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4723 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4724 "Poly resistor spacing to diffusion < %d (poly.9)"
4725
4726#------------------------------------
4727# nsonos
4728#------------------------------------
4729
4730variants (full)
4731 cifmaxwidth bbox_missing 0 bend_illegal \
4732 "SONOS transistor must be in cell with abutment box (tunm.8)"
4733variants (fast),(full)
4734
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4735#------------------------------------
4736# MOS Varactor device rules
4737#------------------------------------
4738
4739 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4740 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4741
4742 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4743 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4744
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4745 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4746 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4747
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4748variants (full)
4749 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4750 "N-well overlap of varactor poly < 0.15um (varac.5)"
4751
4752 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4753 "Varactor N-well must not contain P+ diffusion (varac.7)"
4754variants (fast),(full)
4755
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4756#ifdef MIM
4757#-----------------------------------------------------------
4758# MiM CAP (CAPM) -
4759#-----------------------------------------------------------
4760
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4761 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4762 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4763 spacing *mimcap via3/m3 80 touching_illegal \
4764 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4765 surround *mimcc *mimcap 80 absence_illegal \
4766 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4767 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4768
4769 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4770 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4771 spacing via2 *mimcap 100 touching_illegal \
4772 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4773 spacing *mimcap *metal3/m3 500 surround_ok \
4774 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4775
4776variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4777 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4778 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4779variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4780
4781 # MiM cap contact rules (VIA3)
4782
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4783 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4784 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4785 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4786 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4787 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4788
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4789 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4790 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4791 spacing *mimcap2 via4/m4 10 touching_illegal \
4792 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4793 surround *mim2cc *mimcap2 10 absence_illegal \
4794 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4795 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4796
4797 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4798 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4799 spacing via3 *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4800 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4801 spacing *mimcap2 *metal4/m4 500 surround_ok \
4802 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4803
4804variants (full)
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4805 cifmaxwidth mim2_contact_overlap 0 bend_illegal \
4806 "MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
4807
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4808 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4809 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4810variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4811
4812 # MiM cap contact rules (VIA4)
4813
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4814 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4815 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4816 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4817 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4818 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4819 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4820
4821#endif (MIM)
4822
4823#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4824# HVNTM
4825#----------------------------
4826variants (full)
4827 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4828 "HVNTM spacing < %d (hvntm.2)"
4829variants (fast),(full)
4830
4831#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4832# End DRC style
4833#----------------------------
4834
4835end
4836
4837#----------------------------
4838# LEF format definitions
4839#----------------------------
4840
4841lef
4842
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4843 masterslice pwell pwell PWELL substrate
4844 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4845
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4846 routing li li1 LI1 LI li
4847
4848 routing m1 met1 MET1 m1
4849 routing m2 met2 MET2 m2
4850 routing m3 met3 MET3 m3
4851#ifdef METAL5
4852 routing m4 met4 MET4 m4
4853 routing m5 met5 MET5 m5
4854#endif (METAL5)
4855#ifdef REDISTRIBUTION
4856 routing mrdl met6 MET6 m6 MRDL METRDL
4857#endif
4858
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4859 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4860 cut m2c via via1 VIA VIA1 cont2 via12
4861 cut m3c via2 VIA2 cont3 via23
4862#ifdef METAL5
4863 cut via3 via3 VIA3 cont4 via34
4864 cut via4 via4 VIA4 cont5 via45
4865#endif (METAL5)
4866
4867 obs obsli li1
4868 obs obsm1 met1
4869 obs obsm2 met2
4870 obs obsm3 met3
4871
4872#ifdef METAL5
4873 obs obsm4 met4
4874 obs obsm5 met5
4875#endif (METAL5)
4876#ifdef REDISTRIBUTION
4877 obs obsmrdl met6
4878#endif
4879
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4880 # NOTE: obsmcon only used with li1, not obsli.
4881 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4882
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4883 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4884 obs obsm1 via
4885 obs obsm2 via2
4886#ifdef METAL5
4887 obs obsm3 via3
4888 obs obsm4 via4
4889#endif (METAL5)
4890
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4891end
4892
4893#-----------------------------------------------------
4894# Device and Parasitic extraction
4895#-----------------------------------------------------
4896
4897
4898extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4899 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4900 cscale 1
4901 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4902 # dimensions must be in units of microns in the extract file.
4903 # Use extract style "ngspice(si)" to override this and produce
4904 # a file with SI units for length/area.
4905
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4906 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4907 lambda 1E6
4908 variants (si)
4909 lambda 1.0
4910 variants *
4911
4912 units microns
4913 step 7
4914 sidehalo 2
4915
4916 # NOTE: MiM cap layers have been purposely put out of order,
4917 # may want to reconsider.
4918
4919 planeorder dwell 0
4920 planeorder well 1
4921 planeorder active 2
4922 planeorder locali 3
4923 planeorder metal1 4
4924 planeorder metal2 5
4925 planeorder metal3 6
4926#ifdef METAL5
4927 planeorder metal4 7
4928 planeorder metal5 8
4929#ifdef REDISTRIBUTION
4930 planeorder metali 9
4931 planeorder block 10
4932 planeorder comment 11
4933 planeorder cap1 12
4934 planeorder cap2 13
4935#else (!REDISTRIBUTION)
4936 planeorder block 9
4937 planeorder comment 10
4938 planeorder cap1 11
4939 planeorder cap2 12
4940#endif (!REDISTRIBUTION)
4941#else (!METAL5)
4942#ifdef REDISTRIBUTION
4943 planeorder metali 7
4944 planeorder block 8
4945 planeorder comment 9
4946 planeorder cap1 10
4947 planeorder cap2 11
4948#else (!REDISTRIBUTION)
4949 planeorder block 7
4950 planeorder comment 8
4951 planeorder cap1 9
4952 planeorder cap2 10
4953#endif (!REDISTRIBUTION)
4954#endif (!METAL5)
4955
4956 height dnwell -0.1 0.1
4957 height nwell,pwell 0.0 0.2062
4958 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4959 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4960 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4961 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4962 height alldiffcont 0.3262 0.61
4963 height pc 0.5062 0.43
4964 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4965 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4966 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4967 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4968 height v1 1.7361 0.27
4969 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4970 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4971 height v2 2.3661 0.42
4972 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4973 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4974#ifdef METAL5
4975 height v3 3.6311 0.39
4976 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4977 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4978 height v4 4.8661 0.505
4979 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4980 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4981 height mimcap 2.4661 0.2
4982 height mimcap2 3.7311 0.2
4983 height mimcc 2.6661 0.12
4984 height mim2cc 3.9311 0.09
4985#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]4986 height mrdlc 6.6311 0.63
4987 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4988#endif (!REDISTRIBUTION)
4989#endif (!METAL5)
4990
4991 # Antenna check parameters
4992 # Note that checks w/diode diffusion are not modeled
4993 model partial
4994 antenna poly sidewall 50 none
4995 antenna allcont surface 3 none
4996 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4997 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4998 antenna m1,m2,m3 sidewall 400 2600 400
4999 antenna v1 surface 3 0 18
5000 antenna v2 surface 6 0 36
5001#ifdef METAL5
5002 antenna m4,m5 sidewall 400 2600 400
5003 antenna v3,v4 surface 6 0 36
5004#endif (METAL5)
5005
5006 tiedown alldiffnonfet
5007
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]5008 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5009
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5010# Resistances are in milliohms per square
5011# Optional 3rd argument is the corner adjustment fraction
5012# Device values come from trtc.cor (typical corner)
5013 resist (dnwell)/dwell 2200000
5014 resist (pwell)/well 3050000
5015 resist (nwell)/well 1700000
5016 resist (rpw)/well 3050000 0.5
5017 resist (*ndiff,nsd)/active 120000
5018 resist (*pdiff,*psd)/active 197000
5019 resist (*mvndiff,mvnsd)/active 114000
5020 resist (*mvpdiff,*mvpsd)/active 191000
5021
5022 resist ndiffres/active 120000 0.5
5023 resist pdiffres/active 197000 0.5
5024 resist mvndiffres/active 114000 0.5
5025 resist mvpdiffres/active 191000 0.5
5026 resist mrp1/active 48200 0.5
5027 resist xhrpoly/active 319800 0.5
5028 resist uhrpoly/active 2000000 0.5
5029
5030 resist (allpolynonres)/active 48200
5031 resist rmp/active 48200
5032
5033 resist (allli)/locali 12200
5034 resist (allm1)/metal1 125
5035 resist (allm2)/metal2 125
5036 resist (allm3)/metal3 47
5037#ifdef METAL5
5038 resist (allm4)/metal4 47
5039 resist (allm5)/metal5 29
5040#endif (METAL5)
5041#ifdef REDISTRIBUTION
5042 resist mrdl/metali 5
5043#endif (REDISTRIBUTION)
5044
5045 contact ndc,nsc 15000
5046 contact pdc,psc 15000
5047 contact mvndc,mvnsc 15000
5048 contact mvpdc,mvpsc 15000
5049 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5050 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5051 contact m2c 4500
5052 contact m3c 3410
5053#ifdef METAL5
5054#ifdef MIM
5055 contact mimcc 4500
5056 contact mim2cc 3410
5057#endif (MIM)
5058 contact via3 3410
5059 contact via4 380
5060#endif (METAL5)
5061#ifdef REDISTRIBUTION
5062 contact mrdlc 6
5063#endif (REDISTRIBUTION)
5064
5065#-------------------------------------------------------------------------
5066# Parasitic capacitance values: Use document (...)
5067#-------------------------------------------------------------------------
5068# This uses the new "default" definitions that determine the intervening
5069# planes from the planeorder stack, take care of the reflexive sideoverlap
5070# definitions, and generally clean up the section and make it more readable.
5071#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5072# Also uses "units microns" statement. All values are taken from the
5073# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5074# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5075#-------------------------------------------------------------------------
5076# Remember that device capacitances to substrate are taken care of by the
5077# models. Thus, active and poly definitions ignore all "fet" types.
5078# fet types are excluded when computing parasitic capacitance to
5079# active from layers above them because poly is a shield; fet types are
5080# included for parasitics from layers above to poly. Resistor types
5081# should be removed from all parasitic capacitance calculations, or else
5082# they just create floating caps. Technically, the capacitance probably
5083# should be split between the two terminals. Unsure of the correct model.
5084#-------------------------------------------------------------------------
5085
5086#n-well
5087# NOTE: This value not found in PEX files
5088defaultareacap nwell well 120
5089
5090#n-active
5091# Rely on device models to capture *ndiff area cap
5092# Do not extract parasitics from resistors
5093# defaultareacap allnactivenonfet active 790
5094# defaultperimeter allnactivenonfet active 280
5095
5096#p-active
5097# Rely on device models to capture *pdiff area cap
5098# Do not extract parasitics from resistors
5099# defaultareacap allpactivenonfet active 810
5100# defaultperimeter allpactivenonfet active 300
5101
5102#poly
5103# Do not extract parasitics from resistors
5104# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5105# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5106# defaultperimeter allpolynonfet active 57
5107
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5108 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5109 defaultareacap *poly active nwell,obswell,pwell well 106
5110 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5111
5112#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5113 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5114 defaultareacap allli locali nwell,obswell,pwell well 37
5115 defaultperimeter allli locali nwell,obswell,pwell well 55
5116 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5117
5118#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5119 defaultoverlap allli locali allactivenonfet active 37
5120 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5121
5122#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5123 defaultoverlap allli locali allpolynonres active 94
5124 defaultsideoverlap allli locali allpolynonres active 52
5125 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5126
5127#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5128 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5129 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5130 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5131 defaultoverlap allm1 metal1 nwell well 26
5132
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5133#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5134 defaultoverlap allm1 metal1 allactivenonfet active 26
5135 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5136
5137#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5138 defaultoverlap allm1 metal1 allpolynonres active 45
5139 defaultsideoverlap allm1 metal1 allpolynonres active 47
5140 defaultsideoverlap *poly active allm1 metal1 17
5141
5142#metal1->locali
5143 defaultoverlap allm1 metal1 allli locali 114
5144 defaultsideoverlap allm1 metal1 allli locali 59
5145 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5146
5147#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5148 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5149 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5150 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5151 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5152
5153#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5154 defaultoverlap allm2 metal2 allactivenonfet active 17
5155 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5156
5157#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5158 defaultoverlap allm2 metal2 allpolynonres active 24
5159 defaultsideoverlap allm2 metal2 allpolynonres active 41
5160 defaultsideoverlap *poly active allm2 metal2 11
5161
5162#metal2->locali
5163 defaultoverlap allm2 metal2 allli locali 38
5164 defaultsideoverlap allm2 metal2 allli locali 46
5165 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5166
5167#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5168 defaultoverlap allm2 metal2 allm1 metal1 134
5169 defaultsideoverlap allm2 metal2 allm1 metal1 67
5170 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5171
5172#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5173 defaultsidewall allm3 metal3 63
5174 defaultoverlap allm3 metal3 nwell well 12
5175 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5176 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5177
5178#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5179 defaultoverlap allm3 metal3 allactive active 12
5180 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5181
5182#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5183 defaultoverlap allm3 metal3 allpolynonres active 16
5184 defaultsideoverlap allm3 metal3 allpolynonres active 44
5185 defaultsideoverlap *poly active allm3 metal3 9
5186
5187#metal3->locali
5188 defaultoverlap allm3 metal3 allli locali 21
5189 defaultsideoverlap allm3 metal3 allli locali 47
5190 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5191
5192#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5193 defaultoverlap allm3 metal3 allm1 metal1 35
5194 defaultsideoverlap allm3 metal3 allm1 metal1 55
5195 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5196
5197#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5198 defaultoverlap allm3 metal3 allm2 metal2 86
5199 defaultsideoverlap allm3 metal3 allm2 metal2 70
5200 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5201
5202#ifdef METAL5
5203#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5204 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5205# defaultareacap alltopm metal4 well 6
5206 areacap allm4/m4 8
5207 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5208 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5209
5210#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5211 defaultoverlap allm4 metal4 allactivenonfet active 8
5212 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5213
5214#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5215 defaultoverlap allm4 metal4 allpolynonres active 10
5216 defaultsideoverlap allm4 metal4 allpolynonres active 38
5217 defaultsideoverlap *poly active allm4 metal4 6
5218
5219#metal4->locali
5220 defaultoverlap allm4 metal4 allli locali 12
5221 defaultsideoverlap allm4 metal4 allli locali 40
5222 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5223
5224#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5225 defaultoverlap allm4 metal4 allm1 metal1 15
5226 defaultsideoverlap allm4 metal4 allm1 metal1 43
5227 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5228
5229#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5230 defaultoverlap allm4 metal4 allm2 metal2 20
5231 defaultsideoverlap allm4 metal4 allm2 metal2 46
5232 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5233
5234#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5235 defaultoverlap allm4 metal4 allm3 metal3 84
5236 defaultsideoverlap allm4 metal4 allm3 metal3 71
5237 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5238
5239#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5240 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5241# defaultareacap allm5 metal5 well 6
5242 areacap allm5/m5 6
5243 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5244 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5245
5246#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5247 defaultoverlap allm5 metal5 allactivenonfet active 6
5248 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5249
5250#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5251 defaultoverlap allm5 metal5 allpolynonres active 7
5252 defaultsideoverlap allm5 metal5 allpolynonres active 40
5253 defaultsideoverlap *poly active allm5 metal5 6
5254
5255#metal5->locali
5256 defaultoverlap allm5 metal5 allli locali 8
5257 defaultsideoverlap allm5 metal5 allli locali 41
5258 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5259
5260#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5261 defaultoverlap allm5 metal5 allm1 metal1 9
5262 defaultsideoverlap allm5 metal5 allm1 metal1 43
5263 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5264
5265#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5266 defaultoverlap allm5 metal5 allm2 metal2 11
5267 defaultsideoverlap allm5 metal5 allm2 metal2 46
5268 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5269
5270#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5271 defaultoverlap allm5 metal5 allm3 metal3 20
5272 defaultsideoverlap allm5 metal5 allm3 metal3 54
5273 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5274
5275#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5276 defaultoverlap allm5 metal5 allm4 metal4 68
5277 defaultsideoverlap allm5 metal5 allm4 metal4 83
5278 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5279#endif (METAL5)
5280
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5281#ifdef REDISTRIBUTION
5282#endif (REDISTRIBUTION)
5283
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5284# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5285
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5286variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5287
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5288 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5289 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5290 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5291 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5292 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5293 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5294 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5295 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5296 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5297 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5298 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5299 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5300 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5301 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5302 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5303
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5304 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5305 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5306 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5307 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5308 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5309 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5310 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5311 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5312 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5313 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5314 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5315 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5316 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5317 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5318 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5319 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5320 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5321 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5322 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5323 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5324 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5325 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5326 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5327 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5328
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5329 # Bipolars
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5330 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
5331 error +npn1p00
5332 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
5333 error +npn2p00
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]5334 device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5335 device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
5336 pwell,space/w +pnp0p68
5337 device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
5338 pwell,space/w +pnp3p40
Tim Edwardsb9668302021-05-27 14:10:11 -0400[diff] [blame]5339 device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5340 device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
5341 dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5342 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5343
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5344 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5345 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5346 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5347 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5348
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5349 # Extended drain devices (must appear before the regular devices)
5350 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5351 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5352 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5353 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5354 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5355 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5356
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5357 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5358 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5359 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5360 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5361 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5362 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5363 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5364 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5365 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5366 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5367 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5368 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5369 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5370 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5371 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5372 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5373 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5374 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5375
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5376 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5377 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5378 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5379 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5380#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5381 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5382 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5383#endif (METAL5)
5384
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5385 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5386 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5387 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5388 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5389 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5390 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5391 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5392 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5393 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5394 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5395 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5396 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5397 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5398 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5399 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5400 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5401 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5402 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5403 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5404 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5405 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5406 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5407 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5408 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5409
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5410 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5411 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5412 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5413 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5414 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5415 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5416 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5417 *mvndiff pwell,space/w error l=l w=w
5418 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5419 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5420
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5421 device resistor sky130_fd_pr__res_generic_po rmp *poly
5422 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5423
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5424 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
5425 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
5426 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
5427 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5428
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5429 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
5430 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
5431 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
5432 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5433
5434#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5435 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5436 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5437#endif (MIM)
5438
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5439 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5440
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5441 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5442 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5443 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5444 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5445 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5446 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5447 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5448 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5449 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5450 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5451 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5452 pwell,space/w
5453
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5454 # Note that corenvar, corepvar are not considered devices, and extract as
5455 # parasitic capacitance instead (but cap values need to be added).
5456
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5457 # Extended drain devices (must appear before the regular devices)
5458 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5459 dnwell pwell,space/w error
5460 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5461 dnwell pwell,space/w error
5462 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5463 pwell,space/w nwell error
5464
5465 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5466 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5467 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5468 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5469 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5470 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5471
5472 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5473 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5474 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5475 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5476
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5477 device resistor sky130_fd_pr__res_generic_po rmp *poly
5478 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5479 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5480 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5481 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5482#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5483 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5484 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5485#endif (METAL5)
5486
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5487 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5488 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5489 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5490 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5491 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5492 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5493 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5494 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5495 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5496 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5497 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5498 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5499 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5500 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5501 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5502 device resistor mrdn_hv mvndiffres *mvndiff
5503 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5504 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5505
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5506 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5507 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5508 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5509 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5510
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5511 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5512 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5513 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5514 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5515
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5516 device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
5517 device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5518 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5519 device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
5520 device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5521 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5522 device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5523 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5524
5525#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5526 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5527 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5528#endif (MIM)
5529
5530end
5531
5532#-----------------------------------------------------
5533# Wiring tool definitions
5534#-----------------------------------------------------
5535
5536wiring
5537 # All wiring values are in nanometers
5538 scalefactor 10
5539
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5540 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5541 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5542 contact v2 280 m2 0 45 m3 25 0
5543#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5544 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5545 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5546#endif (METAL5)
5547
5548 contact pc 170 poly 50 80 li 0 80
5549 contact pdc 170 pdiff 40 60 li 0 80
5550 contact ndc 170 ndiff 40 60 li 0 80
5551 contact psc 170 psd 40 60 li 0 80
5552 contact nsc 170 nsd 40 60 li 0 80
5553
5554end
5555
5556#-----------------------------------------------------
5557# Plain old router. . .
5558#-----------------------------------------------------
5559
5560router
5561end
5562
5563#------------------------------------------------------------
5564# Plowing (restored in magic 8.2, need to fill this section)
5565#------------------------------------------------------------
5566
5567plowing
5568end
5569
5570#-----------------------------------------------------------------
5571# No special plot layers defined (use default PNM color choices)
5572#-----------------------------------------------------------------
5573
5574plot
5575 style pnm
5576 default
5577 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5578 draw fillblock4 no_color_at_all
5579 draw fomfill no_color_at_all
5580 draw polyfill no_color_at_all
5581 draw m1fill no_color_at_all
5582 draw m2fill no_color_at_all
5583 draw m3fill no_color_at_all
5584 draw m4fill no_color_at_all
5585 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5586 draw nwell cwell
5587end
5588