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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 194356278b133c2bb879dcd9cf36c5cf22c26978 / . / sky130 / magic / sky130.tech
blob: 121c5ca1c65112661b797a5baf5ae0fc8b85e791 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]66# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v5 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]85# sky130_fd_pr__photodiode photo Photodiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]86#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]87# (*) Note that ppres may extract into some generic type called
88# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
89# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]90#
91# (**) nFET and pFET in standard cells are the same as devices
92# outside of the standard cell except for the DRC rule for
93# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
94#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]95#-------------------------------------------------------------
96# The following devices are not extracted but are represented
97# only by script-generated subcells in the PDK.
98#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]145 dwell isosubstrate,isosub
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]146 dwell photodiode,photo
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]147
148# Wells
149 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well pwell,pw
151 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]152 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]153 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]154 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]155
156# Transistors
157 active nmos,ntransistor,nfet
158 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]159 -active npd,npdfet,sramnfet
160 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]161 active pmos,ptransistor,pfet
162 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]163 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]164 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]165 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]166 active mvnmos,mvntransistor,mvnfet
167 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]168 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]169 -active mvnmosesd,mvntransistoresd,mvnfetesd
170 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]171 active varactor,varact,var
172 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]173
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]174 active pmoslvt,pfetlvt
175 active pmosmvt,pfetmvt
176 active pmoshvt,pfethvt
177 active nmoslvt,nfetlvt
178 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]179 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]180 -active sramnvar,corenvar,corenvaractor
181 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182
183# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]184 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]185 active ndiff,ndiffusion,ndif
186 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]187 active mvndiff,mvndiffusion,mvndif
188 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]189 active ndiffc,ndcontact,ndc
190 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]191 active mvndiffc,mvndcontact,mvndc
192 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]193 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
194 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
195 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
196 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
197 active psubdiffcont,psubstratepcontact,psc,ptapc
198 active nsubdiffcont,nsubstratencontact,nsc,ntapc
199 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
200 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]201 -active obsactive
202 -active mvobsactive
203
204# Poly
205 active poly,p,polysilicon
206 active polycont,pc,pcontact,polycut,polyc
207 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]208 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]209
210# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]211 active npolyres,npres,mrp1
212 active ppolyres,ppres,xhrpoly
213 active xpolyres,xpres,xres,uhrpoly
214 active ndiffres,rnd,rdn,rndiff
215 active pdiffres,rpd,rdp,rpdiff
216 active mvndiffres,mvrnd,mvrdn,mvrndiff
217 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
218 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]219
220# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]221 active pdiode,pdi
222 active ndiode,ndi
223 active nndiode,nndi
224 active pdiodec,pdic
225 active ndiodec,ndic
226 active nndiodec,nndic
227 active mvpdiode,mvpdi
228 active mvndiode,mvndi
229 active mvpdiodec,mvpdic
230 active mvndiodec,mvndic
231 active pdiodelvt,pdilvt
232 active pdiodehvt,pdihvt
233 active ndiodelvt,ndilvt
234 active pdiodelvtc,pdilvtc
235 active pdiodehvtc,pdihvtc
236 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]237
238# Local Interconnect
239 locali locali,li1,li
240 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]241 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]243 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]244 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]245 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]246
247# Metal 1
248 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]249 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]250 metal1 via1,m2contact,m2cut,m2c,via,v,v1
251 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]252 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]253 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]254
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]255#ifdef RERAM
256 metal2 reram,rr
257#endif
258
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259# Metal 2
260 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]261 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]262 metal2 via2,m3contact,m3cut,m3c,v2
263 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]264 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]265
266# Metal 3
267 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]269 -metal3 obsm3
270#ifdef METAL5
271 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]272 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]273
274#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 cap1 mimcap,mim,capm
276 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]277#endif
278
279# Metal 4
280 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]282 -metal4 obsm4
283 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]284 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]285
286#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 cap2 mimcap2,mim2,capm2
288 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]289#endif
290
291# Metal 5
292 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]293 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]294 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]295 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]296#endif (METAL5)
297
298#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]299 metal5 mrdlcontact,mrdlc,pi1
300 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]301 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]302 metali pi2
303 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304#endif (REDISTRIBUTION)
305
306# Miscellaneous
307 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]308 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]309 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]310 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]311# fixed resistor width identifiers
312 -comment res0p35
313 -comment res0p69
314 -comment res1p41
315 -comment res2p85
316 -comment res5p73
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]317# fixed bipolar area identifiers
318 -comment pnp0p68
319 -comment pnp3p40
320 -comment npn1p00
321 -comment npn2p00
322 -comment npn11p0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]323
324end
325
326#-----------------------------------------------------
327# Magic contact types
328#-----------------------------------------------------
329
330contact
331 pc poly locali
332 ndc ndiff locali
333 pdc pdiff locali
334 nsc nsd locali
335 psc psd locali
336 ndic ndiode locali
337 ndilvtc ndiodelvt locali
338 nndic nndiode locali
339 pdic pdiode locali
340 pdilvtc pdiodelvt locali
341 pdihvtc pdiodehvt locali
342 xpc xpc locali
343
344 mvndc mvndiff locali
345 mvpdc mvpdiff locali
346 mvnsc mvnsd locali
347 mvpsc mvpsd locali
348 mvndic mvndiode locali
349 mvpdic mvpdiode locali
350
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]351 mcon locali metal1
352 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]353
354 via1 metal1 metal2
355 via2 metal2 metal3
356#ifdef METAL5
357 via3 metal3 metal4
358 via4 metal4 metal5
359#endif (METAL5)
360 stackable
361
362#ifdef METAL5
363#ifdef MIM
364 # MiM cap contacts are not stackable!
365 mimcc mimcap metal4
366 mim2cc mimcap2 metal5
367#endif (MIM)
368
369 padl m1 m2 m3 m4 m5 glass
370#else
371 padl m1 m2 m3 glass
372#endif (!METAL5)
373
374#ifdef REDISTRIBUTION
375 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]376 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]377#endif (REDISTRIBUTION)
378end
379
380#-----------------------------------------------------
381# Layer aliases
382#-----------------------------------------------------
383
384aliases
385
386 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]387 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]389 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]390 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]391 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]392 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]393 allfetsspecial scnfet,scpfet,scpfethvt
394 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]395 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]396
397 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
398 allnactive allnactivenonfet,allnfets
399 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]400 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]401
402 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
403 allpactive allpactivenonfet,allpfets
404 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]405 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]406
407 allactivenonfet allnactivenonfet,allpactivenonfet
408 allactive allactivenonfet,allfets
409
410 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
411
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]412 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]413 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]414 alldifflv allndifflv,allpdifflv
415 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
416 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
417 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
418
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]419 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]420 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]421 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]422 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]423 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]424 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
425 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
426 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
427 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
428
429 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]430 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]431
432 allpolyres mrp1,xhrpoly,uhrpoly,rmp
433 allpolynonfet *poly,allpolyres,xpc
434 allpolynonres *poly,allfets,xpc
435
436 allpoly allpolynonfet,allfets
437 allpolynoncap *poly,xpc,allfets,allpolyres
438
439 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
440 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
441 allndiffcontmv mvndc,mvnsc,mvndic
442 allpdiffcontmv mvpdc,mvpsc,mvpdic
443 allndiffcont allndiffcontlv,allndiffcontmv
444 allpdiffcont allpdiffcontlv,allpdiffcontmv
445 alldiffcontlv allndiffcontlv,allpdiffcontlv
446 alldiffcontmv allndiffcontmv,allpdiffcontmv
447 alldiffcont alldiffcontlv,alldiffcontmv
448
449 allcont alldiffcont,pc
450
451 allres allpolyres,allactiveres
452
453 allli *locali,coreli,rli
454 allm1 *m1,rm1
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]455#ifdef RERAM
456 allm2 *m2,rm2,reram
457#else (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]458 allm2 *m2,rm2
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]459#endif (!RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]460 allm3 *m3,rm3
461#ifdef METAL5
462 allm4 *m4,rm4
463 allm5 *m5,rm5
464#endif (METAL5)
465
466 allpad padl
467
468 psub pwell
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]469
470 obstypes obswell,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment
471 idtypes res0p35,res0p69,res1p41,res2p85,res5p73,pnp0p68,pnp3p40,npn1p00,npn2p00,npn11p0
472 blocktypes fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473
474end
475
476#-----------------------------------------------------
477# Layer drawing styles
478#-----------------------------------------------------
479
480styles
481 styletype mos
482 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]483 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]484 nwell nwell
485 pwell pwell
486 rpwell pwell ptransistor_stripes
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]487 photo nwell nwell_field_implant
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]488 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]489 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]490 pdiff pdiffusion
491 nsd ndiff_in_nwell
492 psd pdiff_in_pwell
493 nfet ntransistor ntransistor_stripes
494 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]495 npass ntransistor ntransistor_stripes
496 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 pfet ptransistor ptransistor_stripes
498 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]499 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]500 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]501 var polysilicon ndiff_in_nwell
502 ndc ndiffusion metal1 contact_X'es
503 pdc pdiffusion metal1 contact_X'es
504 nsc ndiff_in_nwell metal1 contact_X'es
505 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]506 corenvar polysilicon ndiff_in_nwell
507 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]509 pnp nwell ntransistor_stripes
510 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]511
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]512 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]513 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]514 pfethvt ptransistor ptransistor_stripes implant2
515 nfetlvt ntransistor ntransistor_stripes implant1
516 nsonos ntransistor implant3
517 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]518 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]519
520 mvndiff ndiffusion hvndiff_mask
521 mvpdiff pdiffusion hvpdiff_mask
522 mvnsd ndiff_in_nwell hvndiff_mask
523 mvpsd pdiff_in_pwell hvpdiff_mask
524 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]525 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]526 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
527 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]528 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]529 mvvar polysilicon ndiff_in_nwell hvndiff_mask
530 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
531 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
532 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
533 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
534
535 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]536 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]537 pc polysilicon metal1 contact_X'es
538 npolyres polysilicon silicide_block nselect2
539 ppolyres polysilicon silicide_block pselect2
540 xpc polysilicon pselect2 metal1 contact_X'es
541 rmp polysilicon poly_resist_stripes
542
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]543 res0p35 implant1
544 res0p69 implant1
545 res1p41 implant1
546 res2p85 implant1
547 res5p73 implant1
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]548 pnp0p68 implant1
549 pnp3p40 implant1
550 npn1p00 implant1
551 npn2p00 implant1
552 npn11p0 implant1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]553
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]554 pdiode pdiffusion pselect2
555 ndiode ndiffusion nselect2
556 pdiodec pdiffusion pselect2 metal1 contact_X'es
557 ndiodec ndiffusion nselect2 metal1 contact_X'es
558
559 nndiode ndiffusion nselect2 implant3
560 ndiodelvt ndiffusion nselect2 implant1
561 pdiodelvt pdiffusion pselect2 implant1
562 pdiodehvt pdiffusion pselect2 implant2
563 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
564 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
565 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
566
567 mvpdiode pdiffusion pselect2 hvpdiff_mask
568 mvndiode ndiffusion nselect2 hvndiff_mask
569 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
570 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
571 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
572
573 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]574 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]575 coreli metal1
576 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]577 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]578 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]579 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]580
581 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]582 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]583 rm1 metal2 poly_resist_stripes
584 obsm1 metal2
585 m2c metal2 metal3 via2arrow
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]586
587#ifdef RERAM
588 reram metal2 metal3 via2 contact_X'es
589#endif (RERAM)
590
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]591 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]592 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]593 rm2 metal3 poly_resist_stripes
594 obsm2 metal3
595 m3c metal3 metal4 via3alt
596 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]597 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]598 rm3 metal4 poly_resist_stripes
599 obsm3 metal4
600#ifdef METAL5
601#ifdef MIM
602 mimcap metal3 mems
603 mimcc metal3 contact_X'es mems
604 mimcap2 metal4 mems
605 mim2cc metal4 contact_X'es mems
606#endif (MIM)
607 via3 metal4 metal5 via4
608 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]609 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]610 rm4 metal5 poly_resist_stripes
611 obsm4 metal5
612 via4 metal5 metal6 via5
613 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]614 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]615 rm5 metal6 poly_resist_stripes
616 obsm5 metal6
617#endif (METAL5)
618#ifdef REDISTRIBUTION
619 mrdlc metal6 metal7 via6
620 metalrdl metal7
621 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]622 ubm metal8
623 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]624#endif (REDISTRIBUTION)
625
626 glass overglass
627 mrp1 poly_resist poly_resist_stripes
628 xhrpoly poly_resist silicide_block
629 uhrpoly poly_resist
630 ndiffres ndiffusion ndop_stripes
631 pdiffres pdiffusion pdop_stripes
632 mvndiffres ndiffusion hvndiff_mask ndop_stripes
633 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
634 comment comment
635 error_p error_waffle
636 error_s error_waffle
637 error_ps error_waffle
638 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]639 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]640
641 obswell cwell
642 obsactive implant4
643
644#ifndef METAL5
645 padl metal4 via4 overglass
646#else
647 padl metal6 via6 overglass
648#endif
649
650 magnet substrate_field_implant
651 rotate via3alt
652 fence via5
653end
654
655#-----------------------------------------------------
656# Special paint/erase rules
657#-----------------------------------------------------
658
659compose
660 compose nfet poly ndiff
661 compose pfet poly pdiff
662 compose var poly nsd
663
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]664 decompose npass poly ndiff
665 decompose npd poly ndiff
666 decompose scnfet poly ndiff
667 decompose nfetlvt poly ndiff
668 decompose nsonos poly ndiff
669
670 decompose ppu poly pdiff
671 decompose scpfet poly pdiff
672 decompose scpfethvt poly pdiff
673 decompose pfethvt poly pdiff
674 decompose pfetlvt poly pdiff
675 decompose pfetmvt poly pdiff
676 decompose corenvar poly nsd
677 decompose corepvar poly psd
678 decompose varhvt poly nsd
679
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]680 compose mvnfet poly mvndiff
681 compose mvpfet poly mvpdiff
682 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]683
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]684 decompose nnfet poly mvndiff
685 decompose mvnfetesd poly mvndiff
686 decompose mvnnfet poly mvndiff
687 decompose mvpfetesd poly mvpdiff
688
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]689 paint obsmcon locali via1
690 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]691
692 paint ndc nwell pdc
693 paint nfet nwell pfet
694 paint scnfet nwell scpfet
695 paint ndiff nwell pdiff
696 paint psd nwell nsd
697 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]698 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]699
700 paint pdc pwell ndc
701 paint pfet pwell nfet
702 paint scpfet pwell scnfet
703 paint pdiff pwell ndiff
704 paint nsd pwell psd
705 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]706 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]707
708 paint pdc coreli pdc
709 paint ndc coreli ndc
710 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]711 paint nsc coreli nsc
712 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]713 paint viali coreli viali
714
715 paint coreli pdc pdc
716 paint coreli ndc ndc
717 paint coreli pc pc
718 paint coreli nsc nsc
719 paint coreli psc psc
720 paint coreli viali viali
721
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]722#ifdef RERAM
723 paint reram metal2 reram
724#endif (RERAM)
725
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]726#ifdef METAL5
727 paint m4 obsm4 m4
728 paint m5 obsm5 m5
729#endif (METAL5)
730end
731
732#-----------------------------------------------------
733# Electrical connectivity
734#-----------------------------------------------------
735
736connect
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]737 *nwell,*nsd,*mvnsd,dnwell,pnp,photo *nwell,*nsd,*mvnsd,dnwell,pnp,photo
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]738 pwell,*psd,*mvpsd,npn,isosub pwell,*psd,*mvpsd,npn,isosub
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]739 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]740 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]741#ifdef RERAM
742 *m2,m2fill,reram *m2,m2fill,reram
743#else (!RERAM)
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]744 *m2,m2fill *m2,m2fill
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]745#endif (!RERAM)
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]746 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]747#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]748 *m4,m4fill *m4,m4fill
749 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]750#ifdef MIM
751 *mimcap *mimcap
752 *mimcap2 *mimcap2
753#endif (MIM)
754#endif (METAL5)
755 allnactivenonfet allnactivenonfet
756 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]757 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]758#ifdef REDISTRIBUTION
759 # RDL connects to m5 (i.e., padl) through glass cut
760 *mrdl *mrdl
761 glass metrdl
762#endif (REDISTRIBUTION)
763end
764
765#-----------------------------------------------------
766# CIF/GDS output layer definitions
767#-----------------------------------------------------
768# NOTE: All values in this section MUST be multiples of 25
769# or else magic will scale below the allowed layout grid size
770
771cifoutput
772
773#----------------------------------------------------------------
774style gdsii
775# NOTE: This section is used for actual GDS output
776#----------------------------------------------------------------
777 scalefactor 10 nanometers
778 options calma-permissive-labels
779 gridlimit 5
780
781#----------------------------------------------------------------
782# Create a temp layer from the cell bounding box for use in
783# generating ID layers. Note that "boundary", unlike "bbox",
784# requires the FIXED_BBOX property (abutment box) in the cell.
785#----------------------------------------------------------------
786 templayer CELLBOUND
787 boundary
788
789#----------------------------------------------------------------
790# BOUND
791#----------------------------------------------------------------
792 layer BOUND CELLBOUND
793 calma 235 4
794
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]795#----------------------------------------------------------------
796# DNWELL
797#----------------------------------------------------------------
798
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]799 layer DNWELL dnwell,npn,photo
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]800 calma 64 18
801
802 layer PWRES rpw
803 and dnwell
804 calma 64 13
805
806#----------------------------------------------------------------
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]807# SUBCUT
808#----------------------------------------------------------------
809
810 layer SUBCUT isosub
811 calma 81 53
812
813#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]814# NWELL
815#----------------------------------------------------------------
816
817 layer NWELL allnwell
818 bloat-all rpw dnwell
819 and-not rpw,pwell
820 calma 64 20
821
822 layer WELLTXT
823 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]824 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]825
826 layer WELLPIN
827 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]828 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]829
830#----------------------------------------------------------------
831# SUB (text/port only)
832#----------------------------------------------------------------
833
834 layer SUBTXT
835 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]836 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]837
838 layer SUBPIN
839 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]840 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]841
842#----------------------------------------------------------------
843# DIFF
844#----------------------------------------------------------------
845
846 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]847 calma 65 20
848
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]849 layer DIFFTXT
850 labels allnactivenontap,allpactivenontap noport
851 calma 65 6
852
853 layer DIFFPIN
854 labels allnactivenontap,allpactivenontap port
855 calma 65 16
856
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]857#----------------------------------------------------------------
858# TAP
859#----------------------------------------------------------------
860
861 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]862 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]863 calma 65 44
864
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]865 layer TAPTXT
866 labels allnactivetap,allpactivetap noport
867 calma 65 5
868
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]869#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]870# FOM
871#----------------------------------------------------------------
872
873 layer FOMFILL fomfill
874 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]875 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]876
877#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]878# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]879#----------------------------------------------------------------
880
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]881 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]882 grow 15
883 or xhrpoly,uhrpoly,xpc
884 grow 110
885 bloat-or allpactivetap * 125 allnactivenontap 0
886 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]887
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]888 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]889 grow 125
890 bloat-or allnactivetap * 125 allpactivenontap 0
891 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]892
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]893 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]894 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]895 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]896
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]897 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]898 grow 185
899 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]900 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]901 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]902 calma 94 20
903
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]904 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]905 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]906 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]907
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]908 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]909 grow 185
910 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]911 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]912 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]913 calma 93 44
914
915#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]916# LVID
917#----------------------------------------------------------------
918
919 layer LVID nnfet
920 grow 100
921 calma 81 60
922
923#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]924# LVTN
925#----------------------------------------------------------------
926
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]927 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]928 grow 180
929 bridge 380 380
930 grow 185
931 shrink 185
932 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]933 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]934 calma 125 44
935
936#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]937# HVTR
938#----------------------------------------------------------------
939
940 layer HVTR pfetmvt
941 grow 180
942 bridge 380 380
943 grow 185
944 shrink 185
945 close 265000
946 calma 18 20
947
948#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]949# HVTP
950#----------------------------------------------------------------
951
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]952 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]953 grow 180
954 bridge 380 380
955 grow 185
956 shrink 185
957 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]958 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]959 calma 78 44
960
961#----------------------------------------------------------------
962# SONOS
963#----------------------------------------------------------------
964
965 layer SONOS nsonos
966 grow 100
967 grow-min 410
968 bridge 500 410
969 grow 250
970 shrink 250
971 calma 80 20
972
973#----------------------------------------------------------------
974# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]975# coreli layer indicates a cell needing COREID. Also, devices
976# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]977#----------------------------------------------------------------
978
979 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]980 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]981 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]982 calma 81 2
983
984#----------------------------------------------------------------
985# STDCELL applies to all cells containing scnfet or scpfet.
986#----------------------------------------------------------------
987
988 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]989 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]990 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]991 calma 81 4
992
993#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]994# ESDID is a marker layer for ESD devices in the padframe I/O.
995#----------------------------------------------------------------
996
997 layer ESDID
998 bloat-all mvnfetesd *mvndiff,*poly
999 bloat-all mvpfetesd *mvpdiff,*poly
1000 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1001 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]1002 calma 81 19
1003
1004#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1005# NPNID and PNPID apply to bipolar transistors
1006#----------------------------------------------------------------
1007
1008 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]1009 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1010 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1011 calma 82 20
1012
1013 templayer pnparea pnp
1014 grow 400
1015
1016 layer PNPID
1017 bloat-all pnparea *psd
1018 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]1019 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1020 calma 82 44
1021
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]1022 layer PHOTO photo
1023 calma 81 81
1024
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]1025#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1026# RPM
1027#----------------------------------------------------------------
1028
1029 layer RPM
1030 bloat-all xhrpoly xpc
1031 grow 200
1032 grow-min 1270
1033 grow 420
1034 shrink 420
1035 calma 86 20
1036
1037#----------------------------------------------------------------
1038# URPM (2kOhms/sq. poly implant)
1039#----------------------------------------------------------------
1040
1041 layer URPM
1042 bloat-all uhrpoly xpc
1043 grow 200
1044 grow-min 1270
1045 grow 420
1046 shrink 420
1047 calma 79 20
1048
1049#----------------------------------------------------------------
1050# LDNTM (Tip implant for SONOS FETs)
1051#----------------------------------------------------------------
1052
1053 layer LDNTM
1054 bloat-all nsonos *ndiff
1055 grow 185
1056 grow 345
1057 shrink 345
1058 calma 11 44
1059
1060#----------------------------------------------------------------
1061# HVNTM (Tip implant for MV ndiff devices)
1062#----------------------------------------------------------------
1063
1064 templayer hvntm_block *mvpsd
1065 grow 185
1066
1067 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1068 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1069 bloat-all mvvaractor *mvnsd
1070 and-not hvntm_block
1071 grow 185
1072 grow 345
1073 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1074 and-not hvntm_block
Tim Edwardsce38f722021-07-22 11:43:58 -0400[diff] [blame]1075 mask-hints HVNTM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1076 calma 125 20
1077
1078#----------------------------------------------------------------
1079# POLY
1080#----------------------------------------------------------------
1081
1082 layer POLY allpoly
1083 calma 66 20
1084
1085 layer POLYTXT
1086 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1087 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1088
1089 layer POLYPIN
1090 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1091 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1092
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1093 layer POLYFILL polyfill
1094 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1095 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1096
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1097#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1098# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1099#----------------------------------------------------------------
1100
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1101 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1102 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1103 bloat-all alldiffmv nwell
1104 grow 345
1105 shrink 345
1106
1107 templayer large_ptap_mv thkox_area
1108 shrink 420
1109 grow 420
1110
1111 templayer small_ptap_mv thkox_area
1112 and-not large_ptap_mv
1113 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1114 grow-min 840
1115
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1116 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1117 bridge 700 600
1118 grow 345
1119 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1120 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1121 calma 75 20
1122
1123#----------------------------------------------------------------
1124# CONT (LICON)
1125#----------------------------------------------------------------
1126
1127 layer CONT allcont
1128 squares-grid 0 170 170
1129 calma 66 44
1130
1131 # Contact for pres is different than other LICON contacts
1132 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1133 templayer xpc_horiz xpc
1134 shrink 1007
1135 grow 1007
1136
1137 layer CONT xpc
1138 and-not xpc_horiz
1139 # Force long edge vertical for contacts narrower than 2um
1140 # Minimum space is 350 but 520 satisfies no. of contacts rule
1141 slots 80 190 520 80 2000 350
1142 calma 66 44
1143
1144 layer CONT xpc
1145 and xpc_horiz
1146 # Force long edge vertical for contacts wider than 2um
1147 # Minimum space is 350 but 520 satisfies no. of contacts rule
1148 slots 80 2000 350 80 190 520
1149 calma 66 44
1150
1151#----------------------------------------------------------------
1152# NPC (Nitride poly cut)
1153# surrounds CONT (LICON) on poly only (i.e., pc)
1154#----------------------------------------------------------------
1155
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1156 # Avoids a common case of NPC bridges too close to other LICON shapes.
1157 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1158 grow 90
1159
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1160 layer NPC pc
1161 squares-grid 0 170 170
1162 grow 100
1163 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1164 and-not diffcutarea
1165 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1166 grow 130
1167 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1168 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1169 calma 95 20
1170
1171 # NPC is also generated on xhrpoly and uhrpoly resistors
1172
1173 layer NPC xpc,xhrpoly,uhrpoly
1174 # xpc surrounds precision_resistor by 0.095um
1175 grow 95
1176 grow 130
1177 shrink 130
1178 calma 95 20
1179
1180#----------------------------------------------------------------
1181# Device markers
1182#----------------------------------------------------------------
1183
1184 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1185 calma 65 13
1186
1187 layer POLYRES mrp1
1188 calma 66 13
1189
1190 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1191 layer POLYSHORT rmp
1192 calma 66 15
1193
1194 # POLYRES extends to edge of contact cut
1195 layer POLYRES xhrpoly,uhrpoly
1196 grow 60
1197 and xpc
1198 or xhrpoly,uhrpoly
1199 calma 66 13
1200
1201 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1202 # To be done: Expand to include anode, cathode, and guard ring
1203 calma 81 23
1204
1205#----------------------------------------------------------------
1206# LI
1207#----------------------------------------------------------------
1208 layer LI allli
1209 calma 67 20
1210
1211 layer LITXT
1212 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1213 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1214
1215 layer LIPIN
1216 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1217 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1218
1219 layer LIRES rli
1220 labels rli
1221 calma 67 13
1222
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1223 layer LIFILL lifill
1224 labels lifill
1225 calma 56 28
1226
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1227#----------------------------------------------------------------
1228# MCON
1229#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1230 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1231 squares-grid 0 170 190
1232 calma 67 44
1233
1234#----------------------------------------------------------------
1235# MET1
1236#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1237 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1238 calma 68 20
1239
1240 layer MET1TXT
1241 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1242 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1243
1244 layer MET1PIN
1245 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1246 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1247
1248 layer MET1RES rm1
1249 labels rm1
1250 calma 68 13
1251
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1252 layer MET1FILL m1fill
1253 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1254 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1255
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1256#----------------------------------------------------------------
1257# VIA1
1258#----------------------------------------------------------------
1259 layer VIA1 via1
1260 squares-grid 55 150 170
1261 calma 68 44
1262
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]1263#ifdef RERAM
1264#undef RERAM
1265 layer VIA1 reram
1266 squares-grid 55 150 170
1267 calma 68 44
1268
1269 layer RERAM reram
1270 squares-grid 55 230 230
1271 calma 201 20
1272#define RERAM
1273#endif (RERAM)
1274
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1275#----------------------------------------------------------------
1276# MET2
1277#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1278 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1279 calma 69 20
1280
1281 layer MET2TXT
1282 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1283 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1284
1285 layer MET2PIN
1286 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1287 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1288
1289 layer MET2RES rm2
1290 labels rm2
1291 calma 69 13
1292
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1293 layer MET2FILL m2fill
1294 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1295 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1296
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1297#----------------------------------------------------------------
1298# VIA2
1299#----------------------------------------------------------------
1300 layer VIA2 via2
1301 squares-grid 40 200 200
1302 calma 69 44
1303
1304#----------------------------------------------------------------
1305# MET3
1306#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1307 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1308 calma 70 20
1309
1310 layer MET3TXT
1311 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1312 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1313
1314 layer MET3PIN
1315 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1316 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1317
1318 layer MET3RES rm3
1319 labels rm3
1320 calma 70 13
1321
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1322 layer MET3FILL m3fill
1323 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1324 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1325
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1326#ifdef METAL5
1327#----------------------------------------------------------------
1328# VIA3
1329#----------------------------------------------------------------
1330 layer VIA3 via3
1331#ifdef MIM
1332 or mimcc
1333#endif (MIM)
1334 squares-grid 60 200 200
1335 calma 70 44
1336
1337#----------------------------------------------------------------
1338# MET4
1339#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1340 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1341 calma 71 20
1342
1343 layer MET4TXT
1344 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1345 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1346
1347 layer MET4PIN
1348 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1349 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1350
1351 layer MET4RES rm4
1352 labels rm4
1353 calma 71 13
1354
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1355 layer MET4FILL m4fill
1356 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1357 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1358
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1359#----------------------------------------------------------------
1360# VIA4
1361#----------------------------------------------------------------
1362 layer VIA4 via4
1363#ifdef MIM
1364 or mim2cc
1365#endif (MIM)
1366 squares-grid 190 800 800
1367 calma 71 44
1368
1369#----------------------------------------------------------------
1370# MET5
1371#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1372 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1373 calma 72 20
1374
1375 layer MET5TXT
1376 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1377 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1378
1379 layer MET5PIN
1380 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1381 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1382
1383 layer MET5RES rm5
1384 labels rm5
1385 calma 72 13
1386
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1387 layer MET5FILL m5fill
1388 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1389 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1390
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1391#endif (METAL5)
1392
1393#ifdef REDISTRIBUTION
1394#----------------------------------------------------------------
1395# RDL
1396#----------------------------------------------------------------
1397 layer RDL *metrdl
1398 calma 74 20
1399
1400 layer RDLTXT
1401 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1402 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1403
1404 layer RDLPIN
1405 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1406 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1407
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1408 layer PI1 *metrdl
1409 and padl,glass
1410 # Test only---needs GDS layer number
1411
1412 layer UBM *metrdl
1413 shrink 50000
1414 grow 40000
1415 # Test only---needs GDS layer number
1416
1417 layer PI2 *metrdl
1418 shrink 50000
1419 grow 25000
1420 # Test only---needs GDS layer number
1421
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1422#endif REDISTRIBUTION
1423
1424#----------------------------------------------------------------
1425# GLASS
1426#----------------------------------------------------------------
1427 layer GLASS glass
1428 calma 76 20
1429
1430#ifdef MIM
1431#----------------------------------------------------------------
1432# CAPM
1433#----------------------------------------------------------------
1434 layer CAPM *mimcap
1435 labels mimcap
1436 calma 89 44
1437
1438 layer CAPM2 *mimcap2
1439 labels mimcap2
1440 calma 97 44
1441#endif (MIM)
1442
1443#----------------------------------------------------------------
1444# Chip top level marker for DRC latchup rules to check 15um
1445# distance to taps (otherwise 6um is used)
1446#----------------------------------------------------------------
1447
1448 layer LOWTAPDENSITY
1449 bbox top
1450 # Clear 200um for pads + 50um for required high tap density
1451 # in critical area.
1452 shrink 250000
1453 calma 81 14
1454
1455#----------------------------------------------------------------
1456# FILLBLOCK
1457#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1458 layer FILLOBSFOM obsactive
1459 calma 22 24
1460
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1461 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1462 calma 62 24
1463
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1464 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1465 calma 105 52
1466
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1467 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1468 calma 107 24
1469
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1470 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1471 calma 112 4
1472
1473 render DNWELL cwell -0.1 0.1
1474 render NWELL nwell 0.0 0.2062
1475 render DIFF ndiffusion 0.2062 0.12
1476 render TAP pdiffusion 0.2062 0.12
1477 render POLY polysilicon 0.3262 0.18
1478 render CONT via 0.5062 0.43
1479 render LI metal1 0.9361 0.10
1480 render MCON via 1.0361 0.34
1481 render MET1 metal2 1.3761 0.36
1482 render VIA1 via 1.7361 0.27
1483 render MET2 metal3 2.0061 0.36
1484 render VIA2 via 2.3661 0.42
1485 render MET3 metal4 2.7861 0.845
1486#ifdef METAL5
1487 render VIA3 via 3.6311 0.39
1488 render MET4 metal5 4.0211 0.845
1489 render VIA4 via 4.8661 0.505
1490 render MET5 metal6 5.3711 1.26
1491 render CAPM metal8 2.4661 0.2
1492 render CAPM2 metal9 3.7311 0.2
1493#ifdef REDISTRIBUTION
1494 render RDL metal7 11.8834 4.0
1495#endif (!REDISTRIBUTION)
1496#endif (!METAL5)
1497
1498#----------------------------------------------------------------
1499style drc
1500#----------------------------------------------------------------
1501# NOTE: This style is used for DRC only, not for GDS output
1502#----------------------------------------------------------------
1503 scalefactor 10 nanometers
1504 options calma-permissive-labels
1505
1506 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1507 templayer dnwell_shrink dnwell
1508 shrink 1030
1509
1510 templayer nwell_missing dnwell
1511 grow 400
1512 and-not dnwell_shrink
1513 and-not nwell
1514
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1515 templayer pwell_in_dnwell dnwell
1516 and-not nwell
1517
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1518 # SONOS nFET devices must be in deep nwell
1519 templayer dnwell_missing nsonos
1520 and-not dnwell
1521
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1522 # SONOS nFET devices must be in cell with abutment box
1523 templayer abutment_box
1524 boundary
1525
1526 templayer bbox_missing nsonos
1527 and-not abutment_box
1528
1529 # Make sure nwell covers varactor poly
1530 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1531 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1532 grow 150
1533 and-not nwell
1534
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1535 # Define MiM cap bottom plate for spacing rule
1536 templayer mim_bottom
1537 bloat-all *mimcap *metal3
1538
1539 # Define MiM2 cap bottom plate for spacing rule
1540 templayer mim2_bottom
1541 bloat-all *mimcap2 *metal4
1542
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]1543 # Define areas where mim2cc is inside the boundary of mimcc
1544 # by more than the contact surround
1545 templayer mim2_contact_overlap
1546 bloat-all *mimcap2 mimcc
1547 shrink 60
1548 and-not *mimcap2
1549
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1550 # Note that metal fill is performed by the foundry and so is not
1551 # an option for a cifoutput style.
1552
1553 # Check latchup rule (15um minimum from tap LICON center to any
1554 # non-tap diffusion. Note that to count as a tap, the diffusion
1555 # must be contacted to LI
1556
1557 templayer ptap_reach psc,mvpsc
1558 and-not dnwell
1559 # grow total is 15um. grow in 0.84um increments to ensure that
1560 # no nwell ring is crossed
1561 grow 840
1562 and-not nwell,dnwell
1563 grow 840
1564 and-not nwell,dnwell
1565 grow 840
1566 and-not nwell,dnwell
1567 grow 840
1568 and-not nwell,dnwell
1569 grow 840
1570 and-not nwell,dnwell
1571 grow 840
1572 and-not nwell,dnwell
1573 grow 840
1574 and-not nwell,dnwell
1575 grow 840
1576 and-not nwell,dnwell
1577 grow 840
1578 and-not nwell,dnwell
1579 grow 840
1580 and-not nwell,dnwell
1581 grow 840
1582 and-not nwell,dnwell
1583 grow 840
1584 and-not nwell,dnwell
1585 grow 840
1586 and-not nwell,dnwell
1587 grow 840
1588 and-not nwell,dnwell
1589 grow 840
1590 and-not nwell,dnwell
1591 grow 840
1592 and-not nwell,dnwell
1593 grow 840
1594 and-not nwell,dnwell
1595 grow 635
1596 and-not nwell,dnwell
1597
1598 templayer ptap_missing *ndiff,*mvndiff
1599 and-not dnwell
1600 and-not ptap_reach
1601
1602 templayer ntap_reach nsc,mvnsc
1603 # grow total is 15um. grow in 1.27um increments to ensure that
1604 # no nwell ring is crossed. There is no difference between
1605 # ntaps in and out of deep nwell.
1606 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1607 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1608 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1609 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1610 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1611 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1612 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1613 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1614 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1615 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1616 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1617 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1618 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1619 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1620 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1621 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1622 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1623 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1624 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1625 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1626 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1627 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1628 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1629 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1630
1631 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1632 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1633 and-not ntap_reach
1634
1635 templayer dptap_reach psc,mvpsc
1636 and dnwell
1637 grow 840
1638 and-not nwell
1639 and dnwell
1640 grow 840
1641 and-not nwell
1642 and dnwell
1643 grow 840
1644 and-not nwell
1645 and dnwell
1646 grow 840
1647 and-not nwell
1648 and dnwell
1649 grow 840
1650 and-not nwell
1651 and dnwell
1652 grow 840
1653 and-not nwell
1654 and dnwell
1655 grow 840
1656 and-not nwell
1657 and dnwell
1658 grow 840
1659 and-not nwell
1660 and dnwell
1661 grow 840
1662 and-not nwell
1663 and dnwell
1664 grow 840
1665 and-not nwell
1666 and dnwell
1667 grow 840
1668 and-not nwell
1669 and dnwell
1670 grow 840
1671 and-not nwell
1672 and dnwell
1673 grow 840
1674 and-not nwell
1675 and dnwell
1676 grow 840
1677 and-not nwell
1678 and dnwell
1679 grow 840
1680 and-not nwell
1681 and dnwell
1682 grow 840
1683 and-not nwell
1684 and dnwell
1685 grow 840
1686 and-not nwell
1687 and dnwell
1688 grow 635
1689 and-not nwell
1690 and dnwell
1691
1692 templayer dptap_missing *ndiff,*mvndiff
1693 and dnwell
1694 and-not dptap_reach
1695
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1696 templayer pdiff_crosses_dnwell dnwell
1697 grow 20
1698 and-not dnwell
1699 and allpdifflv,allpdiffmv
1700
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1701 # MV nwell must be 2um from any other nwell
1702 templayer mvnwell
1703 bloat-all alldiffmv nwell
1704 grow-min 840
1705 bridge 700 600
1706
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1707 # Simple spacing checks to lvnwell must use CIF-DRC rule
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1708 # Note that HVI may *abut* lvnwell; this can only be handled
1709 # with mask-hints layers.
1710
1711 templayer drawn_hvi
1712 mask-hints HVI
1713
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1714 templayer allmvdiffnowell *mvndiff,*mvpsd
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]1715 and-not drawn_hvi
1716
1717 templayer nwell_or_hvi nwell,drawn_hvi
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1718
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1719 templayer lvnwell nwell
1720 and-not mvnwell
1721
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1722 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1723 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1724
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1725 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1726 and-not nwell_with_tap
1727
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1728 templayer tap_with_licon
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1729 bloat-all allpactivetap psd,mvpsd
1730 bloat-all allnactivetap nsd,mvnsd
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1731
Tim Edwardse27b6782021-08-05 15:26:07 -0400[diff] [blame]1732 templayer tap_missing_licon allnactivetap,allpactivetap
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1733 and-not tap_with_licon
1734
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1735 # Make sure varactor nwell contains no P diffusion
1736 templayer pdiff_in_varactor_well
1737 bloat-all varactor,mvvaractor nwell
1738 and allpactive
1739
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1740 # HVNTM spacing requires recreating HVNTM
1741 templayer hvntm_block *mvpsd
1742 grow 185
1743
1744 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1745 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1746 bloat-all mvvaractor *mvnsd
1747 and-not hvntm_block
1748 grow 185
1749 grow 345
1750 shrink 345
1751 and-not hvntm_block
1752
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1753 # RPM spacing checks require recreating RPM
1754 templayer rpm_generate
1755 bloat-all xhrpoly,uhrpoly xpc
1756 grow 200
1757 grow-min 1270
1758 grow 420
1759 shrink 420
1760
1761 # Check distance RPM to NSDM
1762 templayer rpm_nsd_check rpm_generate
1763 grow 325
1764 and allndifflv,allndiffmv
1765
1766 # Check distance RPM to (unrelated) POLY
1767 templayer rpm_poly_check rpm_generate
1768 grow 200
1769 and-not xhrpoly,uhrpoly,xpc
1770 and allpoly
1771
1772 # Check distance RPM to HVNTM
1773 templayer rpm_hvntm_check rpm_generate
1774 grow 385
1775 and allndiffmvnontap
1776
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1777 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1778 close 140000
1779
1780 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1781 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1782
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1783 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1784 close 140000
1785
1786 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1787 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1788
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1789 templayer m1_huge allm1
1790 shrink 1500
1791 grow 1500
1792
1793 templayer m1_large_halo m1_huge
1794 grow 280
1795 and-not m1_huge
1796 and allm1
1797
1798 templayer m2_huge allm2
1799 shrink 1500
1800 grow 1500
1801
1802 templayer m2_large_halo m2_huge
1803 grow 280
1804 and-not m2_huge
1805 and allm2
1806
1807 templayer m3_huge allm3
1808 shrink 1500
1809 grow 1500
1810
1811 templayer m3_large_halo m3_huge
1812 grow 400
1813 and-not m3_huge
1814 and allm3
1815
1816 templayer m4_huge allm4
1817 shrink 1500
1818 grow 1500
1819
1820 templayer m4_large_halo m4_huge
1821 grow 400
1822 and-not m4_huge
1823 and allm4
1824
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1825#ifdef EXPERIMENTAL
1826#----------------------------------------------------------------
1827style paint
1828#----------------------------------------------------------------
1829# NOTE: This style is used for database manipulations only via
1830# the "cif paint" command.
1831#----------------------------------------------------------------
1832
1833 scalefactor 10 nanometers
1834
1835 templayer m1grow *m1
1836 grow 290
1837
1838 # layer listrap: Use the following set of commands to strap local
1839 # interconnect wires with metal1 (inside the cursor box) to satisfy
1840 # the maximum aspect ratio rule for local interconnect:
1841 #
1842 # tech unlock *
1843 # cif ostyle paint
1844 # cif paint m1strap comment
1845 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1846 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1847 # erase comment
1848
1849 templayer m1strap *li
1850 and-not m1grow
1851 grow 30
1852
1853 templayer listrap comment
1854 slots 30 170 170 60
1855
1856#endif (EXPERIMENTAL)
1857
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1858#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1859style density
1860#----------------------------------------------------------------
1861# Style used by scripts to check for fill density
1862#----------------------------------------------------------------
1863 scalefactor 10 nanometers
1864 options calma-permissive-labels
1865 gridlimit 5
1866
1867 templayer fom_all alldiff,fomfill
1868
1869 templayer poly_all allpoly,polyfill
1870
1871 templayer li_all allli,lifill
1872
1873 templayer m1_all allm1,m1fill
1874
1875 templayer m2_all allm2,m2fill
1876
1877 templayer m3_all allm3,m3fill
1878
1879 templayer m4_all allm4,m4fill
1880
1881 templayer m5_all allm5,m5fill
1882
1883#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1884style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1885#----------------------------------------------------------------
1886# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1887# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1888#----------------------------------------------------------------
1889 scalefactor 10 nanometers
1890 options calma-permissive-labels
1891 gridlimit 5
1892
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1893#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1894# Generate and retain a layer representing the bounding box.
1895#
1896# For variant ():
1897# The bounding box is the full extent of geometry on the top level
1898# cell.
1899#
1900# For variant (tiled):
1901# Use with a script that breaks layout into flattened tiles and runs
1902# fill individually on each. The tiles should be larger than the
1903# step size, and each should draw a layer "comment" the size of the
1904# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1905#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1906
1907 variants ()
1908 templayer topbox
1909 bbox top
1910
1911 variants (tiled)
1912 templayer topbox comment
1913 # Each tile imposes the full keepout distance rule of
1914 # 3um on all sides.
1915 shrink 1500
1916
1917 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1918
1919#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1920# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1921# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1922# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1923# Enclosure by nwell = Diff/Tap 8 = 0.18um
1924#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1925
1926 templayer mvnwell
1927 bloat-all alldiffmv nwell
1928
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1929 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1930 and-not mvnwell
1931
1932 templayer well_shrink mvnwell
1933 shrink 250
1934 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1935 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1936 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1937 grow 340
1938 and-not well_shrink
1939
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1940#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1941# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1942#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1943 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1944 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1945 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1946 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1947
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1948 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1949 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1950 grow 1000
1951
1952#---------------------------------------------------
1953# FOM and POLY fill
1954#---------------------------------------------------
1955 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1956 # slots 0 4080 1320 0 4080 1320 1360 0
1957 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1958 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1959 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1960 shrink 2035
1961 grow 2035
1962
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1963#---------------------------------------------------
1964
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1965 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1966 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1967 or obstruct_poly
1968 templayer polyfill_pass1 topbox
1969 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1970 and-not obstruct_poly_pass1
1971 and topbox
1972 shrink 355
1973 grow 355
1974
1975#---------------------------------------------------
1976
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1977 templayer obstruct_fom_pass2 fomfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1978 grow 1290
1979 or polyfill_pass1
1980 grow 300
1981 or obstruct_fom
1982 templayer fomfill_pass2 topbox
1983 slots 0 2500 1320 0 2500 1320 1360 0
1984 and-not obstruct_fom_pass2
1985 and topbox
1986 shrink 1245
1987 grow 1245
1988
1989#---------------------------------------------------
1990
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1991 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1992 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]1993 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1994 grow 300
1995 or obstruct_poly
1996 templayer polyfill_coarse topbox
1997 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1998 and-not obstruct_poly_coarse
1999 and topbox
2000 shrink 355
2001 grow 355
2002
2003#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2004 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2005 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2006 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2007 grow 300
2008 or obstruct_poly
2009 templayer polyfill_medium topbox
2010 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2011 and-not obstruct_poly_medium
2012 and topbox
2013 shrink 265
2014 grow 265
2015
2016#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2017 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2018 grow 60
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2019 or fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2020 grow 300
2021 or obstruct_poly
2022 templayer polyfill_fine topbox
2023 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2024 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2025 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2026 shrink 235
2027 grow 235
2028
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2029#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2030
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2031 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2032 grow 1290
2033 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
2034 grow 300
2035 or obstruct_fom
2036 templayer fomfill_coarse topbox
2037 slots 0 1500 1320 0 1500 1320 1360 0
2038 and-not obstruct_fom_coarse
2039 and topbox
2040 shrink 745
2041 grow 745
2042
2043#---------------------------------------------------
2044
Tim Edwardsc3e47c62021-09-14 12:15:07 -0400[diff] [blame]2045 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2046 grow 1290
2047 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
2048 grow 300
2049 or obstruct_fom
2050 templayer fomfill_fine topbox
2051 slots 0 500 400 0 500 400 160 0
2052 and-not obstruct_fom_fine
2053 and topbox
2054 shrink 245
2055 grow 245
2056
2057#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2058 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2059 or fomfill_pass2
2060 or fomfill_coarse
2061 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2062 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2063
2064 layer POLYFILL polyfill_pass1
2065 or polyfill_coarse
2066 or polyfill_medium
2067 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2068 calma 28 28
2069
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2070#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2071# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2072# Note requirement that LI fill may not overlap (non-fill)
2073# diff or poly.
2074#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2075
2076 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2077 grow 2800
2078 or alldiff,allpoly
2079 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2080 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]2081 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]2082 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2083 and-not obstruct_li_coarse
2084 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2085 shrink 1495
2086 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2087
2088 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2089 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2090 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2091 grow 300
2092 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2093 grow 200
2094 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2095 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2096 and-not obstruct_li_medium
2097 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2098 shrink 745
2099 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2100
2101 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2102 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2103 grow 300
2104 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2105 grow 200
2106 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2107 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2108 and-not obstruct_li_fine
2109 and topbox
2110 shrink 285
2111 grow 285
2112
2113 layer LIFILL lifill_coarse
2114 or lifill_medium
2115 or lifill_fine
2116 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2117
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2118#---------------------------------------------------
2119# MET1 fill
2120#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2121
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2122 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2123 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2124 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2125 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2126 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2127 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2128 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2129 shrink 995
2130 grow 995
2131
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2132 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2133 grow 2800
2134 or met1fill_coarse
2135 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2136 templayer met1fill_medium topbox
2137 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2138 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2139 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2140 shrink 495
2141 grow 495
2142
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2143 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2144 grow 300
2145 or met1fill_coarse,met1fill_medium
2146 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2147 templayer met1fill_fine topbox
2148 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2149 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2150 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2151 shrink 285
2152 grow 285
2153
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2154 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2155 grow 100
2156 or met1fill_coarse,met1fill_medium,met1fill_fine
2157 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2158 templayer met1fill_veryfine topbox
2159 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2160 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2161 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2162 shrink 145
2163 grow 145
2164
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2165 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2166 or met1fill_medium
2167 or met1fill_fine
2168 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2169 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2170
2171#---------------------------------------------------
2172# MET2 fill
2173#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2174 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2175 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2176 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2177 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2178 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2179 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2180 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2181 shrink 995
2182 grow 995
2183
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2184 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2185 grow 2800
2186 or met2fill_coarse
2187 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2188 templayer met2fill_medium topbox
2189 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2190 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2191 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2192 shrink 495
2193 grow 495
2194
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2195 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2196 grow 300
2197 or met2fill_coarse,met2fill_medium
2198 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2199 templayer met2fill_fine topbox
2200 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2201 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2202 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2203 shrink 285
2204 grow 285
2205
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2206 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2207 grow 100
2208 or met2fill_coarse,met2fill_medium,met2fill_fine
2209 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2210 templayer met2fill_veryfine topbox
2211 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2212 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2213 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2214 shrink 145
2215 grow 145
2216
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2217 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2218 or met2fill_medium
2219 or met2fill_fine
2220 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2221 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2222
2223#---------------------------------------------------
2224# MET3 fill
2225#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2226 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2227 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2228 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2229 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2230 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2231 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2232 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2233 shrink 995
2234 grow 995
2235
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2236 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2237 grow 2700
2238 or met3fill_coarse
2239 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2240 templayer met3fill_medium topbox
2241 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2242 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2243 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2244 shrink 495
2245 grow 495
2246
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2247 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2248 grow 200
2249 or met3fill_coarse,met3fill_medium
2250 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2251 templayer met3fill_fine topbox
2252 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2253 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2254 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2255 shrink 285
2256 grow 285
2257
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2258 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2259 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2260 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2261 or met3fill_coarse,met3fill_medium,met3fill_fine
2262 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2263 templayer met3fill_veryfine topbox
2264 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2265 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2266 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2267 shrink 195
2268 grow 195
2269
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2270 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2271 or met3fill_medium
2272 or met3fill_fine
2273 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2274 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2275
2276#ifdef METAL5
2277#---------------------------------------------------
2278# MET4 fill
2279#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2280 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2281 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2282 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2283 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2284 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2285 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2286 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2287 shrink 995
2288 grow 995
2289
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2290 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2291 grow 2700
2292 or met4fill_coarse
2293 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2294 templayer met4fill_medium topbox
2295 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2296 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2297 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2298 shrink 495
2299 grow 495
2300
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2301 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2302 grow 200
2303 or met4fill_coarse,met4fill_medium
2304 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2305 templayer met4fill_fine topbox
2306 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2307 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2308 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2309 shrink 285
2310 grow 285
2311
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2312 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2313 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2314 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2315 or met4fill_coarse,met4fill_medium,met4fill_fine
2316 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2317 templayer met4fill_veryfine topbox
2318 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2319 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2320 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2321 shrink 195
2322 grow 195
2323
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2324 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2325 or met4fill_medium
2326 or met4fill_fine
2327 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2328 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2329
2330#---------------------------------------------------
2331# MET5 fill
2332#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2333 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2334 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2335 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2336 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2337 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2338 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2339 shrink 2495
2340 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2341
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2342 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2343 grow 1400
2344 or met5fill_coarse
2345 grow 1600
2346 templayer met5fill_medium topbox
2347 slots 0 3000 1600 0 3000 1600 1000 100
2348 and-not obstruct_m5_medium
2349 and topbox
2350 shrink 1495
2351 grow 1495
2352
2353 layer MET5FILL met5fill_coarse
2354 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2355 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2356#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2357
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2358end
2359
2360#-----------------------------------------------------------------------
2361cifinput
2362#-----------------------------------------------------------------------
2363# NOTE: All values in this section MUST be multiples of 25
2364# or else magic will scale below the allowed layout grid size
2365#-----------------------------------------------------------------------
2366
Tim Edwardsd7d8a102021-07-21 10:56:23 -0400[diff] [blame]2367style sky130 variants (vendor),()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2368 scalefactor 10 nanometers
2369 gridlimit 5
2370
2371 options ignore-unknown-layer-labels no-reconnect-labels
2372
2373#ifndef MIM
2374 ignore CAPM
2375 ignore CAPM2
2376#endif (!MIM)
2377#ifndef METAL5
2378 ignore MET4,VIA3
2379 ignore MET5,VIA4
2380#endif
2381 ignore NPC
2382 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2383 ignore CAPID
2384 ignore LDNTM
2385 ignore HVNTM
2386 ignore POLYMOD
2387 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2388 ignore FILLOBSPOLY
Tim Edwards19435622021-12-31 14:11:01 -0500[diff] [blame^]2389 ignore MET5BLOCK
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2390 ignore OUTLINE
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]2391 ignore POLYCUT
2392 ignore POLYGATE
2393 ignore DIFFCUT
2394 ignore HVNWELLID
2395 ignore PADDIFFID
2396 ignore PADMETALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2397
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2398 layer pnp NWELL,WELLTXT,WELLPIN
2399 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2400 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2401 variants (vendor)
2402 labels WELLTXT port
2403 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2404 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2405 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2406 labels WELLPIN port
2407
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2408 layer nwell NWELL,WELLTXT,WELLPIN
2409 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2410 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2411 variants (vendor)
2412 labels WELLTXT port
2413 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2414 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2415 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2416 labels WELLPIN port
2417
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2418 templayer nwellarea NWELL
2419 copyup nwelcheck
2420
2421 # Copy nwell areas up for diffusion checks
2422 templayer xnwelcheck nwelcheck
2423 copyup nwelcheck
2424
2425 templayer hvarea HVI
2426 copyup hvcheck
2427
2428 # Copy high-voltage (HVI) areas up for diffusion checks
2429 templayer xhvcheck hvcheck
2430 copyup hvcheck
2431
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2432 # Always draw pwell under p-tap and n-diff. This is not always
2433 # necessary but works better with deep nwell for correct extraction.
2434 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2435 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2436 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2437 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2438 grow 420
2439 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2440 variants (vendor)
2441 labels SUBTXT port
2442 variants ()
2443 labels SUBTXT text
2444 variants *
2445 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2446
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2447 layer dnwell DNWELL
2448 labels DNWELL
2449
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]2450 layer isosub SUBCUT
2451 labels SUBCUT
2452
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2453 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2454 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2455 and NPNID
2456
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]2457 layer photo DNWELL
2458 and PHOTO
2459
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2460 layer rpw PWRES
2461 and DNWELL
2462 labels PWRES
2463
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2464 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2465 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2466 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2467 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2468 and-not DIODE
2469 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2470 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2471 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2472 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2473 copyup ndifcheck
2474 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2475 variants (vendor)
2476 labels DIFFTXT port
2477 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2478 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2479 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2480 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2481
2482 layer ndiff ndiffarea
2483
2484 # Copy ndiff areas up for contact checks
2485 templayer xndifcheck ndifcheck
2486 copyup ndifcheck
2487
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2488 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2489 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2490 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2491 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2492 and-not DIODE
2493 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2494 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2495 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2496 copyup ndifcheck
2497 labels DIFF
2498 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2499 variants (vendor)
2500 labels DIFFTXT port
2501 variants ()
2502 labels DIFFTXT text
2503 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2504 labels DIFFPIN port
2505
2506 layer mvndiff mvndiffarea
2507
2508 # Copy ndiff areas up for contact checks
2509 templayer mvxndifcheck mvndifcheck
2510 copyup mvndifcheck
2511
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2512 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2513 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2514 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2515 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2516 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2517 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2518 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2519 and-not LVTN
2520 labels DIFF
2521
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2522 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2523 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2524 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2525 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2526 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2527 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2528 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2529 and LVTN
2530 labels DIFF
2531
2532 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2533 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2534 and-not HVI,hvcheck
2535 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2536 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2537
2538 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2539 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2540 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2541 labels DIFF
2542
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2543 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2544 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2545 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2546 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2547 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2548 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2549 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2550 copyup pdifcheck
2551 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2552 variants (vendor)
2553 labels DIFFTXT port
2554 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2555 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2556 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2557 labels DIFFPIN port
2558
2559 layer pdiff pdiffarea
2560
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2561 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2562 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2563 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2564 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2565 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2566 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2567 and-not LVTN
2568 labels DIFF
2569
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2570 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2571 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2572 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2573 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2574 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2575 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2576 and LVTN
2577 labels DIFF
2578
2579 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2580 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2581 and HVI,hvcheck
2582 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2583 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2584
2585 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2586 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2587 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2588 labels DIFF
2589
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2590 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2591 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2592 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2593 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2594 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2595 and-not DIODE
2596 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2597 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2598 copyup mvpdifcheck
2599 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2600 variants (vendor)
2601 labels DIFFTXT port
2602 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2603 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2604 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2605 labels DIFFPIN port
2606
2607 layer mvpdiff mvpdiffarea
2608
2609 # Copy pdiff areas up for contact checks
2610 templayer xpdifcheck pdifcheck
2611 copyup pdifcheck
2612
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2613 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2614 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2615 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2616 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2617 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2618 and-not LVTN
2619 and-not HVTP
2620 and DIODE
2621 labels DIFF
2622
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2623 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2624 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2625 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2626 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2627 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2628 and LVTN
2629 and-not HVTP
2630 and DIODE
2631 labels DIFF
2632
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2633 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2634 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2635 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2636 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2637 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2638 and-not LVTN
2639 and HVTP
2640 and DIODE
2641 labels DIFF
2642
2643 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2644 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2645 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2646 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2647
2648 # Define pfet areas as known pdiff, regardless of the presence of a well.
2649
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2650 templayer pfetarea DIFF,barediff
2651 and POLY
2652 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2653 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2654 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2655
2656 layer pfet pfetarea
2657 and-not LVTN
2658 and-not HVTP
2659 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2660 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2661 labels DIFF
2662
2663 layer scpfet pfetarea
2664 and-not LVTN
2665 and-not HVTP
2666 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2667 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2668 labels DIFF
2669
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2670 layer scpfethvt pfetarea
2671 and-not LVTN
2672 and HVTP
2673 and STDCELL
2674 labels DIFF
2675
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2676 layer ppu pfetarea
2677 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2678 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2679 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2680 # Shrink-grow operation eliminates the smaller parasitie device
2681 # shrink 70
2682 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2683 labels DIFF
2684
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2685 layer pfetlvt pfetarea
2686 and LVTN
2687 labels DIFF
2688
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2689 layer pfetmvt pfetarea
2690 and HVTR
2691 labels DIFF
2692
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2693 layer pfethvt pfetarea
2694 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2695 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2696 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2697 labels DIFF
2698
2699 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2700 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2701 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2702 grow 180
2703
2704 # Copy mvpdiff areas up for contact checks
2705 templayer mvxpdifcheck mvpdifcheck
2706 copyup mvpdifcheck
2707
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2708 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2709 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2710 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2711 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2712 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2713 and DIODE
2714 labels DIFF
2715
2716 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2717 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2718 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2719 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2720
2721 # Define pfet areas as known pdiff,
2722 # regardless of the presence of a
2723 # well.
2724
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2725 templayer mvpfetarea DIFF,barediff
2726 and POLY
2727 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2728 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2729 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2730
2731 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2732 and-not ESDID
2733 labels DIFF
2734
2735 layer mvpfetesd mvpfetarea
2736 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2737 labels DIFF
2738
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2739 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2740 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2741 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2742 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2743 and-not DIODE
2744 and-not DIFFRES
2745 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2746 variants (vendor)
2747 labels DIFFTXT port
2748 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2749 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2750 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2751 labels DIFFPIN port
2752
2753 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2754 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2755 and NWELL,nwelcheck
2756 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2757 labels DIFF
2758
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2759 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2760 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2761 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2762 and-not PSDM
2763 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2764 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2765 and-not LVTN
2766 and-not SONOS
2767 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2768 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2769 labels DIFF
2770
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2771 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2772 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2773 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2774 and-not PSDM
2775 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2776 and-not NWELL,nwelcheck
2777 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2778 and-not LVTN
2779 and-not SONOS
2780 and STDCELL
2781 labels DIFF
2782
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2783 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2784 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2785 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2786 and-not PSDM
2787 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2788 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2789 and COREID
2790 labels DIFF
2791
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2792 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2793 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2794 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2795 and-not PSDM
2796 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2797 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2798 and COREID
2799 # Shrink-grow operation eliminates the smaller npass device
2800 shrink 70
2801 grow 70
2802 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2803
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2804 # Devices abutting tap under gate are officially npd, not npass
2805 layer npd TAP
2806 grow 100
2807 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2809 and-not PSDM
2810 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2811 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2812 and COREID
2813 labels DIFF
2814
2815 layer nfetlvt DIFF,barediff
2816 and POLY
2817 or baretrans
2818 and-not PSDM
2819 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2820 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2821 and LVTN
2822 and-not SONOS
2823 labels DIFF
2824
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2825 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2826 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2827 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2828 and-not PSDM
2829 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2830 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2831 and LVTN
2832 and SONOS
2833 labels DIFF
2834
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2835 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2836 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2837 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2838 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2839 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2840 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2841 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2842 copyup nsubcheck
2843
2844 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2845 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2846
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2847 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2848 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2849 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2850 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2851 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2852 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2853
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2854 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2855 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2856 and POLY
2857 and COREID
2858 labels TAP
2859
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2860 templayer nsdexpand nsdarea
2861 grow 500
2862
2863 # Copy nsub areas up for contact checks
2864 templayer xnsubcheck nsubcheck
2865 copyup nsubcheck
2866
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2867 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2868 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2869 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2870 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2871 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2872 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2873 and-not pfetexpand
2874 copyup psubcheck
2875
2876 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2877 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2878
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2879 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2880 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2881 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2882 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2883 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2884 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2885
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2886 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2887 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2888 and POLY
2889 and COREID
2890 labels TAP
2891
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2892 templayer psdexpand psdarea
2893 grow 500
2894
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2895 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2896 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2897 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2898 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2899 and mvpfetexpand
2900 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2901 variants (vendor)
2902 labels DIFFTXT port
2903 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2904 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2905 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2906 labels DIFFPIN port
2907
2908 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2909 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2910 and NWELL,nwelcheck
2911 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2912 and-not mvrdpioedge
2913 labels DIFF
2914
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2915 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2916 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2917 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2918 and-not PSDM
2919 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2920 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2921 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2922 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2923
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2924 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2925 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2926 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2927 and-not PSDM
2928 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2929 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2930 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2931 and-not mvnfetarea
2932
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2933 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2934 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2935 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2936 and-not PSDM
2937 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2938 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2939 and ESDID
2940 and-not mvnnfetarea
2941 labels DIFF
2942
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2943 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2944 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2945 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2946 and-not PSDM
2947 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2948 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2949 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2950 and-not mvnnfetarea
2951 labels DIFF
2952
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2953 layer nnfet mvnnfetarea
2954 and LVID
2955 labels DIFF
2956
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2957 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2958 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2959 labels DIFF
2960
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2961 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2962 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2963 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2964 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2965 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2966 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2967 copyup mvnsubcheck
2968
2969 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2970 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2971
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2972 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2973 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2974 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2975 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2976 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2977
2978 templayer mvnsdexpand mvnsdarea
2979 grow 500
2980
2981 # Copy nsub areas up for contact checks
2982 templayer mvxnsubcheck mvnsubcheck
2983 copyup mvnsubcheck
2984
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2985 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2986 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2987 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2988 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2989 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2990 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2991 and-not mvpfetexpand
2992 copyup mvpsubcheck
2993
2994 layer mvpsd mvpsdarea
2995 labels DIFF
2996
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2997 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2998 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2999 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3000 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3001 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3002
3003 templayer mvpsdexpand mvpsdarea
3004 grow 500
3005
3006 # Copy psub areas up for contact checks
3007 templayer xpsubcheck psubcheck
3008 copyup psubcheck
3009
3010 templayer mvxpsubcheck mvpsubcheck
3011 copyup mvpsubcheck
3012
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3013 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3014 and-not PSDM
3015 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3016 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3017 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3018 and-not pfetexpand
3019 and psdexpand
3020
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3021 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3022 and-not PSDM
3023 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3024 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3025 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3026 and nsdexpand
3027
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3028 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3029 and-not PSDM
3030 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3031 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3032 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3033 and-not mvpfetexpand
3034 and mvpsdexpand
3035
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3036 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3037 and-not PSDM
3038 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3039 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3040 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3041 and mvnsdexpand
3042
3043 templayer hresarea POLY
3044 and RPM
3045 grow 3000
3046
3047 templayer uresarea POLY
3048 and URPM
3049 grow 3000
3050
3051 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3052 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3053 grow 3000
3054
3055 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3056 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3057 grow 3000
3058
3059 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
3060
3061 layer pfet POLY
3062 and DIFF
3063 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3064 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3065 and-not STDCELL
3066
3067 layer scpfet POLY
3068 and DIFF
3069 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3070 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3071 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3072 and STDCELL
3073
3074 layer scpfethvt POLY
3075 and DIFF
3076 and diffresarea
3077 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3078 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3079 and STDCELL
3080
3081 templayer xpolyterm RPM,URPM
3082 and POLY
3083 and-not POLYRES
3084 # add back the 0.06um contact surround in the direction of the resistor
3085 grow 60
3086 and POLY
3087
3088 layer xpc xpolyterm
3089
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3090 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3091 and-not POLYRES
3092 and-not POLYSHORT
3093 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3094 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3095 and-not RPM
3096 and-not URPM
3097 copyup polycheck
3098
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]3099 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3100 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3101 variants (vendor)
3102 labels POLYTXT port
3103 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3104 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3105 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3106 labels POLYPIN port
3107
3108 # Copy (non-resistor) poly areas up for contact checks
3109 templayer xpolycheck polycheck
3110 copyup polycheck
3111
3112 layer mrp1 POLY
3113 and POLYRES
3114 and-not RPM
3115 and-not URPM
3116 labels POLY
3117
3118 layer rmp POLY
3119 and POLYSHORT
3120 labels POLY
3121
3122 layer xhrpoly POLY
3123 and POLYRES
3124 and RPM
3125 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3126 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3127 and NPC
3128 and-not xpolyterm
3129 labels POLY
3130
3131 layer uhrpoly POLY
3132 and POLYRES
3133 and URPM
3134 and-not RPM
3135 and NPC
3136 and-not xpolyterm
3137 labels POLY
3138
3139 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3140 or barecont
3141 and LI
3142 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3143 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3144 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3145 and-not NWELL,nwelcheck
3146 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3147
3148 layer ndc ndcbase
3149 grow 85
3150 shrink 85
3151 shrink 85
3152 grow 85
3153 or ndcbase
3154 labels CONT
3155
3156 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3157 or barecont
3158 and LI
3159 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3160 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3161 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3162 and NWELL,nwelcheck
3163 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3164
3165 layer nsc nscbase
3166 grow 85
3167 shrink 85
3168 shrink 85
3169 grow 85
3170 or nscbase
3171 labels CONT
3172
3173 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3174 or barecont
3175 and LI
3176 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3177 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3178 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3179 and NWELL,nwelcheck
3180 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3181
3182 layer pdc pdcbase
3183 grow 85
3184 shrink 85
3185 shrink 85
3186 grow 85
3187 or pdcbase
3188 labels CONT
3189
3190 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3191 or barecont
3192 and LI
3193 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3194 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3195 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3196 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3197 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3198
3199 layer pdc pdcnowell
3200 grow 85
3201 shrink 85
3202 shrink 85
3203 grow 85
3204 or pdcnowell
3205 labels CONT
3206
3207 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3208 or barecont
3209 and LI
3210 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3211 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3212 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3213 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3214 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3215 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3216
3217 layer psc pscbase
3218 grow 85
3219 shrink 85
3220 shrink 85
3221 grow 85
3222 or pscbase
3223 labels CONT
3224
3225 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3226 or barecont
3227 and LI
3228 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3229 and POLY
3230 and-not DIFF
3231 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3232
3233 layer pc pcbase
3234 grow 85
3235 shrink 85
3236 shrink 85
3237 grow 85
3238 or pcbase
3239 labels CONT
3240
3241 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3242 or barecont
3243 and LI
3244 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3245 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3246 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3247 and DIODE
3248 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3249 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3250 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3251 and-not LVTN
3252
3253 layer ndic ndicbase
3254 grow 85
3255 shrink 85
3256 shrink 85
3257 grow 85
3258 or ndicbase
3259 labels CONT
3260
3261 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3262 or barecont
3263 and LI
3264 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3265 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3266 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3267 and DIODE
3268 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3269 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3270 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3271 and LVTN
3272
3273 layer ndilvtc ndilvtcbase
3274 grow 85
3275 shrink 85
3276 shrink 85
3277 grow 85
3278 or ndilvtcbase
3279 labels CONT
3280
3281 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3282 or barecont
3283 and LI
3284 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3285 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3286 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3287 and DIODE
3288 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3289 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3290 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3291 and-not LVTN
3292 and-not HVTP
3293
3294 layer pdic pdicbase
3295 grow 85
3296 shrink 85
3297 shrink 85
3298 grow 85
3299 or pdicbase
3300 labels CONT
3301
3302 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3303 or barecont
3304 and LI
3305 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3306 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3307 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3308 and DIODE
3309 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3310 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3311 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3312 and LVTN
3313 and-not HVTP
3314
3315 layer pdilvtc pdilvtcbase
3316 grow 85
3317 shrink 85
3318 shrink 85
3319 grow 85
3320 or pdilvtcbase
3321 labels CONT
3322
3323 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3324 or barecont
3325 and LI
3326 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3327 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3328 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3329 and DIODE
3330 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3331 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3332 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3333 and-not LVTN
3334 and HVTP
3335
3336 layer pdihvtc pdihvtcbase
3337 grow 85
3338 shrink 85
3339 shrink 85
3340 grow 85
3341 or pdihvtcbase
3342 labels CONT
3343
3344 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3345 or barecont
3346 and LI
3347 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3348 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3349 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3350 and-not NWELL,nwelcheck
3351 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3352
3353 layer mvndc mvndcbase
3354 grow 85
3355 shrink 85
3356 shrink 85
3357 grow 85
3358 or mvndcbase
3359 labels CONT
3360
3361 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3362 or barecont
3363 and LI
3364 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3365 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3366 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3367 and NWELL,nwelcheck
3368 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3369
3370 layer mvnsc mvnscbase
3371 grow 85
3372 shrink 85
3373 shrink 85
3374 grow 85
3375 or mvnscbase
3376 labels CONT
3377
3378 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3379 or barecont
3380 and LI
3381 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3382 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3383 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3384 and NWELL,nwelcheck
3385 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3386
3387 layer mvpdc mvpdcbase
3388 grow 85
3389 shrink 85
3390 shrink 85
3391 grow 85
3392 or mvpdcbase
3393 labels CONT
3394
3395 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3396 or barecont
3397 and LI
3398 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3399 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3400 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3401 and mvpfetexpand
3402 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3403 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3404
3405 layer mvpdc mvpdcnowell
3406 grow 85
3407 shrink 85
3408 shrink 85
3409 grow 85
3410 or mvpdcnowell
3411 labels CONT
3412
3413 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3414 or barecont
3415 and LI
3416 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3417 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3418 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3419 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3420 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3421 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3422
3423 layer mvpsc mvpscbase
3424 grow 85
3425 shrink 85
3426 shrink 85
3427 grow 85
3428 or mvpscbase
3429 labels CONT
3430
3431 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3432 or barecont
3433 and LI
3434 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3435 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3436 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3437 and DIODE
3438 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3439 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3440 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3441 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3442
3443 layer mvndic mvndicbase
3444 grow 85
3445 shrink 85
3446 shrink 85
3447 grow 85
3448 or mvndicbase
3449 labels CONT
3450
3451 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3452 or barecont
3453 and LI
3454 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3455 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3456 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3457 and DIODE
3458 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3459 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3460 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3461 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3462
3463 layer nndic nndicbase
3464 grow 85
3465 shrink 85
3466 shrink 85
3467 grow 85
3468 or nndicbase
3469 labels CONT
3470
3471 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3472 or barecont
3473 and LI
3474 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3475 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3476 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3477 and DIODE
3478 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3479 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3480 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3481
3482 layer mvpdic mvpdicbase
3483 grow 85
3484 shrink 85
3485 shrink 85
3486 grow 85
3487 or mvpdicbase
3488 labels CONT
3489
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3490 layer fomfill FOMFILL
3491 labels FOMFILL
3492
3493 layer polyfill POLYFILL
3494 labels POLYFILL
3495
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3496 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3497 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3498 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3499 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3500 variants (vendor)
3501 labels LITXT port
3502 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3503 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3504 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3505 labels LIPIN port
3506
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3507 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3508 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3509 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3510 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3511 variants (vendor)
3512 labels LITXT port
3513 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3514 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3515 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3516 labels LIPIN port
3517
3518 layer rli LI
3519 and LIRES,LISHORT
3520 labels LIRES,LISHORT
3521
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3522 layer lifill LIFILL
3523 labels LIFILL
3524
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3525 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3526 grow 95
3527 shrink 95
3528 shrink 85
3529 grow 85
3530 or MCON
3531 labels MCON
3532
3533 layer m1 MET1,MET1TXT,MET1PIN
3534 and-not MET1RES,MET1SHORT
3535 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3536 variants (vendor)
3537 labels MET1TXT port
3538 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3539 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3540 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3541 labels MET1PIN port
3542
3543 layer rm1 MET1
3544 and MET1RES,MET1SHORT
3545 labels MET1RES,MET1SHORT
3546
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3547 layer m1fill MET1FILL
3548 labels MET1FILL
3549
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3550#ifdef MIM
3551 layer mimcap MET3
3552 and CAPM
3553 labels CAPM
3554
3555 layer mimcc VIA3
3556 and CAPM
3557 grow 60
3558 grow 40
3559 shrink 40
3560 labels CAPM
3561
3562 layer mimcap2 MET4
3563 and CAPM2
3564 labels CAPM2
3565
3566 layer mim2cc VIA4
3567 and CAPM2
3568 grow 190
3569 grow 210
3570 shrink 210
3571 labels CAPM2
3572
3573#endif (MIM)
3574
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3575#ifdef RERAM
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3576#undef RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3577 layer reram RERAM
3578 and VIA1
3579 grow 55
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3580#define RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]3581#endif (RERAM)
3582
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3583 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3584 and-not COREID
3585 grow 5
3586 or VIA1
3587 grow 50
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]3588#ifdef RERAM
3589#undef RERAM
3590 and-not RERAM
3591#define RERAM
3592#endif (RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3593
3594 layer m2c m2cbase
3595 grow 30
3596 shrink 30
3597 shrink 130
3598 grow 130
3599 or m2cbase
3600
3601 layer m2 MET2,MET2TXT,MET2PIN
3602 and-not MET2RES,MET2SHORT
3603 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3604 variants (vendor)
3605 labels MET2TXT port
3606 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3607 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3608 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3609 labels MET2PIN port
3610
3611 layer rm2 MET2
3612 and MET2RES,MET2SHORT
3613 labels MET2RES,MET2SHORT
3614
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3615 layer m2fill MET2FILL
3616 labels MET2FILL
3617
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3618 templayer m3cbase VIA2
3619 grow 40
3620
3621 layer m3c m3cbase
3622 grow 60
3623 shrink 60
3624 shrink 140
3625 grow 140
3626 or m3cbase
3627
3628 layer m3 MET3,MET3TXT,MET3PIN
3629 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3630 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3631 variants (vendor)
3632 labels MET3TXT port
3633 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3634 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3635 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3636 labels MET3PIN port
3637
3638 layer rm3 MET3
3639 and MET3RES,MET3SHORT
3640 labels MET3RES,MET3SHORT
3641
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3642 layer m3fill MET3FILL
3643 labels MET3FILL
3644
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3645#ifdef (METAL5)
3646
3647 templayer via3base VIA3
3648#ifdef MIM
3649 and-not CAPM
3650#endif (MIM)
3651 grow 60
3652
3653 layer via3 via3base
3654 grow 40
3655 shrink 40
3656 shrink 160
3657 grow 160
3658 or via3base
3659
3660 layer m4 MET4,MET4TXT,MET4PIN
3661 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3662 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3663 variants (vendor)
3664 labels MET4TXT port
3665 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3666 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3667 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3668 labels MET4PIN port
3669
3670 layer rm4 MET4
3671 and MET4RES,MET4SHORT
3672 labels MET4RES,MET4SHORT
3673
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3674 layer m4fill MET4FILL
3675 labels MET4FILL
3676
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3677 layer m5 MET5,MET5TXT,MET5PIN
3678 and-not MET5RES,MET5SHORT
3679 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3680 variants (vendor)
3681 labels MET5TXT port
3682 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3683 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3684 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3685 labels MET5PIN port
3686
3687 layer rm5 MET5
3688 and MET5RES,MET5SHORT
3689 labels MET5RES,MET5SHORT
3690
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3691 layer m5fill MET5FILL
3692 labels MET5FILL
3693
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3694 templayer via4base VIA4
3695#ifdef MIM
3696 and-not CAPM2
3697#endif (MIM)
3698 grow 190
3699
3700 layer via4 via4base
3701 grow 210
3702 shrink 210
3703 shrink 590
3704 grow 590
3705 or via4base
3706#endif (METAL5)
3707
3708#ifdef REDISTRIBUTION
3709 layer metrdl RDL,RDLTXT,RDLPIN
3710 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3711 variants (vendor)
3712 labels RDLTXT port
3713 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3714 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3715 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3716 labels RDLPIN port
3717#endif
3718
3719 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3720 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3721 # the next layer up
3722
3723 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3724 and-not PSDM
3725 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3726 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3727 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3728
3729 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3730 and-not PSDM
3731 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3732 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3733 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3734 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3735
3736 # Handle contacts found by copyup
3737
3738 templayer ndiccopy CONT
3739 and LI
3740 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3741 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3742 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3743
3744 layer ndic ndiccopy
3745 grow 85
3746 shrink 85
3747 shrink 85
3748 grow 85
3749 or ndiccopy
3750 labels CONT
3751
3752 templayer mvndiccopy CONT
3753 and LI
3754 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3755 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3756 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3757
3758 layer mvndic mvndiccopy
3759 grow 85
3760 shrink 85
3761 shrink 85
3762 grow 85
3763 or mvndiccopy
3764 labels CONT
3765
3766 templayer pdiccopy CONT
3767 and LI
3768 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3769 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3770 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3771
3772 layer pdic pdiccopy
3773 grow 85
3774 shrink 85
3775 shrink 85
3776 grow 85
3777 or pdiccopy
3778 labels CONT
3779
3780 templayer mvpdiccopy CONT
3781 and LI
3782 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3783 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3784 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3785
3786 layer mvpdic mvpdiccopy
3787 grow 85
3788 shrink 85
3789 shrink 85
3790 grow 85
3791 or mvpdiccopy
3792 labels CONT
3793
3794 templayer ndccopy CONT
3795 and ndifcheck
3796
3797 layer ndc ndccopy
3798 grow 85
3799 shrink 85
3800 shrink 85
3801 grow 85
3802 or ndccopy
3803 labels CONT
3804
3805 templayer mvndccopy CONT
3806 and mvndifcheck
3807
3808 layer mvndc mvndccopy
3809 grow 85
3810 shrink 85
3811 shrink 85
3812 grow 85
3813 or mvndccopy
3814 labels CONT
3815
3816 templayer pdccopy CONT
3817 and pdifcheck
3818
3819 layer pdc pdccopy
3820 grow 85
3821 shrink 85
3822 shrink 85
3823 grow 85
3824 or pdccopy
3825 labels CONT
3826
3827 templayer mvpdccopy CONT
3828 and mvpdifcheck
3829
3830 layer mvpdc mvpdccopy
3831 grow 85
3832 shrink 85
3833 shrink 85
3834 grow 85
3835 or mvpdccopy
3836 labels CONT
3837
3838 templayer pccopy CONT
3839 and polycheck
3840
3841 layer pc pccopy
3842 grow 85
3843 shrink 85
3844 shrink 85
3845 grow 85
3846 or pccopy
3847 labels CONT
3848
3849 templayer nsccopy CONT
3850 and nsubcheck
3851
3852 layer nsc nsccopy
3853 grow 85
3854 shrink 85
3855 shrink 85
3856 grow 85
3857 or nsccopy
3858 labels CONT
3859
3860 templayer mvnsccopy CONT
3861 and mvnsubcheck
3862
3863 layer mvnsc mvnsccopy
3864 grow 85
3865 shrink 85
3866 shrink 85
3867 grow 85
3868 or mvnsccopy
3869 labels CONT
3870
3871 templayer psccopy CONT
3872 and psubcheck
3873
3874 layer psc psccopy
3875 grow 85
3876 shrink 85
3877 shrink 85
3878 grow 85
3879 or psccopy
3880 labels CONT
3881
3882 templayer mvpsccopy CONT
3883 and mvpsubcheck
3884
3885 layer mvpsc mvpsccopy
3886 grow 85
3887 shrink 85
3888 shrink 85
3889 grow 85
3890 or mvpsccopy
3891 labels CONT
3892
3893 # Find contacts not covered in
3894 # metal and pull them into the
3895 # next layer up
3896
3897 templayer gencont CONT
3898 and LI
3899 and-not DIFF,TAP
3900 and-not POLY
3901 and-not DIODE
3902 and-not nsubcheck
3903 and-not psubcheck
3904 and-not mvnsubcheck
3905 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3906 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3907 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3908
3909 templayer barecont CONT
3910 and-not LI
3911 and-not nsubcheck
3912 and-not psubcheck
3913 and-not mvnsubcheck
3914 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3915 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3916 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3917
3918 layer glass GLASS,PADTXT,PADPIN
3919 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3920 variants (vendor)
3921 labels PADTXT port
3922 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3923 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3924 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3925 labels PADPIN port
3926
3927 templayer boundary BOUND,STDCELL,PADCELL
3928 boundary
3929
3930 layer comment LVSTEXT
3931 labels LVSTEXT text
3932
3933 layer comment TTEXT
3934 labels TTEXT text
3935
3936 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3937 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3938
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3939 layer obsactive FILLOBSFOM
3940
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3941# MOS Varactor
3942
3943 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3944 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3945 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3946 and NWELL,nwelcheck
3947 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3948 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3949 # NOTE: Else forms a varactor that is not in the vendor netlist.
3950 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3951 labels POLY
3952
3953 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3954 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3955 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3956 and NWELL,nwelcheck
3957 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3958 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3959 labels POLY
3960
3961 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3962 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3963 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3964 and NWELL,nwelcheck
3965 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3966 labels POLY
3967
3968 calma NWELL 64 20
3969 calma DIFF 65 20
3970 calma DNWELL 64 18
Tim Edwardsb4bd4f92021-07-07 09:51:31 -0400[diff] [blame]3971 calma SUBCUT 81 53
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3972 calma PWRES 64 13
3973 calma TAP 65 44
3974 # LVTN
3975 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3976 # HVTR
3977 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3978 # HVTP
3979 calma HVTP 78 44
3980 # SONOS (TUNM)
3981 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3982 # NSDM (NPLUS)
3983 calma NSDM 93 44
3984 # PSDM (PPLUS)
3985 calma PSDM 94 20
3986 # HVI (THKOX)
3987 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3988 # NPC
3989 calma NPC 95 20
3990 # P+ POLY MASK
3991 calma RPM 86 20
3992 calma URPM 79 20
3993 calma LDNTM 11 44
3994 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3995 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3996 calma POLYRES 66 13
3997 # Diffusion resistor ID mark
3998 calma DIFFRES 65 13
3999 calma POLY 66 20
4000 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4001 # 3.3V native FET ID mark
4002 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4003 # Diode ID mark
4004 calma DIODE 81 23
4005 # Bipolar NPN mark
4006 calma NPNID 82 20
4007 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4008 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4009 # Capacitor ID
4010 calma CAPID 82 64
4011 # Core area ID mark
4012 calma COREID 81 2
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]4013 # Photodiode ID mark
4014 calma PHOTO 81 81
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4015 # Standard cell ID mark
4016 calma STDCELL 81 4
4017 # Padframe cell ID mark
4018 calma PADCELL 81 3
4019 # Seal ring ID mark
4020 calma SEALID 81 1
4021 # Low tap density ID mark
4022 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4023 # ESD area ID
4024 calma ESDID 81 19
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]4025 # Various unused layers
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]4026 calma OUTLINE 236 0
Tim Edwardsb8f8fa22021-12-31 13:51:35 -0500[diff] [blame]4027 calma POLYCUT 66 14
4028 calma POLYGATE 66 9
4029 calma DIFFCUT 65 14
4030 calma HVNWELLID 81 63
4031 calma MET5BLOCK 72 10
4032 calma PADDIFFID 81 6
4033 calma PADMETALID 81 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4034
4035 # LICON
4036 calma CONT 66 44
4037 calma LI 67 20
4038 calma MCON 67 44
4039
4040 calma MET1 68 20
4041 calma VIA1 68 44
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4042#ifdef RERAM
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]4043#undef RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4044 calma RERAM 201 20
Tim Edwards624f7962021-12-23 10:34:55 -0500[diff] [blame]4045#define RERAM
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4046#endif (RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4047 calma MET2 69 20
4048 calma VIA2 69 44
4049 calma MET3 70 20
4050#ifdef METAL5
4051 calma VIA3 70 44
4052 calma MET4 71 20
4053 calma VIA4 71 44
4054 calma MET5 72 20
4055#endif
4056#ifdef REDISTRIBUTION
4057 calma RDL 74 20
4058#endif
4059 calma GLASS 76 20
4060
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4061 calma SUBTXT 64 59
4062 calma PADTXT 76 5
4063 calma DIFFTXT 65 6
4064 calma TAPTXT 65 5
4065 calma WELLTXT 64 5
4066 calma LITXT 67 5
4067 calma POLYTXT 66 5
4068 calma MET1TXT 68 5
4069 calma MET2TXT 69 5
4070 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4071#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4072 calma MET4TXT 71 5
4073 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4074#endif
4075#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4076 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4077#endif
4078
4079 calma LIRES 67 13
4080 calma MET1RES 68 13
4081 calma MET2RES 69 13
4082 calma MET3RES 70 13
4083#ifdef METAL5
4084 calma MET4RES 71 13
4085 calma MET5RES 72 13
4086#endif
4087
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4088 calma LIFILL 56 28
4089 calma MET1FILL 36 28
4090 calma MET2FILL 41 28
4091 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4092#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4093 calma MET4FILL 51 28
4094 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4095#endif
4096
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4097 calma POLYSHORT 66 15
4098 calma LISHORT 67 15
4099 calma MET1SHORT 68 15
4100 calma MET2SHORT 69 15
4101 calma MET3SHORT 70 15
4102#ifdef METAL5
4103 calma MET4SHORT 71 15
4104 calma MET5SHORT 72 15
4105#endif
4106
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4107 calma SUBPIN 122 16
4108 calma PADPIN 76 16
4109 calma DIFFPIN 65 16
4110 calma POLYPIN 66 16
4111 calma WELLPIN 64 16
4112 calma LIPIN 67 16
4113 calma MET1PIN 68 16
4114 calma MET2PIN 69 16
4115 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4116#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]4117 calma MET4PIN 71 16
4118 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4119#endif
4120#ifdef REDISTRIBUTION
4121 calma RDLPIN 74 16
4122#endif
4123
4124 calma BOUND 235 4
4125
4126 calma LVSTEXT 83 44
4127
4128#ifdef (MIM)
4129 calma CAPM 89 44
4130 calma CAPM2 97 44
4131#endif (MIM)
4132
4133 calma FILLOBSM1 62 24
4134 calma FILLOBSM2 105 52
4135 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]4136 calma FILLOBSM4 112 4
4137 calma FILLOBSFOM 22 24
4138 calma FILLOBSPOLY 33 24
4139
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]4140 calma FOMFILL 23 28
4141 calma POLYFILL 28 28
4142 calma LIFILL 56 28
4143 calma MET1FILL 36 28
4144 calma MET2FILL 41 28
4145 calma MET3FILL 34 28
4146 calma MET4FILL 51 28
4147 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4148
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4149#-----------------------------------------------------------------------
4150
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4151style rdlimport
4152 # This style is for reading shapes generated with the RDL layers
4153
4154 scalefactor 10 nanometers
4155 gridlimit 5
4156
4157 options ignore-unknown-layer-labels no-reconnect-labels
4158
4159 layer mrdl RDL
4160 layer mrdlc RDLC
4161
4162 calma RDL 10 0
4163 calma RDLC 20 0
4164
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4165end
4166
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4167#-----------------------------------------------------
4168# Digital flow maze router cost parameters
4169#-----------------------------------------------------
4170
4171mzrouter
4172end
4173
4174#-----------------------------------------------------
4175# Vendor DRC rules
4176#-----------------------------------------------------
4177
4178drc
4179
4180 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4181 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4182 cifstyle drc
4183
4184 variants (fast),(full)
4185
4186#-----------------------------
4187# DNWELL
4188#-----------------------------
4189
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4190 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4191 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4192 spacing allnwell dnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4193 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4194
4195 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4196 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4197 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4198 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4199 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4200
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4201 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4202 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4203 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4204
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]4205 width photo 3000 "Photodiode width < %d (photo.2)"
4206 spacing photo photo 5000 touching_ok "Photodiode spacing < %d (photo.3)"
4207 spacing photo dnwell 5300 touching_illegal \
4208 "Photodiode spacing to deep nwell < %d (photo.4)"
4209
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4210#-----------------------------
4211# NWELL
4212#-----------------------------
4213
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4214 width allnwell 840 "N-well width < %d (nwell.1)"
4215 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4216
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4217 variants (full)
4218 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4219 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4220
4221 cifspacing mvnwell lvnwell 2000 touching_illegal \
4222 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4223 cifspacing mvnwell mvnwell 2000 touching_ok \
4224 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4225 variants (fast),(full)
4226
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4227#-----------------------------
4228# DIFF
4229#-----------------------------
4230
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4231 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4232 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4233 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4234 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4235
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4236 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4237 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4238 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4239 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4240 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4241 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4242 spacing alldifflv,var,varhvt,corenvar,corepvar,fomfill \
4243 alldifflv,var,varhvt,corenvar,corepvar,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4244 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwardsada35632021-08-19 21:00:32 -0400[diff] [blame]4245 spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \
4246 "LV to MV Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4247 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4248 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4249 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4250 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4251 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4252 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4253 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4254 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4255 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4256 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4257 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4258 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4259 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4260 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4261 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4262 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4263 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4264 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4265 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4266 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4267 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4268 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4269 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4270 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4271 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4272 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4273 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4274 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4275
4276variants (full)
4277 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4278 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
Tim Edwardsf6a94bd2021-06-01 11:02:58 -0400[diff] [blame]4279 cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \
4280 "HVI to HVI or LV nwell spacing < %d (hvi.5)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4281variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4282
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4283 spacing allnfets allpactivenonfet 270 touching_illegal \
4284 "nFET cannot abut P-diffusion (diff/tap.3)"
4285 spacing allpfets allnactivenonfet 270 touching_illegal \
4286 "pFET cannot abut N-diffusion (diff/tap.3)"
4287
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4288 # Butting junction rules
4289 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4290 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4291 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4292 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4293 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4294 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4295 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4296 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4297
4298 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4299 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4300 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4301 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4302 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4303 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4304 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4305 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4306
4307 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4308 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4309 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4310
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4311 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4312 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4313
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4314 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4315
4316 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4317 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4318
4319 # Latchup rules
4320 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4321 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4322 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4323 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4324 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4325 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4326
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4327 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4328
4329#-----------------------------
4330# POLY
4331#-----------------------------
4332
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4333 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4334 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4335
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4336 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4337 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4338 75 corner_ok allfets \
4339 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4340 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4341 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards434a0852021-11-17 16:36:15 -0500[diff] [blame]4342 overhang *ndiff,rndiff nfet,scnfet,npd,npass,nsonos 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4343 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4344 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4345 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4346 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4347 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4348 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4349 rect_only allfets "No bends in transistors (poly.11)"
4350 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4351 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4352 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4353 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4354 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4355
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4356 variants (fast)
4357
4358 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4359 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4360 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4361 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4362 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4363 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4364
4365 # Minimum width requirement means actual spacing from res to ndiff has to be
4366 # constructed from mask rules. These supercede the simpler checks.
4367
4368 variants (full)
4369
4370 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4371 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4372 cifmaxwidth rpm_poly_check 0 bend_illegal \
4373 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4374 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4375 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4376
Tim Edwards75dea452021-05-08 15:55:26 -0400[diff] [blame]4377 variants (fast),(full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4378
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4379 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4380
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4381#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4382# HVTP
4383#--------------------------------------------------------------------
4384
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4385 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4386 360 touching_illegal \
4387 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4388
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4389 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4390 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4391
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4392#--------------------------------------------------------------------
4393# LVTN
4394#--------------------------------------------------------------------
4395
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4396 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4397 allfetsnolvt 360 touching_illegal \
4398 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4399
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4400 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4401 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4402 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4403
4404 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4405 edge4way allfetsnolvt allactivenonfet 415 \
4406 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4407 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4408
4409#--------------------------------------------------------------------
4410# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4411#--------------------------------------------------------------------
4412
4413# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4414
4415#--------------------------------------------------------------------
4416# CONT (LICON, contact between poly/diff and LI)
4417#--------------------------------------------------------------------
4418
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4419 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4420 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4421 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4422 width psc/li 170 "P-tap contact width < %d (licon.1)"
4423 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4424 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4425 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4426
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4427 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4428 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4429 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4430
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4431 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4432 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4433 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4434 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4435 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4436 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4437
4438 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4439 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4440 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4441 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4442 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4443 "Diffusion contact spacing < %d (licon.2)"
4444 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4445
4446 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4447 "poly contact spacing to diffusion < %d (licon.14)"
4448 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4449 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4450
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4451 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4452 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4453 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4454 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4455 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4456 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards7261d722021-11-17 16:44:27 -0500[diff] [blame]4457 spacing ndc,pdc nsonos 75 touching_illegal \
4458 "Diffusion contact to SONOS gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4459 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4460 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4461 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4462 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4463 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4464 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4465
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4466 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4467 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4468 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4469 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4470 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4471 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4472 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4473 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4474 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4475
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4476 spacing psc/a allnactivenontap 60 touching_illegal \
4477 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4478 spacing nsc/a allpactivenontap 60 touching_illegal \
4479 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4480
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4481 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4482 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4483 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4484 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4485 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4486 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4487 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4488 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4489 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4490
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4491 surround nsc/a *nsd,corenvar 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4492 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwardsf2997092021-11-18 11:54:17 -0500[diff] [blame]4493 surround psc/a *psd,corepvar 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4494 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4495
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4496 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4497 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4498 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4499 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4500 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4501 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4502 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4503 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4504
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4505 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4506 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4507 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4508 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4509
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4510 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4511 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4512 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4513 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4514 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4515 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4516 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4517 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4518
4519 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4520 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4521 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4522 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4523
4524 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4525 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4526 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4527 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4528
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4529 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4530
4531#-------------------------------------------------------------
4532# LI - Local interconnect layer
4533#-------------------------------------------------------------
4534
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4535variants *
4536
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4537 width *li 170 "Local interconnect width < %d (li.1)"
4538 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4539
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4540 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4541 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4542
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4543 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4544 # no special layers for the contacts in core cells, so they must be included
4545 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4546 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4547 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4548
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4549 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4550 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4551
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4552 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4553 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4554
4555 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4556 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4557 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4558
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4559 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4560
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4561 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4562 angles coreli 45 \
4563 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4564
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4565#-------------------------------------------------------------
4566# MCON - Contact between local interconnect and metal1
4567#-------------------------------------------------------------
4568
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4569 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4570 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4571
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4572 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4573
4574#-------------------------------------------------------------
4575# METAL1 -
4576#-------------------------------------------------------------
4577
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4578 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4579 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4580 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4581
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4582 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4583 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4584 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4585 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4586
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4587 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4588
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4589variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4590 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4591 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4592 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4593 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4594
4595variants (full)
4596 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4597 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4598
4599 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4600 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4601variants *
4602
4603#--------------------------------------------------
4604# VIA1
4605#--------------------------------------------------
4606
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4607 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4608 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4609 surround v1/m1 *m1,rm1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4610 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4611 surround v1/m2 *m2,rm2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4612 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4613
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4614 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4615
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4616#ifdef RERAM
4617#--------------------------------------------------
4618# ReRAM
4619#--------------------------------------------------
4620
Tim Edwardsbf1da952021-12-21 15:41:31 -0500[diff] [blame]4621 width reram 260 "ReRAM width < %d (rr1.1)"
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]4622 spacing reram reram 55 touching_illegal "ReRAM spacing < %d (rr1.2)"
4623 surround reram *m1,rm1 30 directional \
4624 "Metal1 overlap of ReRAM < %d in one direction (via.5a - via.4a)"
4625 surround reram *m2,rm2 30 directional \
4626 "Metal2 overlap of ReRAM < %d in one direction (met2.5 - met2.4)"
4627
4628 no_overlap reram,v1 reram,v1
4629
4630#endif (RERAM)
4631
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4632#--------------------------------------------------
4633# METAL2 -
4634#--------------------------------------------------
4635
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4636 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4637 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4638 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4639
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4640 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4641
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4642variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4643 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4644 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4645 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4646 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4647
4648variants (full)
4649 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4650 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4651
4652 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4653 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4654variants *
4655
4656#--------------------------------------------------
4657# VIA2
4658#--------------------------------------------------
4659
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4660 width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4661
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4662 spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4663
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4664 surround v2/m2 *m2,rm2 45 directional \
4665 "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)"
4666 surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4667
4668 exact_overlap v2/m2
4669
4670#--------------------------------------------------
4671# METAL3 -
4672#--------------------------------------------------
4673
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4674 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4675 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4676 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4677
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4678 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4679
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4680variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4681 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4682 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4683 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4684 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4685variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4686 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4687 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4688variants *
4689
4690
4691#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4692#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4693#--------------------------------------------------
4694# VIA3 - Requires METAL5 Module
4695#--------------------------------------------------
4696
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4697 width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)"
4698 spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)"
4699 surround v3/m3 *m3,rm3 30 directional \
4700 "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)"
4701 surround v3/m4 *m4,rm4 5 absence_illegal \
4702 "Metal4 overlap of via3 < %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4703
4704 exact_overlap v3/m3
4705
4706#-----------------------------
4707# METAL4 - METAL4 Module
4708#-----------------------------
4709
4710variants *
4711
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4712 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4713 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4714 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4715
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4716 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4717
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4718variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4719 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4720 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4721 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4722 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4723variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4724 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4725 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4726variants *
4727
4728#--------------------------------------------------
4729# VIA4 - Requires METAL5 Module
4730#--------------------------------------------------
4731
Tim Edwardsc681f202021-05-28 22:29:50 -0400[diff] [blame]4732 width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)"
4733 spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)"
4734 surround v4/m5 *m5,rm5 120 absence_illegal \
4735 "Metal5 overlap of via4 < %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4736
4737 exact_overlap v4/m4
4738
4739#-----------------------------
4740# METAL5 - METAL5 Module
4741#-----------------------------
4742
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4743 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4744 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4745 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4746
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4747 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4748
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4749#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4750#endif (METAL5)
4751
4752#ifdef REDISTRIBUTION
4753
4754variants (full)
4755
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4756 width metrdl 10000 "RDL width < %d (rdl.1)"
4757 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4758 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
Tim Edwards64f54802021-06-04 12:28:40 -0400[diff] [blame]4759 spacing padl metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4760
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4761variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4762
4763#endif (REDISTRIBUTION)
4764
4765#--------------------------------------------------
4766# NMOS, PMOS
4767#--------------------------------------------------
4768
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4769 edge4way *poly allfetsstd 420 allfets 0 0 \
4770 "Transistor width < %d (diff/tap.2)"
4771 edge4way *poly allfetsspecial 360 allfets 0 0 \
4772 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4773 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4774 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4775 edge4way *poly ppu 140 allfets 0 0 \
4776 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4777
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4778 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4779 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4780
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4781 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4782 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4783 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4784 "poly spacing to diffusion tap < %d (poly.5)"
4785 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4786 "poly spacing to diffusion tap < %d (poly.5)"
4787 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4788 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4789
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4790 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4791 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4792 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4793 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4794 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4795 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4796 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4797 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4798
4799 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4800 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4801 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4802
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4803 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4804 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4805
4806 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4807 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4808 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4809
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4810 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4811 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4812
4813 # Minimum length of MV FETs. Note that this is larger than the minimum
4814 # width (0.29um), so an edge rule is required
4815
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4816 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4817 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4818
4819 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4820 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4821
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4822 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4823 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824
4825#--------------------------------------------------
4826# mrp1 (N+ poly resistor)
4827#--------------------------------------------------
4828
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4829 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4830
4831#--------------------------------------------------
4832# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4833# uhrpoly (P+ poly resistor, 2kOhm/sq)
4834#--------------------------------------------------
4835
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4836 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4837 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4838 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4839
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4840 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4841 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4842
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4843 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4844 "Poly resistor spacing to poly < %d (poly.9)"
4845
4846 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4847 "Poly resistor spacing to poly < %d (poly.9)"
4848
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4849 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4850 "Poly resistor spacing to poly < %d (poly.9)"
4851
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4852 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4853 "Poly resistor spacing to diffusion < %d (poly.9)"
4854
4855#------------------------------------
4856# nsonos
4857#------------------------------------
4858
4859variants (full)
4860 cifmaxwidth bbox_missing 0 bend_illegal \
4861 "SONOS transistor must be in cell with abutment box (tunm.8)"
4862variants (fast),(full)
4863
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4864#------------------------------------
4865# MOS Varactor device rules
4866#------------------------------------
4867
4868 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4869 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4870
4871 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4872 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4873
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4874 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4875 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4876
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4877variants (full)
4878 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4879 "N-well overlap of varactor poly < 0.15um (varac.5)"
4880
4881 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4882 "Varactor N-well must not contain P+ diffusion (varac.7)"
4883variants (fast),(full)
4884
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4885#ifdef MIM
4886#-----------------------------------------------------------
4887# MiM CAP (CAPM) -
4888#-----------------------------------------------------------
4889
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4890 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4891 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4892 spacing *mimcap via3/m3 80 touching_illegal \
4893 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4894 surround *mimcc *mimcap 80 absence_illegal \
4895 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4896 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4897
4898 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4899 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4900 spacing via2 *mimcap 100 touching_illegal \
4901 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4902 spacing *mimcap *metal3/m3 500 surround_ok \
4903 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4904
4905variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4906 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4907 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4908variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4909
4910 # MiM cap contact rules (VIA3)
4911
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4912 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4913 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4914 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4915 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4916 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4917
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4918 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4919 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4920 spacing *mimcap2 via4/m4 10 touching_illegal \
4921 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4922 surround *mim2cc *mimcap2 10 absence_illegal \
4923 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4924 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4925
4926 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4927 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4928 spacing via3 *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4929 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4930 spacing *mimcap2 *metal4/m4 500 surround_ok \
4931 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4932
4933variants (full)
Tim Edwards23daea12021-05-24 13:57:25 -0400[diff] [blame]4934 cifmaxwidth mim2_contact_overlap 0 bend_illegal \
4935 "MiM2 cap contact must not cross MiM cap contact (cap2m.8)"
4936
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4937 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4938 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4939variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4940
4941 # MiM cap contact rules (VIA4)
4942
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4943 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4944 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4945 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4946 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4947 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4948 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4949
4950#endif (MIM)
4951
4952#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4953# HVNTM
4954#----------------------------
4955variants (full)
4956 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4957 "HVNTM spacing < %d (hvntm.2)"
4958variants (fast),(full)
4959
4960#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4961# End DRC style
4962#----------------------------
4963
4964end
4965
4966#----------------------------
4967# LEF format definitions
4968#----------------------------
4969
4970lef
4971
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4972 masterslice pwell pwell PWELL substrate
4973 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4974
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4975 routing li li1 LI1 LI li
4976
4977 routing m1 met1 MET1 m1
4978 routing m2 met2 MET2 m2
4979 routing m3 met3 MET3 m3
4980#ifdef METAL5
4981 routing m4 met4 MET4 m4
4982 routing m5 met5 MET5 m5
4983#endif (METAL5)
4984#ifdef REDISTRIBUTION
4985 routing mrdl met6 MET6 m6 MRDL METRDL
4986#endif
4987
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4988 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4989 cut m2c via via1 VIA VIA1 cont2 via12
4990 cut m3c via2 VIA2 cont3 via23
4991#ifdef METAL5
4992 cut via3 via3 VIA3 cont4 via34
4993 cut via4 via4 VIA4 cont5 via45
4994#endif (METAL5)
4995
4996 obs obsli li1
4997 obs obsm1 met1
4998 obs obsm2 met2
4999 obs obsm3 met3
5000
5001#ifdef METAL5
5002 obs obsm4 met4
5003 obs obsm5 met5
5004#endif (METAL5)
5005#ifdef REDISTRIBUTION
5006 obs obsmrdl met6
5007#endif
5008
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5009 # NOTE: obsmcon only used with li1, not obsli.
5010 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5011
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]5012 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
5013 obs obsm1 via
5014 obs obsm2 via2
5015#ifdef METAL5
5016 obs obsm3 via3
5017 obs obsm4 via4
5018#endif (METAL5)
5019
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5020end
5021
5022#-----------------------------------------------------
5023# Device and Parasitic extraction
5024#-----------------------------------------------------
5025
5026
5027extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5028 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5029 cscale 1
5030 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5031 # dimensions must be in units of microns in the extract file.
5032 # Use extract style "ngspice(si)" to override this and produce
5033 # a file with SI units for length/area.
5034
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5035 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5036 lambda 1E6
5037 variants (si)
5038 lambda 1.0
5039 variants *
5040
5041 units microns
5042 step 7
5043 sidehalo 2
5044
5045 # NOTE: MiM cap layers have been purposely put out of order,
5046 # may want to reconsider.
5047
5048 planeorder dwell 0
5049 planeorder well 1
5050 planeorder active 2
5051 planeorder locali 3
5052 planeorder metal1 4
5053 planeorder metal2 5
5054 planeorder metal3 6
5055#ifdef METAL5
5056 planeorder metal4 7
5057 planeorder metal5 8
5058#ifdef REDISTRIBUTION
5059 planeorder metali 9
5060 planeorder block 10
5061 planeorder comment 11
5062 planeorder cap1 12
5063 planeorder cap2 13
5064#else (!REDISTRIBUTION)
5065 planeorder block 9
5066 planeorder comment 10
5067 planeorder cap1 11
5068 planeorder cap2 12
5069#endif (!REDISTRIBUTION)
5070#else (!METAL5)
5071#ifdef REDISTRIBUTION
5072 planeorder metali 7
5073 planeorder block 8
5074 planeorder comment 9
5075 planeorder cap1 10
5076 planeorder cap2 11
5077#else (!REDISTRIBUTION)
5078 planeorder block 7
5079 planeorder comment 8
5080 planeorder cap1 9
5081 planeorder cap2 10
5082#endif (!REDISTRIBUTION)
5083#endif (!METAL5)
5084
5085 height dnwell -0.1 0.1
5086 height nwell,pwell 0.0 0.2062
5087 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5088 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5089 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5090 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5091 height alldiffcont 0.3262 0.61
5092 height pc 0.5062 0.43
5093 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5094 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5095 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5096 height m1fill 1.3761 0.36
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5097#ifdef RERAM
5098 # TO-DO: Rework all heights based on ReRAM!
5099#endif (RERAM)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5100 height v1 1.7361 0.27
5101 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5102 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5103 height v2 2.3661 0.42
5104 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5105 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5106#ifdef METAL5
5107 height v3 3.6311 0.39
5108 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5109 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5110 height v4 4.8661 0.505
5111 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5112 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5113 height mimcap 2.4661 0.2
5114 height mimcap2 3.7311 0.2
5115 height mimcc 2.6661 0.12
5116 height mim2cc 3.9311 0.09
5117#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]5118 height mrdlc 6.6311 0.63
5119 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5120#endif (!REDISTRIBUTION)
5121#endif (!METAL5)
5122
5123 # Antenna check parameters
5124 # Note that checks w/diode diffusion are not modeled
5125 model partial
5126 antenna poly sidewall 50 none
5127 antenna allcont surface 3 none
5128 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5129 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5130 antenna m1,m2,m3 sidewall 400 2600 400
5131 antenna v1 surface 3 0 18
5132 antenna v2 surface 6 0 36
5133#ifdef METAL5
5134 antenna m4,m5 sidewall 400 2600 400
5135 antenna v3,v4 surface 6 0 36
5136#endif (METAL5)
5137
5138 tiedown alldiffnonfet
5139
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]5140 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5141
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5142# Resistances are in milliohms per square
5143# Optional 3rd argument is the corner adjustment fraction
5144# Device values come from trtc.cor (typical corner)
Tim Edwards14beb9c2021-09-15 16:19:23 -0400[diff] [blame]5145 resist (pwell,isosub)/well 4400000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5146 resist (dnwell)/dwell 2200000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5147 resist (nwell)/well 1700000
5148 resist (rpw)/well 3050000 0.5
5149 resist (*ndiff,nsd)/active 120000
5150 resist (*pdiff,*psd)/active 197000
5151 resist (*mvndiff,mvnsd)/active 114000
5152 resist (*mvpdiff,*mvpsd)/active 191000
5153
5154 resist ndiffres/active 120000 0.5
5155 resist pdiffres/active 197000 0.5
5156 resist mvndiffres/active 114000 0.5
5157 resist mvpdiffres/active 191000 0.5
5158 resist mrp1/active 48200 0.5
5159 resist xhrpoly/active 319800 0.5
5160 resist uhrpoly/active 2000000 0.5
5161
5162 resist (allpolynonres)/active 48200
5163 resist rmp/active 48200
5164
5165 resist (allli)/locali 12200
5166 resist (allm1)/metal1 125
5167 resist (allm2)/metal2 125
5168 resist (allm3)/metal3 47
5169#ifdef METAL5
5170 resist (allm4)/metal4 47
5171 resist (allm5)/metal5 29
5172#endif (METAL5)
5173#ifdef REDISTRIBUTION
5174 resist mrdl/metali 5
5175#endif (REDISTRIBUTION)
5176
Tim Edwardsb9023ba2021-07-23 09:51:31 -0400[diff] [blame]5177 # These types should not be considered as electrical nodes
5178 resist blocktypes None
5179 resist obstypes None
5180 resist idtypes None
5181 resist comment None
5182
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5183 contact ndc,nsc 15000
5184 contact pdc,psc 15000
5185 contact mvndc,mvnsc 15000
5186 contact mvpdc,mvpsc 15000
5187 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5188 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5189 contact m2c 4500
5190 contact m3c 3410
5191#ifdef METAL5
5192#ifdef MIM
5193 contact mimcc 4500
5194 contact mim2cc 3410
5195#endif (MIM)
5196 contact via3 3410
5197 contact via4 380
5198#endif (METAL5)
5199#ifdef REDISTRIBUTION
5200 contact mrdlc 6
5201#endif (REDISTRIBUTION)
5202
5203#-------------------------------------------------------------------------
5204# Parasitic capacitance values: Use document (...)
5205#-------------------------------------------------------------------------
5206# This uses the new "default" definitions that determine the intervening
5207# planes from the planeorder stack, take care of the reflexive sideoverlap
5208# definitions, and generally clean up the section and make it more readable.
5209#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5210# Also uses "units microns" statement. All values are taken from the
5211# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5212# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5213#-------------------------------------------------------------------------
5214# Remember that device capacitances to substrate are taken care of by the
5215# models. Thus, active and poly definitions ignore all "fet" types.
5216# fet types are excluded when computing parasitic capacitance to
5217# active from layers above them because poly is a shield; fet types are
5218# included for parasitics from layers above to poly. Resistor types
5219# should be removed from all parasitic capacitance calculations, or else
5220# they just create floating caps. Technically, the capacitance probably
5221# should be split between the two terminals. Unsure of the correct model.
5222#-------------------------------------------------------------------------
5223
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5224#deep n-well
5225defaultareacap dnwell dwell 120
5226
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5227#p-well
5228defaultoverlap pwell well dnwell dwell 120
5229
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5230#n-well
5231# NOTE: This value not found in PEX files
5232defaultareacap nwell well 120
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5233defaultoverlap nwell well isosub dwell 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5234
5235#n-active
5236# Rely on device models to capture *ndiff area cap
5237# Do not extract parasitics from resistors
5238# defaultareacap allnactivenonfet active 790
5239# defaultperimeter allnactivenonfet active 280
5240
5241#p-active
5242# Rely on device models to capture *pdiff area cap
5243# Do not extract parasitics from resistors
5244# defaultareacap allpactivenonfet active 810
5245# defaultperimeter allpactivenonfet active 300
5246
5247#poly
5248# Do not extract parasitics from resistors
5249# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5250# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5251# defaultperimeter allpolynonfet active 57
5252
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5253 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5254 defaultareacap *poly active nwell,obswell,pwell well 106
5255 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5256 defaultsideoverlap *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5257
5258#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5259 defaultsidewall allli locali 33
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5260 defaultoverlap allli locali dnwell,isosub dwell 37
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5261 defaultareacap allli locali nwell,obswell,pwell well 37
Tim Edwards195d9a32021-12-30 15:38:35 -0500[diff] [blame]5262 defaultperimeter allli locali nwell,obswell,pwell well 41
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5263 defaultoverlap allli locali nwell,obswell,pwell well 37
Tim Edwards195d9a32021-12-30 15:38:35 -0500[diff] [blame]5264 defaultsideoverlap allli locali nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5265
5266#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5267 defaultoverlap allli locali allactivenonfet active 37
Tim Edwards195d9a32021-12-30 15:38:35 -0500[diff] [blame]5268 defaultsideoverlap allli locali allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5269
5270#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5271 defaultoverlap allli locali allpolynonres active 94
5272 defaultsideoverlap allli locali allpolynonres active 52
5273 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5274
5275#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5276 defaultsidewall allm1 metal1 45
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5277 defaultoverlap allm1 metal1 dnwell,isosub dwell 26
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5278 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5279 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5280 defaultoverlap allm1 metal1 nwell,obswell,pwell well 26
5281 defaultsideoverlap allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5282
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5283#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5284 defaultoverlap allm1 metal1 allactivenonfet active 26
5285 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5286
5287#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5288 defaultoverlap allm1 metal1 allpolynonres active 45
5289 defaultsideoverlap allm1 metal1 allpolynonres active 47
5290 defaultsideoverlap *poly active allm1 metal1 17
5291
5292#metal1->locali
5293 defaultoverlap allm1 metal1 allli locali 114
5294 defaultsideoverlap allm1 metal1 allli locali 59
5295 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5296
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5297#ifdef RERAM
5298# TO-DO: Modify all metal stack parasitics above metal1 based on ReRAM!
5299#endif (RERAM)
5300
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5301#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5302 defaultsidewall allm2 metal2 50
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5303 defaultoverlap allm2 metal2 dnwell,isosub dwell 17
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5304 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
Tim Edwards195d9a32021-12-30 15:38:35 -0500[diff] [blame]5305 defaultperimeter allm2 metal2 nwell,obswell,pwell well 38
5306 defaultoverlap allm2 metal2 nwell,obswell,pwell well 17
5307 defaultsideoverlap allm2 metal2 nwell,obswell,pwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5308
5309#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5310 defaultoverlap allm2 metal2 allactivenonfet active 17
Tim Edwards195d9a32021-12-30 15:38:35 -0500[diff] [blame]5311 defaultsideoverlap allm2 metal2 allactivenonfet active 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5312
5313#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5314 defaultoverlap allm2 metal2 allpolynonres active 24
5315 defaultsideoverlap allm2 metal2 allpolynonres active 41
5316 defaultsideoverlap *poly active allm2 metal2 11
5317
5318#metal2->locali
5319 defaultoverlap allm2 metal2 allli locali 38
5320 defaultsideoverlap allm2 metal2 allli locali 46
5321 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5322
5323#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5324 defaultoverlap allm2 metal2 allm1 metal1 134
5325 defaultsideoverlap allm2 metal2 allm1 metal1 67
5326 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5327
5328#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5329 defaultsidewall allm3 metal3 63
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5330 defaultoverlap allm3 metal3 dnwell,isosub dwell 12
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5331 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5332 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5333 defaultoverlap allm3 metal3 nwell,obswell,pwell well 12
5334 defaultsideoverlap allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5335
5336#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5337 defaultoverlap allm3 metal3 allactive active 12
5338 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5339
5340#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5341 defaultoverlap allm3 metal3 allpolynonres active 16
5342 defaultsideoverlap allm3 metal3 allpolynonres active 44
5343 defaultsideoverlap *poly active allm3 metal3 9
5344
5345#metal3->locali
5346 defaultoverlap allm3 metal3 allli locali 21
5347 defaultsideoverlap allm3 metal3 allli locali 47
5348 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5349
5350#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5351 defaultoverlap allm3 metal3 allm1 metal1 35
5352 defaultsideoverlap allm3 metal3 allm1 metal1 55
5353 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5354
5355#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5356 defaultoverlap allm3 metal3 allm2 metal2 86
5357 defaultsideoverlap allm3 metal3 allm2 metal2 70
5358 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5359
5360#ifdef METAL5
5361#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5362 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5363# defaultareacap alltopm metal4 well 6
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5364 defaultoverlap allm4 metal4 dnwell,isosub dwell 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5365 areacap allm4/m4 8
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5366 defaultperimeter allm4 metal4 nwell,obswell,pwell well 37
5367 defaultoverlap allm4 metal4 nwell,obswell,pwell well 8
5368 defaultsideoverlap allm4 metal4 nwell,obswell,pwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5369
5370#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5371 defaultoverlap allm4 metal4 allactivenonfet active 8
5372 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5373
5374#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5375 defaultoverlap allm4 metal4 allpolynonres active 10
5376 defaultsideoverlap allm4 metal4 allpolynonres active 38
5377 defaultsideoverlap *poly active allm4 metal4 6
5378
5379#metal4->locali
5380 defaultoverlap allm4 metal4 allli locali 12
5381 defaultsideoverlap allm4 metal4 allli locali 40
5382 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5383
5384#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5385 defaultoverlap allm4 metal4 allm1 metal1 15
5386 defaultsideoverlap allm4 metal4 allm1 metal1 43
5387 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5388
5389#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5390 defaultoverlap allm4 metal4 allm2 metal2 20
5391 defaultsideoverlap allm4 metal4 allm2 metal2 46
5392 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5393
5394#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5395 defaultoverlap allm4 metal4 allm3 metal3 84
5396 defaultsideoverlap allm4 metal4 allm3 metal3 71
5397 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5398
5399#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5400 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5401# defaultareacap allm5 metal5 well 6
Tim Edwards7e0dd832021-12-31 11:19:39 -0500[diff] [blame]5402 defaultoverlap allm5 metal5 dnwell,isosub dwell 6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5403 areacap allm5/m5 6
Tim Edwardsb1383ef2021-12-30 15:17:34 -0500[diff] [blame]5404 defaultoverlap allm5 metal5 nwell,obswell,pwell well 6
5405 defaultperimeter allm5 metal5 nwell,obswell,pwell well 39
5406 defaultsideoverlap allm5 metal5 nwell,obswell,pwell well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5407
5408#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5409 defaultoverlap allm5 metal5 allactivenonfet active 6
5410 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5411
5412#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5413 defaultoverlap allm5 metal5 allpolynonres active 7
5414 defaultsideoverlap allm5 metal5 allpolynonres active 40
5415 defaultsideoverlap *poly active allm5 metal5 6
5416
5417#metal5->locali
5418 defaultoverlap allm5 metal5 allli locali 8
5419 defaultsideoverlap allm5 metal5 allli locali 41
5420 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5421
5422#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5423 defaultoverlap allm5 metal5 allm1 metal1 9
5424 defaultsideoverlap allm5 metal5 allm1 metal1 43
5425 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5426
5427#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5428 defaultoverlap allm5 metal5 allm2 metal2 11
5429 defaultsideoverlap allm5 metal5 allm2 metal2 46
5430 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5431
5432#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5433 defaultoverlap allm5 metal5 allm3 metal3 20
5434 defaultsideoverlap allm5 metal5 allm3 metal3 54
5435 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5436
5437#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5438 defaultoverlap allm5 metal5 allm4 metal4 68
5439 defaultsideoverlap allm5 metal5 allm4 metal4 83
5440 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5441#endif (METAL5)
5442
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5443#ifdef REDISTRIBUTION
5444#endif (REDISTRIBUTION)
5445
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5446# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5447
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5448variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5449
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5450 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5451 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5452 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5453 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5454 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5455 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5456 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5457 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5458 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5459 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5460 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5461 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5462 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5463 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5464 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5465
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5466 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5467 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5468 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5469 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5470 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5471 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5472 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5473 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5474 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5475 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5476 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5477 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5478 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5479 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5480 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5481 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5482 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5483 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5484 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5485 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5486 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5487 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5488 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5489 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5490
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5491 # Bipolars
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5492 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \
5493 error +npn1p00
5494 device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \
5495 error +npn2p00
Tim Edwards42a78832021-05-07 21:25:41 -0400[diff] [blame]5496 device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5497 device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \
5498 pwell,space/w +pnp0p68
5499 device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \
5500 pwell,space/w +pnp3p40
Tim Edwardsb9668302021-05-27 14:10:11 -0400[diff] [blame]5501 device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5502 device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \
5503 dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5504 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5505
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5506 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5507 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5508 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5509 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5510
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5511 # Extended drain devices (must appear before the regular devices)
5512 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5513 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5514 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5515 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5516 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5517 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5518
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5519 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5520 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5521 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5522 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5523 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5524 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5525 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5526 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5527 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5528 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5529 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5530 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5531 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5532 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5533 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5534 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5535 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5536 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5537
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5538 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5539 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5540 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5541 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5542#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5543 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5544 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5545#endif (METAL5)
Tim Edwardsc2787e82021-11-17 15:27:23 -0500[diff] [blame]5546 device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \
5547 photo pwell,space/w error a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5548
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5549 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5550 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5551 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5552 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5553 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5554 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5555 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5556 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5557 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5558 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5559 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5560 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5561 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5562 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5563 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5564 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5565 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5566 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5567 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5568 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5569 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5570 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5571 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5572 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5573
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5574 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5575 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5576 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5577 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5578 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5579 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5580 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5581 *mvndiff pwell,space/w error l=l w=w
5582 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5583 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5584
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5585 device resistor sky130_fd_pr__res_generic_po rmp *poly
5586 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5587
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5588 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area p=pj
5589 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area p=pj
5590 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area p=pj
5591 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area p=pj
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5592
Tim Edwards78ee6332021-05-17 16:31:05 -0400[diff] [blame]5593 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area p=pj
5594 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area p=pj
5595 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area p=pj
5596 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area p=pj
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5597
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5598#ifdef RERAM
Tim Edwardsf1bee922021-11-24 23:05:34 -0500[diff] [blame]5599 device csubcircuit sky130_fd_pr__reram_reram_cell reram m1 a=area_ox
Tim Edwards33e65982021-11-24 22:35:04 -0500[diff] [blame]5600#endif (RERAM)
5601
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5602#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5603 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5604 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5605#endif (MIM)
5606
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5607 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5608
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5609 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5610 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5611 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5612 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5613 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5614 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5615 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5616 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5617 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5618 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5619 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5620 pwell,space/w
5621
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5622 # Note that corenvar, corepvar are not considered devices, and extract as
5623 # parasitic capacitance instead (but cap values need to be added).
5624
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5625 # Extended drain devices (must appear before the regular devices)
5626 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5627 dnwell pwell,space/w error
5628 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5629 dnwell pwell,space/w error
5630 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5631 pwell,space/w nwell error
5632
5633 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5634 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5635 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5636 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5637 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5638 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5639
5640 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5641 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5642 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5643 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5644
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5645 device resistor sky130_fd_pr__res_generic_po rmp *poly
5646 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5647 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5648 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5649 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5650#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5651 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5652 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5653#endif (METAL5)
5654
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5655 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5656 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5657 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5658 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5659 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5660 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5661 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5662 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5663 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5664 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5665 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5666 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5667 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5668 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5669 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5670 device resistor mrdn_hv mvndiffres *mvndiff
5671 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5672 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5673
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5674 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5675 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5676 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5677 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5678
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5679 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5680 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5681 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5682 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5683
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5684 device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error +npn1p00
5685 device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error +npn2p00
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5686 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5687 device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w +pnp0p68
5688 device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w +pnp3p40
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5689 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
Tim Edwardsdaad1062021-05-19 10:51:27 -0400[diff] [blame]5690 device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error +npn11p0
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5691 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5692
5693#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5694 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5695 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5696#endif (MIM)
5697
5698end
5699
5700#-----------------------------------------------------
5701# Wiring tool definitions
5702#-----------------------------------------------------
5703
5704wiring
5705 # All wiring values are in nanometers
5706 scalefactor 10
5707
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5708 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5709 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5710 contact v2 280 m2 0 45 m3 25 0
5711#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5712 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5713 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5714#endif (METAL5)
5715
5716 contact pc 170 poly 50 80 li 0 80
5717 contact pdc 170 pdiff 40 60 li 0 80
5718 contact ndc 170 ndiff 40 60 li 0 80
5719 contact psc 170 psd 40 60 li 0 80
5720 contact nsc 170 nsd 40 60 li 0 80
5721
5722end
5723
5724#-----------------------------------------------------
5725# Plain old router. . .
5726#-----------------------------------------------------
5727
5728router
5729end
5730
5731#------------------------------------------------------------
5732# Plowing (restored in magic 8.2, need to fill this section)
5733#------------------------------------------------------------
5734
5735plowing
5736end
5737
5738#-----------------------------------------------------------------
5739# No special plot layers defined (use default PNM color choices)
5740#-----------------------------------------------------------------
5741
5742plot
5743 style pnm
5744 default
5745 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5746 draw fillblock4 no_color_at_all
5747 draw fomfill no_color_at_all
5748 draw polyfill no_color_at_all
5749 draw m1fill no_color_at_all
5750 draw m2fill no_color_at_all
5751 draw m3fill no_color_at_all
5752 draw m4fill no_color_at_all
5753 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5754 draw nwell cwell
5755end
5756