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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 9930f071fe70ea427e2d24eb84dd943aeb488fa4 / . / sky130 / magic / sky130.tech
blob: bfc96358a49c16a25bd84773604c84a4881aec91 [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]25 description "SkyWater SKY130: Open Source rules and DRC"
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]26 requires magic-8.3.111
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
Tim Edwards26ab4962021-01-03 14:22:54 -0500[diff] [blame]34# Status 1/3/21: Taking out of beta and declaring an official release.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]35#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]36
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]37#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]38# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]39#------------------------------------------------------------------------
40# device name magic ID layer description
41#------------------------------------------------------------------------
42# sky130_fd_pr__nfet_01v8 nfet standard nFET
43# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]44# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
45# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]46# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]47# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]48# sky130_fd_pr__pfet_01v8 pfet standard pFET
49# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]50# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]51# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
52# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
53# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]54# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]55# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
56# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
57# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
60# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]61# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
62# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]63# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
64# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]65# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]66# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]67# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]68# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]69# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
70# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
71# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]72# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]75# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
76# sky130_fd_pr__res_generic_po npres n+ poly resistor
77# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
78# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
79# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
80# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
81# sky130_fd_pr__cap_var mvvaractor thickox varactor
82# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]83# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
84# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]85#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]86# (*) Note that ppres may extract into some generic type called
87# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
88# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]89#
90# (**) nFET and pFET in standard cells are the same as devices
91# outside of the standard cell except for the DRC rule for
92# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
93#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]94#-------------------------------------------------------------
95# The following devices are not extracted but are represented
96# only by script-generated subcells in the PDK.
97#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]100# sky130_fd_pr__special_nfet_pass_flash flash nFET device
101# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
102# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
103# sky130_fd_pr__cap_vpp_* Vpp cap
104# sky130_fd_pr__ind_* inductor
105# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]106#--------------------------------------------------------------
107
108#-----------------------------------------------------
109# Tile planes
110#-----------------------------------------------------
111
112planes
113 dwell,dw
114 well,w
115 active,a
116 locali,li1,li
117 metal1,m1
118 metal2,m2
119 metal3,m3
120#ifdef METAL5
121#ifdef MIM
122 cap1,c1
123#endif (MIM)
124 metal4,m4
125#ifdef MIM
126 cap2,c2
127#endif (MIM)
128 metal5,m5
129#endif (METAL5)
130#ifdef REDISTRIBUTION
131 metali,mi
132#endif
133 block,b
134 comment,c
135end
136
137#-----------------------------------------------------
138# Tile types
139#-----------------------------------------------------
140
141types
142# Deep nwell
143 dwell dnwell,dnw
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]144 dwell isosubstrate,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]163 active nnmos,nntransistor,nnfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]167 -active mvnmosesd,mvntransistoresd,mvnfetesd
168 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]169 active varactor,varact,var
170 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]171
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]172 active pmoslvt,pfetlvt
173 active pmosmvt,pfetmvt
174 active pmoshvt,pfethvt
175 active nmoslvt,nfetlvt
176 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]177 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]178 -active sramnvar,corenvar,corenvaractor
179 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]180
181# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]182 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]183 active ndiff,ndiffusion,ndif
184 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]185 active mvndiff,mvndiffusion,mvndif
186 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]187 active ndiffc,ndcontact,ndc
188 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]189 active mvndiffc,mvndcontact,mvndc
190 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]191 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
192 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
193 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
194 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
195 active psubdiffcont,psubstratepcontact,psc,ptapc
196 active nsubdiffcont,nsubstratencontact,nsc,ntapc
197 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
198 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]199 -active obsactive
200 -active mvobsactive
201
202# Poly
203 active poly,p,polysilicon
204 active polycont,pc,pcontact,polycut,polyc
205 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]206 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]207
208# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]209 active npolyres,npres,mrp1
210 active ppolyres,ppres,xhrpoly
211 active xpolyres,xpres,xres,uhrpoly
212 active ndiffres,rnd,rdn,rndiff
213 active pdiffres,rpd,rdp,rpdiff
214 active mvndiffres,mvrnd,mvrdn,mvrndiff
215 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
216 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]217
218# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]219 active pdiode,pdi
220 active ndiode,ndi
221 active nndiode,nndi
222 active pdiodec,pdic
223 active ndiodec,ndic
224 active nndiodec,nndic
225 active mvpdiode,mvpdi
226 active mvndiode,mvndi
227 active mvpdiodec,mvpdic
228 active mvndiodec,mvndic
229 active pdiodelvt,pdilvt
230 active pdiodehvt,pdihvt
231 active ndiodelvt,ndilvt
232 active pdiodelvtc,pdilvtc
233 active pdiodehvtc,pdihvtc
234 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235
236# Local Interconnect
237 locali locali,li1,li
238 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]239 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]240 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]242 -locali obsli1c,obsmcon
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]243 -locali lifill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]244
245# Metal 1
246 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]248 metal1 via1,m2contact,m2cut,m2c,via,v,v1
249 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]250 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 2
254 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 metal2 via2,m3contact,m3cut,m3c,v2
257 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]258 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]259
260# Metal 3
261 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]263 -metal3 obsm3
264#ifdef METAL5
265 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]266 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]267
268#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]269 cap1 mimcap,mim,capm
270 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]271#endif
272
273# Metal 4
274 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]275 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276 -metal4 obsm4
277 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]278 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]279
280#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]281 cap2 mimcap2,mim2,capm2
282 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif
284
285# Metal 5
286 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]287 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]289 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]290#endif (METAL5)
291
292#ifdef REDISTRIBUTION
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]293 metal5 mrdlcontact,mrdlc,pi1
294 metali metalrdl,mrdl,metrdl,rdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -metali obsmrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]296 metali pi2
297 block ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]298#endif (REDISTRIBUTION)
299
300# Miscellaneous
301 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]302 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]303 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]304 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]305# fixed resistor width identifiers
306 -comment res0p35
307 -comment res0p69
308 -comment res1p41
309 -comment res2p85
310 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]311
312end
313
314#-----------------------------------------------------
315# Magic contact types
316#-----------------------------------------------------
317
318contact
319 pc poly locali
320 ndc ndiff locali
321 pdc pdiff locali
322 nsc nsd locali
323 psc psd locali
324 ndic ndiode locali
325 ndilvtc ndiodelvt locali
326 nndic nndiode locali
327 pdic pdiode locali
328 pdilvtc pdiodelvt locali
329 pdihvtc pdiodehvt locali
330 xpc xpc locali
331
332 mvndc mvndiff locali
333 mvpdc mvpdiff locali
334 mvnsc mvnsd locali
335 mvpsc mvpsd locali
336 mvndic mvndiode locali
337 mvpdic mvpdiode locali
338
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]339 mcon locali metal1
340 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]341
342 via1 metal1 metal2
343 via2 metal2 metal3
344#ifdef METAL5
345 via3 metal3 metal4
346 via4 metal4 metal5
347#endif (METAL5)
348 stackable
349
350#ifdef METAL5
351#ifdef MIM
352 # MiM cap contacts are not stackable!
353 mimcc mimcap metal4
354 mim2cc mimcap2 metal5
355#endif (MIM)
356
357 padl m1 m2 m3 m4 m5 glass
358#else
359 padl m1 m2 m3 glass
360#endif (!METAL5)
361
362#ifdef REDISTRIBUTION
363 mrdlc metal5 mrdl
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]364 pi2 mrdl ubm
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]365#endif (REDISTRIBUTION)
366end
367
368#-----------------------------------------------------
369# Layer aliases
370#-----------------------------------------------------
371
372aliases
373
374 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]375 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]376
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]377 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]378 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]379 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]380 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]381 allfetsspecial scnfet,scpfet,scpfethvt
382 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]383 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]384
385 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
386 allnactive allnactivenonfet,allnfets
387 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]388 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]389
390 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
391 allpactive allpactivenonfet,allpfets
392 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]393 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]394
395 allactivenonfet allnactivenonfet,allpactivenonfet
396 allactive allactivenonfet,allfets
397
398 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
399
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]400 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]401 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]402 alldifflv allndifflv,allpdifflv
403 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
404 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
405 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
406
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]407 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]408 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]409 alldiffmv allndiffmv,allpdiffmv
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]410 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]411 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]412 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
413 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
414 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
415 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
416
417 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]418 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]419
420 allpolyres mrp1,xhrpoly,uhrpoly,rmp
421 allpolynonfet *poly,allpolyres,xpc
422 allpolynonres *poly,allfets,xpc
423
424 allpoly allpolynonfet,allfets
425 allpolynoncap *poly,xpc,allfets,allpolyres
426
427 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
428 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
429 allndiffcontmv mvndc,mvnsc,mvndic
430 allpdiffcontmv mvpdc,mvpsc,mvpdic
431 allndiffcont allndiffcontlv,allndiffcontmv
432 allpdiffcont allpdiffcontlv,allpdiffcontmv
433 alldiffcontlv allndiffcontlv,allpdiffcontlv
434 alldiffcontmv allndiffcontmv,allpdiffcontmv
435 alldiffcont alldiffcontlv,alldiffcontmv
436
437 allcont alldiffcont,pc
438
439 allres allpolyres,allactiveres
440
441 allli *locali,coreli,rli
442 allm1 *m1,rm1
443 allm2 *m2,rm2
444 allm3 *m3,rm3
445#ifdef METAL5
446 allm4 *m4,rm4
447 allm5 *m5,rm5
448#endif (METAL5)
449
450 allpad padl
451
452 psub pwell
453
454end
455
456#-----------------------------------------------------
457# Layer drawing styles
458#-----------------------------------------------------
459
460styles
461 styletype mos
462 dnwell cwell
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]463 isosub subcircuit
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]464 nwell nwell
465 pwell pwell
466 rpwell pwell ptransistor_stripes
467 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]468 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]469 pdiff pdiffusion
470 nsd ndiff_in_nwell
471 psd pdiff_in_pwell
472 nfet ntransistor ntransistor_stripes
473 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]474 npass ntransistor ntransistor_stripes
475 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]476 pfet ptransistor ptransistor_stripes
477 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]478 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]479 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]480 var polysilicon ndiff_in_nwell
481 ndc ndiffusion metal1 contact_X'es
482 pdc pdiffusion metal1 contact_X'es
483 nsc ndiff_in_nwell metal1 contact_X'es
484 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]485 corenvar polysilicon ndiff_in_nwell
486 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]487
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]488 pnp nwell ntransistor_stripes
489 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]490
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]491 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]492 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]493 pfethvt ptransistor ptransistor_stripes implant2
494 nfetlvt ntransistor ntransistor_stripes implant1
495 nsonos ntransistor implant3
496 varhvt polysilicon ndiff_in_nwell implant2
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]497 nnfet ntransistor ndiff_in_nwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]498
499 mvndiff ndiffusion hvndiff_mask
500 mvpdiff pdiffusion hvpdiff_mask
501 mvnsd ndiff_in_nwell hvndiff_mask
502 mvpsd pdiff_in_pwell hvpdiff_mask
503 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]504 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]505 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
506 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]507 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508 mvvar polysilicon ndiff_in_nwell hvndiff_mask
509 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
510 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
511 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
512 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
513
514 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]515 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]516 pc polysilicon metal1 contact_X'es
517 npolyres polysilicon silicide_block nselect2
518 ppolyres polysilicon silicide_block pselect2
519 xpc polysilicon pselect2 metal1 contact_X'es
520 rmp polysilicon poly_resist_stripes
521
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]522 res0p35 implant1
523 res0p69 implant1
524 res1p41 implant1
525 res2p85 implant1
526 res5p73 implant1
527
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]528 pdiode pdiffusion pselect2
529 ndiode ndiffusion nselect2
530 pdiodec pdiffusion pselect2 metal1 contact_X'es
531 ndiodec ndiffusion nselect2 metal1 contact_X'es
532
533 nndiode ndiffusion nselect2 implant3
534 ndiodelvt ndiffusion nselect2 implant1
535 pdiodelvt pdiffusion pselect2 implant1
536 pdiodehvt pdiffusion pselect2 implant2
537 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
538 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
539 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
540
541 mvpdiode pdiffusion pselect2 hvpdiff_mask
542 mvndiode ndiffusion nselect2 hvndiff_mask
543 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
544 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
545 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
546
547 locali metal1
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]548 lifill metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]549 coreli metal1
550 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]551 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]552 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]553 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]554
555 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]556 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]557 rm1 metal2 poly_resist_stripes
558 obsm1 metal2
559 m2c metal2 metal3 via2arrow
560 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]561 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]562 rm2 metal3 poly_resist_stripes
563 obsm2 metal3
564 m3c metal3 metal4 via3alt
565 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]566 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]567 rm3 metal4 poly_resist_stripes
568 obsm3 metal4
569#ifdef METAL5
570#ifdef MIM
571 mimcap metal3 mems
572 mimcc metal3 contact_X'es mems
573 mimcap2 metal4 mems
574 mim2cc metal4 contact_X'es mems
575#endif (MIM)
576 via3 metal4 metal5 via4
577 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]578 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]579 rm4 metal5 poly_resist_stripes
580 obsm4 metal5
581 via4 metal5 metal6 via5
582 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]583 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]584 rm5 metal6 poly_resist_stripes
585 obsm5 metal6
586#endif (METAL5)
587#ifdef REDISTRIBUTION
588 mrdlc metal6 metal7 via6
589 metalrdl metal7
590 obsmrdl metal7
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]591 ubm metal8
592 pi2 metal7 metal8 via7
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]593#endif (REDISTRIBUTION)
594
595 glass overglass
596 mrp1 poly_resist poly_resist_stripes
597 xhrpoly poly_resist silicide_block
598 uhrpoly poly_resist
599 ndiffres ndiffusion ndop_stripes
600 pdiffres pdiffusion pdop_stripes
601 mvndiffres ndiffusion hvndiff_mask ndop_stripes
602 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
603 comment comment
604 error_p error_waffle
605 error_s error_waffle
606 error_ps error_waffle
607 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]608 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]609
610 obswell cwell
611 obsactive implant4
612
613#ifndef METAL5
614 padl metal4 via4 overglass
615#else
616 padl metal6 via6 overglass
617#endif
618
619 magnet substrate_field_implant
620 rotate via3alt
621 fence via5
622end
623
624#-----------------------------------------------------
625# Special paint/erase rules
626#-----------------------------------------------------
627
628compose
629 compose nfet poly ndiff
630 compose pfet poly pdiff
631 compose var poly nsd
632
633 compose mvnfet poly mvndiff
634 compose mvpfet poly mvpdiff
635 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]636
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]637 paint obsmcon locali via1
638 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]639
640 paint ndc nwell pdc
641 paint nfet nwell pfet
642 paint scnfet nwell scpfet
643 paint ndiff nwell pdiff
644 paint psd nwell nsd
645 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]646 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]647
648 paint pdc pwell ndc
649 paint pfet pwell nfet
650 paint scpfet pwell scnfet
651 paint pdiff pwell ndiff
652 paint nsd pwell psd
653 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]654 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]655
656 paint pdc coreli pdc
657 paint ndc coreli ndc
658 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]659 paint nsc coreli nsc
660 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]661 paint viali coreli viali
662
663 paint coreli pdc pdc
664 paint coreli ndc ndc
665 paint coreli pc pc
666 paint coreli nsc nsc
667 paint coreli psc psc
668 paint coreli viali viali
669
670#ifdef METAL5
671 paint m4 obsm4 m4
672 paint m5 obsm5 m5
673#endif (METAL5)
674end
675
676#-----------------------------------------------------
677# Electrical connectivity
678#-----------------------------------------------------
679
680connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]681 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
682 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]683 *li,coreli,lifill *li,coreli,lifill
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]684 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]685 *m2,m2fill *m2,m2fill
686 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]687#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]688 *m4,m4fill *m4,m4fill
689 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]690#ifdef MIM
691 *mimcap *mimcap
692 *mimcap2 *mimcap2
693#endif (MIM)
694#endif (METAL5)
695 allnactivenonfet allnactivenonfet
696 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]697 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]698#ifdef REDISTRIBUTION
699 # RDL connects to m5 (i.e., padl) through glass cut
700 *mrdl *mrdl
701 glass metrdl
702#endif (REDISTRIBUTION)
703end
704
705#-----------------------------------------------------
706# CIF/GDS output layer definitions
707#-----------------------------------------------------
708# NOTE: All values in this section MUST be multiples of 25
709# or else magic will scale below the allowed layout grid size
710
711cifoutput
712
713#----------------------------------------------------------------
714style gdsii
715# NOTE: This section is used for actual GDS output
716#----------------------------------------------------------------
717 scalefactor 10 nanometers
718 options calma-permissive-labels
719 gridlimit 5
720
721#----------------------------------------------------------------
722# Create a temp layer from the cell bounding box for use in
723# generating ID layers. Note that "boundary", unlike "bbox",
724# requires the FIXED_BBOX property (abutment box) in the cell.
725#----------------------------------------------------------------
726 templayer CELLBOUND
727 boundary
728
729#----------------------------------------------------------------
730# BOUND
731#----------------------------------------------------------------
732 layer BOUND CELLBOUND
733 calma 235 4
734
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]735#----------------------------------------------------------------
736# DNWELL
737#----------------------------------------------------------------
738
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]739 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]740 calma 64 18
741
742 layer PWRES rpw
743 and dnwell
744 calma 64 13
745
746#----------------------------------------------------------------
747# NWELL
748#----------------------------------------------------------------
749
750 layer NWELL allnwell
751 bloat-all rpw dnwell
752 and-not rpw,pwell
753 calma 64 20
754
755 layer WELLTXT
756 labels allnwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]757 calma 64 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]758
759 layer WELLPIN
760 labels allnwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]761 calma 64 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]762
763#----------------------------------------------------------------
764# SUB (text/port only)
765#----------------------------------------------------------------
766
767 layer SUBTXT
768 labels pwell noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]769 calma 64 59
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]770
771 layer SUBPIN
772 labels pwell port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]773 calma 122 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]774
775#----------------------------------------------------------------
776# DIFF
777#----------------------------------------------------------------
778
779 layer DIFF allnactivenontap,allpactivenontap,allactiveres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]780 calma 65 20
781
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]782 layer DIFFTXT
783 labels allnactivenontap,allpactivenontap noport
784 calma 65 6
785
786 layer DIFFPIN
787 labels allnactivenontap,allpactivenontap port
788 calma 65 16
789
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]790#----------------------------------------------------------------
791# TAP
792#----------------------------------------------------------------
793
794 layer TAP allnactivetap,allpactivetap
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]795 labels allnactivetap,allpactivetap port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]796 calma 65 44
797
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]798 layer TAPTXT
799 labels allnactivetap,allpactivetap noport
800 calma 65 5
801
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]802#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]803# FOM
804#----------------------------------------------------------------
805
806 layer FOMFILL fomfill
807 labels fomfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]808 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]809
810#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]811# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]812#----------------------------------------------------------------
813
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]814 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]815 grow 15
816 or xhrpoly,uhrpoly,xpc
817 grow 110
818 bloat-or allpactivetap * 125 allnactivenontap 0
819 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]820
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]821 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]822 grow 125
823 bloat-or allnactivetap * 125 allpactivenontap 0
824 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]825
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]826 templayer extendPSDM basePSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]827 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]828 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]829
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]830 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]831 grow 185
832 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]833 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]834 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]835 calma 94 20
836
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]837 templayer extendNSDM baseNSDM
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]838 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]839 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]840
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]841 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]842 grow 185
843 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]844 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]845 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]846 calma 93 44
847
848#----------------------------------------------------------------
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]849# LVID
850#----------------------------------------------------------------
851
852 layer LVID nnfet
853 grow 100
854 calma 81 60
855
856#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]857# LVTN
858#----------------------------------------------------------------
859
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]860 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]861 grow 180
862 bridge 380 380
863 grow 185
864 shrink 185
865 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]866 mask-hints LVTN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]867 calma 125 44
868
869#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]870# HVTR
871#----------------------------------------------------------------
872
873 layer HVTR pfetmvt
874 grow 180
875 bridge 380 380
876 grow 185
877 shrink 185
878 close 265000
879 calma 18 20
880
881#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]882# HVTP
883#----------------------------------------------------------------
884
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]885 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]886 grow 180
887 bridge 380 380
888 grow 185
889 shrink 185
890 close 265000
Tim Edwards05284082021-01-28 14:41:48 -0500[diff] [blame]891 mask-hints HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]892 calma 78 44
893
894#----------------------------------------------------------------
895# SONOS
896#----------------------------------------------------------------
897
898 layer SONOS nsonos
899 grow 100
900 grow-min 410
901 bridge 500 410
902 grow 250
903 shrink 250
904 calma 80 20
905
906#----------------------------------------------------------------
907# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]908# coreli layer indicates a cell needing COREID. Also, devices
909# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]910#----------------------------------------------------------------
911
912 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]913 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]914 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]915 calma 81 2
916
917#----------------------------------------------------------------
918# STDCELL applies to all cells containing scnfet or scpfet.
919#----------------------------------------------------------------
920
921 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]922 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]923 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]924 calma 81 4
925
926#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]927# ESDID is a marker layer for ESD devices in the padframe I/O.
928#----------------------------------------------------------------
929
930 layer ESDID
931 bloat-all mvnfetesd *mvndiff,*poly
932 bloat-all mvpfetesd *mvpdiff,*poly
933 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]934 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]935 calma 81 19
936
937#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]938# NPNID and PNPID apply to bipolar transistors
939#----------------------------------------------------------------
940
941 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]942 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]943 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]944 calma 82 20
945
946 templayer pnparea pnp
947 grow 400
948
949 layer PNPID
950 bloat-all pnparea *psd
951 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]952 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]953 calma 82 44
954
955#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]956# RPM
957#----------------------------------------------------------------
958
959 layer RPM
960 bloat-all xhrpoly xpc
961 grow 200
962 grow-min 1270
963 grow 420
964 shrink 420
965 calma 86 20
966
967#----------------------------------------------------------------
968# URPM (2kOhms/sq. poly implant)
969#----------------------------------------------------------------
970
971 layer URPM
972 bloat-all uhrpoly xpc
973 grow 200
974 grow-min 1270
975 grow 420
976 shrink 420
977 calma 79 20
978
979#----------------------------------------------------------------
980# LDNTM (Tip implant for SONOS FETs)
981#----------------------------------------------------------------
982
983 layer LDNTM
984 bloat-all nsonos *ndiff
985 grow 185
986 grow 345
987 shrink 345
988 calma 11 44
989
990#----------------------------------------------------------------
991# HVNTM (Tip implant for MV ndiff devices)
992#----------------------------------------------------------------
993
994 templayer hvntm_block *mvpsd
995 grow 185
996
997 layer HVNTM
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]998 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]999 bloat-all mvvaractor *mvnsd
1000 and-not hvntm_block
1001 grow 185
1002 grow 345
1003 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]1004 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1005 calma 125 20
1006
1007#----------------------------------------------------------------
1008# POLY
1009#----------------------------------------------------------------
1010
1011 layer POLY allpoly
1012 calma 66 20
1013
1014 layer POLYTXT
1015 labels allpoly noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1016 calma 66 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1017
1018 layer POLYPIN
1019 labels allpoly port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1020 calma 66 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1021
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1022 layer POLYFILL polyfill
1023 labels polyfill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1024 calma 28 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1025
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1026#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1027# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1028#----------------------------------------------------------------
1029
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1030 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1031 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1032 bloat-all alldiffmv nwell
1033 grow 345
1034 shrink 345
1035
1036 templayer large_ptap_mv thkox_area
1037 shrink 420
1038 grow 420
1039
1040 templayer small_ptap_mv thkox_area
1041 and-not large_ptap_mv
1042 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1043 grow-min 840
1044
Tim Edwards4e5bf212021-01-06 13:11:31 -0500[diff] [blame]1045 layer HVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1046 bridge 700 600
1047 grow 345
1048 shrink 345
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1049 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1050 calma 75 20
1051
1052#----------------------------------------------------------------
1053# CONT (LICON)
1054#----------------------------------------------------------------
1055
1056 layer CONT allcont
1057 squares-grid 0 170 170
1058 calma 66 44
1059
1060 # Contact for pres is different than other LICON contacts
1061 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1062 templayer xpc_horiz xpc
1063 shrink 1007
1064 grow 1007
1065
1066 layer CONT xpc
1067 and-not xpc_horiz
1068 # Force long edge vertical for contacts narrower than 2um
1069 # Minimum space is 350 but 520 satisfies no. of contacts rule
1070 slots 80 190 520 80 2000 350
1071 calma 66 44
1072
1073 layer CONT xpc
1074 and xpc_horiz
1075 # Force long edge vertical for contacts wider than 2um
1076 # Minimum space is 350 but 520 satisfies no. of contacts rule
1077 slots 80 2000 350 80 190 520
1078 calma 66 44
1079
1080#----------------------------------------------------------------
1081# NPC (Nitride poly cut)
1082# surrounds CONT (LICON) on poly only (i.e., pc)
1083#----------------------------------------------------------------
1084
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1085 # Avoids a common case of NPC bridges too close to other LICON shapes.
1086 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
1087 grow 90
1088
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1089 layer NPC pc
1090 squares-grid 0 170 170
1091 grow 100
1092 bridge 270 270
Tim Edwards522a3732021-02-04 09:57:08 -0500[diff] [blame]1093 and-not diffcutarea
1094 bridge 270 270
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1095 grow 130
1096 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1097 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1098 calma 95 20
1099
1100 # NPC is also generated on xhrpoly and uhrpoly resistors
1101
1102 layer NPC xpc,xhrpoly,uhrpoly
1103 # xpc surrounds precision_resistor by 0.095um
1104 grow 95
1105 grow 130
1106 shrink 130
1107 calma 95 20
1108
1109#----------------------------------------------------------------
1110# Device markers
1111#----------------------------------------------------------------
1112
1113 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1114 calma 65 13
1115
1116 layer POLYRES mrp1
1117 calma 66 13
1118
1119 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1120 layer POLYSHORT rmp
1121 calma 66 15
1122
1123 # POLYRES extends to edge of contact cut
1124 layer POLYRES xhrpoly,uhrpoly
1125 grow 60
1126 and xpc
1127 or xhrpoly,uhrpoly
1128 calma 66 13
1129
1130 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1131 # To be done: Expand to include anode, cathode, and guard ring
1132 calma 81 23
1133
1134#----------------------------------------------------------------
1135# LI
1136#----------------------------------------------------------------
1137 layer LI allli
1138 calma 67 20
1139
1140 layer LITXT
1141 labels *locali,coreli noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1142 calma 67 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1143
1144 layer LIPIN
1145 labels *locali,coreli port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1146 calma 67 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1147
1148 layer LIRES rli
1149 labels rli
1150 calma 67 13
1151
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1152 layer LIFILL lifill
1153 labels lifill
1154 calma 56 28
1155
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1156#----------------------------------------------------------------
1157# MCON
1158#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1159 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1160 squares-grid 0 170 190
1161 calma 67 44
1162
1163#----------------------------------------------------------------
1164# MET1
1165#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1166 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1167 calma 68 20
1168
1169 layer MET1TXT
1170 labels allm1 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1171 calma 68 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1172
1173 layer MET1PIN
1174 labels allm1 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1175 calma 68 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1176
1177 layer MET1RES rm1
1178 labels rm1
1179 calma 68 13
1180
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1181 layer MET1FILL m1fill
1182 labels m1fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1183 calma 36 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1184
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1185#----------------------------------------------------------------
1186# VIA1
1187#----------------------------------------------------------------
1188 layer VIA1 via1
1189 squares-grid 55 150 170
1190 calma 68 44
1191
1192#----------------------------------------------------------------
1193# MET2
1194#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1195 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1196 calma 69 20
1197
1198 layer MET2TXT
1199 labels allm2 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1200 calma 69 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1201
1202 layer MET2PIN
1203 labels allm2 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1204 calma 69 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1205
1206 layer MET2RES rm2
1207 labels rm2
1208 calma 69 13
1209
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1210 layer MET2FILL m2fill
1211 labels m2fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1212 calma 41 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1213
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1214#----------------------------------------------------------------
1215# VIA2
1216#----------------------------------------------------------------
1217 layer VIA2 via2
1218 squares-grid 40 200 200
1219 calma 69 44
1220
1221#----------------------------------------------------------------
1222# MET3
1223#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1224 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1225 calma 70 20
1226
1227 layer MET3TXT
1228 labels allm3 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1229 calma 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1230
1231 layer MET3PIN
1232 labels allm3 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1233 calma 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1234
1235 layer MET3RES rm3
1236 labels rm3
1237 calma 70 13
1238
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1239 layer MET3FILL m3fill
1240 labels m3fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1241 calma 34 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1242
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1243#ifdef METAL5
1244#----------------------------------------------------------------
1245# VIA3
1246#----------------------------------------------------------------
1247 layer VIA3 via3
1248#ifdef MIM
1249 or mimcc
1250#endif (MIM)
1251 squares-grid 60 200 200
1252 calma 70 44
1253
1254#----------------------------------------------------------------
1255# MET4
1256#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1257 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1258 calma 71 20
1259
1260 layer MET4TXT
1261 labels allm4 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1262 calma 71 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1263
1264 layer MET4PIN
1265 labels allm4 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1266 calma 71 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1267
1268 layer MET4RES rm4
1269 labels rm4
1270 calma 71 13
1271
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1272 layer MET4FILL m4fill
1273 labels m4fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1274 calma 51 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1275
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1276#----------------------------------------------------------------
1277# VIA4
1278#----------------------------------------------------------------
1279 layer VIA4 via4
1280#ifdef MIM
1281 or mim2cc
1282#endif (MIM)
1283 squares-grid 190 800 800
1284 calma 71 44
1285
1286#----------------------------------------------------------------
1287# MET5
1288#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1289 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1290 calma 72 20
1291
1292 layer MET5TXT
1293 labels allm5 noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1294 calma 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1295
1296 layer MET5PIN
1297 labels allm5 port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1298 calma 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1299
1300 layer MET5RES rm5
1301 labels rm5
1302 calma 72 13
1303
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1304 layer MET5FILL m5fill
1305 labels m5fill
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1306 calma 59 28
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1307
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1308#endif (METAL5)
1309
1310#ifdef REDISTRIBUTION
1311#----------------------------------------------------------------
1312# RDL
1313#----------------------------------------------------------------
1314 layer RDL *metrdl
1315 calma 74 20
1316
1317 layer RDLTXT
1318 labels *metrdl noport
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1319 calma 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1320
1321 layer RDLPIN
1322 labels *metrdl port
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]1323 calma 74 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1324
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1325 layer PI1 *metrdl
1326 and padl,glass
1327 # Test only---needs GDS layer number
1328
1329 layer UBM *metrdl
1330 shrink 50000
1331 grow 40000
1332 # Test only---needs GDS layer number
1333
1334 layer PI2 *metrdl
1335 shrink 50000
1336 grow 25000
1337 # Test only---needs GDS layer number
1338
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1339#endif REDISTRIBUTION
1340
1341#----------------------------------------------------------------
1342# GLASS
1343#----------------------------------------------------------------
1344 layer GLASS glass
1345 calma 76 20
1346
1347#ifdef MIM
1348#----------------------------------------------------------------
1349# CAPM
1350#----------------------------------------------------------------
1351 layer CAPM *mimcap
1352 labels mimcap
1353 calma 89 44
1354
1355 layer CAPM2 *mimcap2
1356 labels mimcap2
1357 calma 97 44
1358#endif (MIM)
1359
1360#----------------------------------------------------------------
1361# Chip top level marker for DRC latchup rules to check 15um
1362# distance to taps (otherwise 6um is used)
1363#----------------------------------------------------------------
1364
1365 layer LOWTAPDENSITY
1366 bbox top
1367 # Clear 200um for pads + 50um for required high tap density
1368 # in critical area.
1369 shrink 250000
1370 calma 81 14
1371
1372#----------------------------------------------------------------
1373# FILLBLOCK
1374#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1375 layer FILLOBSFOM obsactive
1376 calma 22 24
1377
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1378 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1379 calma 62 24
1380
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1381 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1382 calma 105 52
1383
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1384 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1385 calma 107 24
1386
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1387 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1388 calma 112 4
1389
1390 render DNWELL cwell -0.1 0.1
1391 render NWELL nwell 0.0 0.2062
1392 render DIFF ndiffusion 0.2062 0.12
1393 render TAP pdiffusion 0.2062 0.12
1394 render POLY polysilicon 0.3262 0.18
1395 render CONT via 0.5062 0.43
1396 render LI metal1 0.9361 0.10
1397 render MCON via 1.0361 0.34
1398 render MET1 metal2 1.3761 0.36
1399 render VIA1 via 1.7361 0.27
1400 render MET2 metal3 2.0061 0.36
1401 render VIA2 via 2.3661 0.42
1402 render MET3 metal4 2.7861 0.845
1403#ifdef METAL5
1404 render VIA3 via 3.6311 0.39
1405 render MET4 metal5 4.0211 0.845
1406 render VIA4 via 4.8661 0.505
1407 render MET5 metal6 5.3711 1.26
1408 render CAPM metal8 2.4661 0.2
1409 render CAPM2 metal9 3.7311 0.2
1410#ifdef REDISTRIBUTION
1411 render RDL metal7 11.8834 4.0
1412#endif (!REDISTRIBUTION)
1413#endif (!METAL5)
1414
1415#----------------------------------------------------------------
1416style drc
1417#----------------------------------------------------------------
1418# NOTE: This style is used for DRC only, not for GDS output
1419#----------------------------------------------------------------
1420 scalefactor 10 nanometers
1421 options calma-permissive-labels
1422
1423 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1424 templayer dnwell_shrink dnwell
1425 shrink 1030
1426
1427 templayer nwell_missing dnwell
1428 grow 400
1429 and-not dnwell_shrink
1430 and-not nwell
1431
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1432 templayer pwell_in_dnwell dnwell
1433 and-not nwell
1434
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1435 # SONOS nFET devices must be in deep nwell
1436 templayer dnwell_missing nsonos
1437 and-not dnwell
1438
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1439 # SONOS nFET devices must be in cell with abutment box
1440 templayer abutment_box
1441 boundary
1442
1443 templayer bbox_missing nsonos
1444 and-not abutment_box
1445
1446 # Make sure nwell covers varactor poly
1447 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1448 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1449 grow 150
1450 and-not nwell
1451
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1452 # Define MiM cap bottom plate for spacing rule
1453 templayer mim_bottom
1454 bloat-all *mimcap *metal3
1455
1456 # Define MiM2 cap bottom plate for spacing rule
1457 templayer mim2_bottom
1458 bloat-all *mimcap2 *metal4
1459
1460 # Note that metal fill is performed by the foundry and so is not
1461 # an option for a cifoutput style.
1462
1463 # Check latchup rule (15um minimum from tap LICON center to any
1464 # non-tap diffusion. Note that to count as a tap, the diffusion
1465 # must be contacted to LI
1466
1467 templayer ptap_reach psc,mvpsc
1468 and-not dnwell
1469 # grow total is 15um. grow in 0.84um increments to ensure that
1470 # no nwell ring is crossed
1471 grow 840
1472 and-not nwell,dnwell
1473 grow 840
1474 and-not nwell,dnwell
1475 grow 840
1476 and-not nwell,dnwell
1477 grow 840
1478 and-not nwell,dnwell
1479 grow 840
1480 and-not nwell,dnwell
1481 grow 840
1482 and-not nwell,dnwell
1483 grow 840
1484 and-not nwell,dnwell
1485 grow 840
1486 and-not nwell,dnwell
1487 grow 840
1488 and-not nwell,dnwell
1489 grow 840
1490 and-not nwell,dnwell
1491 grow 840
1492 and-not nwell,dnwell
1493 grow 840
1494 and-not nwell,dnwell
1495 grow 840
1496 and-not nwell,dnwell
1497 grow 840
1498 and-not nwell,dnwell
1499 grow 840
1500 and-not nwell,dnwell
1501 grow 840
1502 and-not nwell,dnwell
1503 grow 840
1504 and-not nwell,dnwell
1505 grow 635
1506 and-not nwell,dnwell
1507
1508 templayer ptap_missing *ndiff,*mvndiff
1509 and-not dnwell
1510 and-not ptap_reach
1511
1512 templayer ntap_reach nsc,mvnsc
1513 # grow total is 15um. grow in 1.27um increments to ensure that
1514 # no nwell ring is crossed. There is no difference between
1515 # ntaps in and out of deep nwell.
1516 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1517 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1518 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1519 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1520 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1521 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1522 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1523 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1524 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1525 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1526 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1527 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1528 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1529 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1530 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1531 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1532 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1533 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1534 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1535 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1536 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1537 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1538 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1539 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1540
1541 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1542 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1543 and-not ntap_reach
1544
1545 templayer dptap_reach psc,mvpsc
1546 and dnwell
1547 grow 840
1548 and-not nwell
1549 and dnwell
1550 grow 840
1551 and-not nwell
1552 and dnwell
1553 grow 840
1554 and-not nwell
1555 and dnwell
1556 grow 840
1557 and-not nwell
1558 and dnwell
1559 grow 840
1560 and-not nwell
1561 and dnwell
1562 grow 840
1563 and-not nwell
1564 and dnwell
1565 grow 840
1566 and-not nwell
1567 and dnwell
1568 grow 840
1569 and-not nwell
1570 and dnwell
1571 grow 840
1572 and-not nwell
1573 and dnwell
1574 grow 840
1575 and-not nwell
1576 and dnwell
1577 grow 840
1578 and-not nwell
1579 and dnwell
1580 grow 840
1581 and-not nwell
1582 and dnwell
1583 grow 840
1584 and-not nwell
1585 and dnwell
1586 grow 840
1587 and-not nwell
1588 and dnwell
1589 grow 840
1590 and-not nwell
1591 and dnwell
1592 grow 840
1593 and-not nwell
1594 and dnwell
1595 grow 840
1596 and-not nwell
1597 and dnwell
1598 grow 635
1599 and-not nwell
1600 and dnwell
1601
1602 templayer dptap_missing *ndiff,*mvndiff
1603 and dnwell
1604 and-not dptap_reach
1605
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1606 templayer pdiff_crosses_dnwell dnwell
1607 grow 20
1608 and-not dnwell
1609 and allpdifflv,allpdiffmv
1610
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1611 # MV nwell must be 2um from any other nwell
1612 templayer mvnwell
1613 bloat-all alldiffmv nwell
1614 grow-min 840
1615 bridge 700 600
1616
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1617 # Simple spacing checks to lvnwell must use CIF-DRC rule
1618 templayer allmvdiffnowell *mvndiff,*mvpsd
1619
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1620 templayer lvnwell nwell
1621 and-not mvnwell
1622
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1623 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1624 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1625
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1626 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1627 and-not nwell_with_tap
1628
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1629 templayer tap_with_licon
1630 bloat-all psc,mvpsc psd,mvpsd
1631 bloat-all nsc,mvnsc nsd,mvnsd
1632
1633 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1634 and-not tap_with_licon
1635
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1636 # Make sure varactor nwell contains no P diffusion
1637 templayer pdiff_in_varactor_well
1638 bloat-all varactor,mvvaractor nwell
1639 and allpactive
1640
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1641 # HVNTM spacing requires recreating HVNTM
1642 templayer hvntm_block *mvpsd
1643 grow 185
1644
1645 templayer hvntm_generate
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]1646 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1647 bloat-all mvvaractor *mvnsd
1648 and-not hvntm_block
1649 grow 185
1650 grow 345
1651 shrink 345
1652 and-not hvntm_block
1653
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]1654 # RPM spacing checks require recreating RPM
1655 templayer rpm_generate
1656 bloat-all xhrpoly,uhrpoly xpc
1657 grow 200
1658 grow-min 1270
1659 grow 420
1660 shrink 420
1661
1662 # Check distance RPM to NSDM
1663 templayer rpm_nsd_check rpm_generate
1664 grow 325
1665 and allndifflv,allndiffmv
1666
1667 # Check distance RPM to (unrelated) POLY
1668 templayer rpm_poly_check rpm_generate
1669 grow 200
1670 and-not xhrpoly,uhrpoly,xpc
1671 and allpoly
1672
1673 # Check distance RPM to HVNTM
1674 templayer rpm_hvntm_check rpm_generate
1675 grow 385
1676 and allndiffmvnontap
1677
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1678 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1679 close 140000
1680
1681 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1682 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1683
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1684 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1685 close 140000
1686
1687 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1688 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1689
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1690 templayer m1_huge allm1
1691 shrink 1500
1692 grow 1500
1693
1694 templayer m1_large_halo m1_huge
1695 grow 280
1696 and-not m1_huge
1697 and allm1
1698
1699 templayer m2_huge allm2
1700 shrink 1500
1701 grow 1500
1702
1703 templayer m2_large_halo m2_huge
1704 grow 280
1705 and-not m2_huge
1706 and allm2
1707
1708 templayer m3_huge allm3
1709 shrink 1500
1710 grow 1500
1711
1712 templayer m3_large_halo m3_huge
1713 grow 400
1714 and-not m3_huge
1715 and allm3
1716
1717 templayer m4_huge allm4
1718 shrink 1500
1719 grow 1500
1720
1721 templayer m4_large_halo m4_huge
1722 grow 400
1723 and-not m4_huge
1724 and allm4
1725
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1726#ifdef EXPERIMENTAL
1727#----------------------------------------------------------------
1728style paint
1729#----------------------------------------------------------------
1730# NOTE: This style is used for database manipulations only via
1731# the "cif paint" command.
1732#----------------------------------------------------------------
1733
1734 scalefactor 10 nanometers
1735
1736 templayer m1grow *m1
1737 grow 290
1738
1739 # layer listrap: Use the following set of commands to strap local
1740 # interconnect wires with metal1 (inside the cursor box) to satisfy
1741 # the maximum aspect ratio rule for local interconnect:
1742 #
1743 # tech unlock *
1744 # cif ostyle paint
1745 # cif paint m1strap comment
1746 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1747 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1748 # erase comment
1749
1750 templayer m1strap *li
1751 and-not m1grow
1752 grow 30
1753
1754 templayer listrap comment
1755 slots 30 170 170 60
1756
1757#endif (EXPERIMENTAL)
1758
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1759#----------------------------------------------------------------
Tim Edwards9ff76c52021-01-11 22:12:22 -0500[diff] [blame]1760style density
1761#----------------------------------------------------------------
1762# Style used by scripts to check for fill density
1763#----------------------------------------------------------------
1764 scalefactor 10 nanometers
1765 options calma-permissive-labels
1766 gridlimit 5
1767
1768 templayer fom_all alldiff,fomfill
1769
1770 templayer poly_all allpoly,polyfill
1771
1772 templayer li_all allli,lifill
1773
1774 templayer m1_all allm1,m1fill
1775
1776 templayer m2_all allm2,m2fill
1777
1778 templayer m3_all allm3,m3fill
1779
1780 templayer m4_all allm4,m4fill
1781
1782 templayer m5_all allm5,m5fill
1783
1784#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1785style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1786#----------------------------------------------------------------
1787# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1788# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1789#----------------------------------------------------------------
1790 scalefactor 10 nanometers
1791 options calma-permissive-labels
1792 gridlimit 5
1793
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1794#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1795# Generate and retain a layer representing the bounding box.
1796#
1797# For variant ():
1798# The bounding box is the full extent of geometry on the top level
1799# cell.
1800#
1801# For variant (tiled):
1802# Use with a script that breaks layout into flattened tiles and runs
1803# fill individually on each. The tiles should be larger than the
1804# step size, and each should draw a layer "comment" the size of the
1805# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1806#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1807
1808 variants ()
1809 templayer topbox
1810 bbox top
1811
1812 variants (tiled)
1813 templayer topbox comment
1814 # Each tile imposes the full keepout distance rule of
1815 # 3um on all sides.
1816 shrink 1500
1817
1818 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1819
1820#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1821# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1822# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1823# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1824# Enclosure by nwell = Diff/Tap 8 = 0.18um
1825#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1826
1827 templayer mvnwell
1828 bloat-all alldiffmv nwell
1829
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1830 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1831 and-not mvnwell
1832
1833 templayer well_shrink mvnwell
1834 shrink 250
1835 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1836 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1837 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1838 grow 340
1839 and-not well_shrink
1840
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1841#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1842# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1843#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1844 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1845 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1846 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1847 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1848
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1849 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1850 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1851 grow 1000
1852
1853#---------------------------------------------------
1854# FOM and POLY fill
1855#---------------------------------------------------
1856 templayer fomfill_pass1 topbox
Tim Edwards546432e2021-02-17 12:19:21 -0500[diff] [blame]1857 # slots 0 4080 1320 0 4080 1320 1360 0
1858 slots 0 4080 1600 0 4080 1600 1360 0
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1859 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1860 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1861 shrink 2035
1862 grow 2035
1863
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1864#---------------------------------------------------
1865
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1866 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1867 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1868 or obstruct_poly
1869 templayer polyfill_pass1 topbox
1870 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1871 and-not obstruct_poly_pass1
1872 and topbox
1873 shrink 355
1874 grow 355
1875
1876#---------------------------------------------------
1877
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1878 templayer obstruct_fom_pass2 fomfill_pass1
1879 grow 1290
1880 or polyfill_pass1
1881 grow 300
1882 or obstruct_fom
1883 templayer fomfill_pass2 topbox
1884 slots 0 2500 1320 0 2500 1320 1360 0
1885 and-not obstruct_fom_pass2
1886 and topbox
1887 shrink 1245
1888 grow 1245
1889
1890#---------------------------------------------------
1891
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1892 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1893 grow 60
1894 or fomfill_pass1,fomfill_pass2
1895 grow 300
1896 or obstruct_poly
1897 templayer polyfill_coarse topbox
1898 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1899 and-not obstruct_poly_coarse
1900 and topbox
1901 shrink 355
1902 grow 355
1903
1904#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1905 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1906 grow 60
1907 or fomfill_pass1,fomfill_pass2
1908 grow 300
1909 or obstruct_poly
1910 templayer polyfill_medium topbox
1911 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1912 and-not obstruct_poly_medium
1913 and topbox
1914 shrink 265
1915 grow 265
1916
1917#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1918 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1919 grow 60
1920 or fomfill_pass1,fomfill_pass2
1921 grow 300
1922 or obstruct_poly
1923 templayer polyfill_fine topbox
1924 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1925 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1926 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1927 shrink 235
1928 grow 235
1929
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1930#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1931
1932 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1933 grow 1290
1934 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1935 grow 300
1936 or obstruct_fom
1937 templayer fomfill_coarse topbox
1938 slots 0 1500 1320 0 1500 1320 1360 0
1939 and-not obstruct_fom_coarse
1940 and topbox
1941 shrink 745
1942 grow 745
1943
1944#---------------------------------------------------
1945
1946 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1947 grow 1290
1948 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1949 grow 300
1950 or obstruct_fom
1951 templayer fomfill_fine topbox
1952 slots 0 500 400 0 500 400 160 0
1953 and-not obstruct_fom_fine
1954 and topbox
1955 shrink 245
1956 grow 245
1957
1958#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1959 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1960 or fomfill_pass2
1961 or fomfill_coarse
1962 or fomfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1963 calma 23 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1964
1965 layer POLYFILL polyfill_pass1
1966 or polyfill_coarse
1967 or polyfill_medium
1968 or polyfill_fine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1969 calma 28 28
1970
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1971#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1972# LI fill
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1973# Note requirement that LI fill may not overlap (non-fill)
1974# diff or poly.
1975#---------------------------------------------------------
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1976
1977 templayer obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1978 grow 2800
1979 or alldiff,allpoly
1980 grow 200
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1981 templayer lifill_coarse topbox
Tim Edwards86e6b072021-02-07 12:48:05 -0500[diff] [blame]1982 # slots 0 3000 650 0 3000 650 700 0
Tim Edwards8aa46802021-02-08 11:25:37 -0500[diff] [blame]1983 slots 0 3000 900 0 3000 900 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1984 and-not obstruct_li_coarse
1985 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1986 shrink 1495
1987 grow 1495
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1988
1989 templayer obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1990 grow 2500
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1991 or lifill_coarse
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1992 grow 300
1993 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1994 grow 200
1995 templayer lifill_medium topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1996 slots 0 1500 500 0 1500 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]1997 and-not obstruct_li_medium
1998 and topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]1999 shrink 745
2000 grow 745
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2001
2002 templayer obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2003 or lifill_coarse,lifill_medium
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2004 grow 300
2005 or alldiff,allpoly
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2006 grow 200
2007 templayer lifill_fine topbox
Tim Edwardse4947402021-01-15 13:56:56 -0500[diff] [blame]2008 slots 0 580 500 0 580 500 700 0
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2009 and-not obstruct_li_fine
2010 and topbox
2011 shrink 285
2012 grow 285
2013
2014 layer LIFILL lifill_coarse
2015 or lifill_medium
2016 or lifill_fine
2017 calma 56 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]2018
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2019#---------------------------------------------------
2020# MET1 fill
2021#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2022
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2023 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2024 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2025 templayer met1fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2026 # slots 0 2000 200 0 2000 200 700 0
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2027 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2028 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2029 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2030 shrink 995
2031 grow 995
2032
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2033 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2034 grow 2800
2035 or met1fill_coarse
2036 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2037 templayer met1fill_medium topbox
2038 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2039 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2040 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2041 shrink 495
2042 grow 495
2043
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2044 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2045 grow 300
2046 or met1fill_coarse,met1fill_medium
2047 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2048 templayer met1fill_fine topbox
2049 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2050 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2051 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2052 shrink 285
2053 grow 285
2054
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2055 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2056 grow 100
2057 or met1fill_coarse,met1fill_medium,met1fill_fine
2058 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2059 templayer met1fill_veryfine topbox
2060 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2061 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2062 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2063 shrink 145
2064 grow 145
2065
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2066 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2067 or met1fill_medium
2068 or met1fill_fine
2069 or met1fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2070 calma 36 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2071
2072#---------------------------------------------------
2073# MET2 fill
2074#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2075 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2076 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2077 templayer met2fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2078 # slots 0 2000 200 0 2000 200 700 350
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2079 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2080 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2081 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2082 shrink 995
2083 grow 995
2084
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2085 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2086 grow 2800
2087 or met2fill_coarse
2088 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2089 templayer met2fill_medium topbox
2090 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2091 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2092 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2093 shrink 495
2094 grow 495
2095
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2096 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2097 grow 300
2098 or met2fill_coarse,met2fill_medium
2099 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2100 templayer met2fill_fine topbox
2101 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2102 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2103 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2104 shrink 285
2105 grow 285
2106
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2107 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2108 grow 100
2109 or met2fill_coarse,met2fill_medium,met2fill_fine
2110 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2111 templayer met2fill_veryfine topbox
2112 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2113 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2114 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115 shrink 145
2116 grow 145
2117
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2118 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2119 or met2fill_medium
2120 or met2fill_fine
2121 or met2fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2122 calma 41 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2123
2124#---------------------------------------------------
2125# MET3 fill
2126#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2127 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2128 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2129 templayer met3fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2130 # slots 0 2000 300 0 2000 300 700 700
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2131 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2132 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2133 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2134 shrink 995
2135 grow 995
2136
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2137 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2138 grow 2700
2139 or met3fill_coarse
2140 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2141 templayer met3fill_medium topbox
2142 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2143 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2144 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2145 shrink 495
2146 grow 495
2147
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2148 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2149 grow 200
2150 or met3fill_coarse,met3fill_medium
2151 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2152 templayer met3fill_fine topbox
2153 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2154 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2155 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2156 shrink 285
2157 grow 285
2158
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2159 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2160 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2161 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2162 or met3fill_coarse,met3fill_medium,met3fill_fine
2163 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2164 templayer met3fill_veryfine topbox
2165 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2166 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2167 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2168 shrink 195
2169 grow 195
2170
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2171 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2172 or met3fill_medium
2173 or met3fill_fine
2174 or met3fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2175 calma 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2176
2177#ifdef METAL5
2178#---------------------------------------------------
2179# MET4 fill
2180#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2181 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2182 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2183 templayer met4fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2184 # slots 0 2000 300 0 2000 300 700 1050
Tim Edwards5c4222f2021-02-16 13:12:17 -0500[diff] [blame]2185 slots 0 2000 800 0 2000 800 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2186 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2187 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2188 shrink 995
2189 grow 995
2190
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2191 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2192 grow 2700
2193 or met4fill_coarse
2194 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2195 templayer met4fill_medium topbox
2196 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2197 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2198 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2199 shrink 495
2200 grow 495
2201
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2202 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2203 grow 200
2204 or met4fill_coarse,met4fill_medium
2205 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2206 templayer met4fill_fine topbox
2207 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2208 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2209 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2210 shrink 285
2211 grow 285
2212
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2213 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2214 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2215 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2216 or met4fill_coarse,met4fill_medium,met4fill_fine
2217 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2218 templayer met4fill_veryfine topbox
2219 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2220 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2221 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2222 shrink 195
2223 grow 195
2224
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2225 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2226 or met4fill_medium
2227 or met4fill_fine
2228 or met4fill_veryfine
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2229 calma 51 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2230
2231#---------------------------------------------------
2232# MET5 fill
2233#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2234 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2235 grow 3000
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2236 templayer met5fill_coarse topbox
Tim Edwards7904e762021-01-11 12:56:39 -0500[diff] [blame]2237 slots 0 5000 1600 0 5000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2238 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2239 and topbox
Tim Edwards7324f652021-01-12 10:20:16 -0500[diff] [blame]2240 shrink 2495
2241 grow 2495
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2242
Tim Edwardsf0664562021-01-16 20:47:13 -0500[diff] [blame]2243 templayer obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
2244 grow 1400
2245 or met5fill_coarse
2246 grow 1600
2247 templayer met5fill_medium topbox
2248 slots 0 3000 1600 0 3000 1600 1000 100
2249 and-not obstruct_m5_medium
2250 and topbox
2251 shrink 1495
2252 grow 1495
2253
2254 layer MET5FILL met5fill_coarse
2255 or met5fill_medium
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]2256 calma 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2257#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2258
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2259end
2260
2261#-----------------------------------------------------------------------
2262cifinput
2263#-----------------------------------------------------------------------
2264# NOTE: All values in this section MUST be multiples of 25
2265# or else magic will scale below the allowed layout grid size
2266#-----------------------------------------------------------------------
2267
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2268style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2269 scalefactor 10 nanometers
2270 gridlimit 5
2271
2272 options ignore-unknown-layer-labels no-reconnect-labels
2273
2274#ifndef MIM
2275 ignore CAPM
2276 ignore CAPM2
2277#endif (!MIM)
2278#ifndef METAL5
2279 ignore MET4,VIA3
2280 ignore MET5,VIA4
2281#endif
2282 ignore NPC
2283 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2284 ignore CAPID
2285 ignore LDNTM
2286 ignore HVNTM
2287 ignore POLYMOD
2288 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2289 ignore FILLOBSPOLY
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]2290 ignore OUTLINE
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2291
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2292 layer pnp NWELL,WELLTXT,WELLPIN
2293 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2294 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2295 variants (vendor)
2296 labels WELLTXT port
2297 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2298 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2299 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2300 labels WELLPIN port
2301
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2302 layer nwell NWELL,WELLTXT,WELLPIN
2303 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2304 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2305 variants (vendor)
2306 labels WELLTXT port
2307 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2308 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2309 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2310 labels WELLPIN port
2311
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2312 templayer nwellarea NWELL
2313 copyup nwelcheck
2314
2315 # Copy nwell areas up for diffusion checks
2316 templayer xnwelcheck nwelcheck
2317 copyup nwelcheck
2318
2319 templayer hvarea HVI
2320 copyup hvcheck
2321
2322 # Copy high-voltage (HVI) areas up for diffusion checks
2323 templayer xhvcheck hvcheck
2324 copyup hvcheck
2325
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2326 # Always draw pwell under p-tap and n-diff. This is not always
2327 # necessary but works better with deep nwell for correct extraction.
2328 layer pwell TAP,DIFF
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2329 and-not NWELL,nwelcheck
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2330 grow 130
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2331 or SUBTXT,SUBPIN
Tim Edwards8c59e412021-03-25 22:06:10 -0400[diff] [blame]2332 grow 420
2333 shrink 420
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]2334 variants (vendor)
2335 labels SUBTXT port
2336 variants ()
2337 labels SUBTXT text
2338 variants *
2339 labels SUBPIN port
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2340
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2341 layer dnwell DNWELL
2342 labels DNWELL
2343
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2344 layer npn DNWELL
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2345 and-not NWELL,nwelcheck
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2346 and NPNID
2347
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2348 layer rpw PWRES
2349 and DNWELL
2350 labels PWRES
2351
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2352 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2353 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2354 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2355 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2356 and-not DIODE
2357 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2358 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2359 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2360 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2361 copyup ndifcheck
2362 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2363 variants (vendor)
2364 labels DIFFTXT port
2365 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2366 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2367 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2368 labels DIFFPIN port
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2369
2370 layer ndiff ndiffarea
2371
2372 # Copy ndiff areas up for contact checks
2373 templayer xndifcheck ndifcheck
2374 copyup ndifcheck
2375
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2376 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2377 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2378 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2379 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2380 and-not DIODE
2381 and-not DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2382 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2383 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2384 copyup ndifcheck
2385 labels DIFF
2386 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2387 variants (vendor)
2388 labels DIFFTXT port
2389 variants ()
2390 labels DIFFTXT text
2391 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2392 labels DIFFPIN port
2393
2394 layer mvndiff mvndiffarea
2395
2396 # Copy ndiff areas up for contact checks
2397 templayer mvxndifcheck mvndifcheck
2398 copyup mvndifcheck
2399
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2400 layer ndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2401 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2402 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2403 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2404 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2405 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2406 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2407 and-not LVTN
2408 labels DIFF
2409
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2410 layer ndiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2411 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2412 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2413 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2414 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2415 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2416 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2417 and LVTN
2418 labels DIFF
2419
2420 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2421 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2422 and-not HVI,hvcheck
2423 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2424 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2425
2426 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2427 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2428 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2429 labels DIFF
2430
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2431 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2432 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2433 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2434 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2435 and-not DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2436 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2437 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2438 copyup pdifcheck
2439 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2440 variants (vendor)
2441 labels DIFFTXT port
2442 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2443 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2444 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2445 labels DIFFPIN port
2446
2447 layer pdiff pdiffarea
2448
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2449 layer mvndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2450 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2451 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2452 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2453 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2454 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2455 and-not LVTN
2456 labels DIFF
2457
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2458 layer nndiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2459 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2460 and DIODE
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2461 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2462 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2463 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2464 and LVTN
2465 labels DIFF
2466
2467 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2468 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2469 and HVI,hvcheck
2470 and-not NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2471 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2472
2473 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2474 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2475 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2476 labels DIFF
2477
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2478 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2479 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2480 and NWELL,nwelcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2481 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2482 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2483 and-not DIODE
2484 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2485 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2486 copyup mvpdifcheck
2487 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2488 variants (vendor)
2489 labels DIFFTXT port
2490 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2491 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2492 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2493 labels DIFFPIN port
2494
2495 layer mvpdiff mvpdiffarea
2496
2497 # Copy pdiff areas up for contact checks
2498 templayer xpdifcheck pdifcheck
2499 copyup pdifcheck
2500
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2501 layer pdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2502 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2503 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2504 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2505 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2506 and-not LVTN
2507 and-not HVTP
2508 and DIODE
2509 labels DIFF
2510
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2511 layer pdiodelvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2512 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2513 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2514 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2515 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2516 and LVTN
2517 and-not HVTP
2518 and DIODE
2519 labels DIFF
2520
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2521 layer pdiodehvt DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2522 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2523 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2524 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2525 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2526 and-not LVTN
2527 and HVTP
2528 and DIODE
2529 labels DIFF
2530
2531 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2532 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2533 and-not HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2534 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2535
2536 # Define pfet areas as known pdiff, regardless of the presence of a well.
2537
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2538 templayer pfetarea DIFF,barediff
2539 and POLY
2540 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2541 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2542 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2543
2544 layer pfet pfetarea
2545 and-not LVTN
2546 and-not HVTP
2547 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2548 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2549 labels DIFF
2550
2551 layer scpfet pfetarea
2552 and-not LVTN
2553 and-not HVTP
2554 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2555 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2556 labels DIFF
2557
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2558 layer scpfethvt pfetarea
2559 and-not LVTN
2560 and HVTP
2561 and STDCELL
2562 labels DIFF
2563
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2564 layer ppu pfetarea
2565 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2566 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2567 and COREID
Tim Edwardsca2b9a92021-02-25 21:12:08 -0500[diff] [blame]2568 # Shrink-grow operation eliminates the smaller parasitie device
2569 # shrink 70
2570 # grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2571 labels DIFF
2572
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2573 layer pfetlvt pfetarea
2574 and LVTN
2575 labels DIFF
2576
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2577 layer pfetmvt pfetarea
2578 and HVTR
2579 labels DIFF
2580
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2581 layer pfethvt pfetarea
2582 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2583 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2584 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2585 labels DIFF
2586
2587 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2588 layer nwell pfetarea
Tim Edwardsa12a9412021-05-05 14:38:30 -0400[diff] [blame]2589 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2590 grow 180
2591
2592 # Copy mvpdiff areas up for contact checks
2593 templayer mvxpdifcheck mvpdifcheck
2594 copyup mvpdifcheck
2595
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2596 layer mvpdiode DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2597 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2598 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2599 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2600 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2601 and DIODE
2602 labels DIFF
2603
2604 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2605 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2606 and HVI,hvcheck
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2607 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2608
2609 # Define pfet areas as known pdiff,
2610 # regardless of the presence of a
2611 # well.
2612
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2613 templayer mvpfetarea DIFF,barediff
2614 and POLY
2615 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2616 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2617 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2618
2619 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2620 and-not ESDID
2621 labels DIFF
2622
2623 layer mvpfetesd mvpfetarea
2624 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2625 labels DIFF
2626
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2627 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2628 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2629 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2630 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2631 and-not DIODE
2632 and-not DIFFRES
2633 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2634 variants (vendor)
2635 labels DIFFTXT port
2636 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2637 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2638 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2639 labels DIFFPIN port
2640
2641 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2642 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2643 and NWELL,nwelcheck
2644 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2645 labels DIFF
2646
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2647 layer nfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2648 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2649 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2650 and-not PSDM
2651 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2652 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2653 and-not LVTN
2654 and-not SONOS
2655 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2656 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2657 labels DIFF
2658
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2659 layer scnfet DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2660 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2661 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2662 and-not PSDM
2663 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2664 and-not NWELL,nwelcheck
2665 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2666 and-not LVTN
2667 and-not SONOS
2668 and STDCELL
2669 labels DIFF
2670
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2671 layer npass DIFF,barediff
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2672 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2673 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2674 and-not PSDM
2675 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2676 and-not NWELL,nwelcheck
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2677 and COREID
2678 labels DIFF
2679
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2680 layer npd DIFF,barediff
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2681 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2682 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2683 and-not PSDM
2684 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2685 and-not NWELL,nwelcheck
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2686 and COREID
2687 # Shrink-grow operation eliminates the smaller npass device
2688 shrink 70
2689 grow 70
2690 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2691
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2692 # Devices abutting tap under gate are officially npd, not npass
2693 layer npd TAP
2694 grow 100
2695 and DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2696 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2697 and-not PSDM
2698 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2699 and-not NWELL,nwelcheck
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2700 and COREID
2701 labels DIFF
2702
2703 layer nfetlvt DIFF,barediff
2704 and POLY
2705 or baretrans
2706 and-not PSDM
2707 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2708 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2709 and LVTN
2710 and-not SONOS
2711 labels DIFF
2712
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2713 layer nsonos DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2714 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2715 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2716 and-not PSDM
2717 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2718 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2719 and LVTN
2720 and SONOS
2721 labels DIFF
2722
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2723 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2724 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2725 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2726 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2727 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2728 and-not HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2729 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2730 copyup nsubcheck
2731
2732 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2733 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2734
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2735 layer nsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2736 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2737 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2738 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2739 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2740 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2741
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2742 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2743 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2744 and POLY
2745 and COREID
2746 labels TAP
2747
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2748 templayer nsdexpand nsdarea
2749 grow 500
2750
2751 # Copy nsub areas up for contact checks
2752 templayer xnsubcheck nsubcheck
2753 copyup nsubcheck
2754
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2755 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2756 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2757 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2758 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2759 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2760 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2761 and-not pfetexpand
2762 copyup psubcheck
2763
2764 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2765 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2766
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2767 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2768 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2769 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2770 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2771 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2772 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2773
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2774 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2775 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2776 and POLY
2777 and COREID
2778 labels TAP
2779
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2780 templayer psdexpand psdarea
2781 grow 500
2782
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2783 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2784 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2785 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2786 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2787 and mvpfetexpand
2788 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2789 variants (vendor)
2790 labels DIFFTXT port
2791 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2792 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2793 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2794 labels DIFFPIN port
2795
2796 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2797 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2798 and NWELL,nwelcheck
2799 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2800 and-not mvrdpioedge
2801 labels DIFF
2802
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2803 templayer mvnfetarea DIFF,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2804 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2805 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2806 and-not PSDM
2807 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2809 and HVI,hvcheck
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2810 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2811
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2812 templayer mvnnfetarea DIFF,TAP,barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2813 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2814 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2815 and-not PSDM
2816 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2817 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2818 and HVI,hvcheck
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2819 and-not mvnfetarea
2820
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2821 layer mvnfetesd DIFF,barediff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2822 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2823 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2824 and-not PSDM
2825 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2826 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2827 and ESDID
2828 and-not mvnnfetarea
2829 labels DIFF
2830
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2831 layer mvnfet DIFF,barediff
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2832 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2833 or baretrans
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2834 and-not PSDM
2835 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2836 and HVI,hvcheck
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2837 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2838 and-not mvnnfetarea
2839 labels DIFF
2840
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2841 layer nnfet mvnnfetarea
2842 and LVID
2843 labels DIFF
2844
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2845 layer mvnnfet mvnnfetarea
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]2846 and-not LVID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2847 labels DIFF
2848
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2849 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2850 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2851 and NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2852 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2853 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2854 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2855 copyup mvnsubcheck
2856
2857 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2858 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2859
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2860 layer mvnsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2861 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2862 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2863 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2864 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2865
2866 templayer mvnsdexpand mvnsdarea
2867 grow 500
2868
2869 # Copy nsub areas up for contact checks
2870 templayer mvxnsubcheck mvnsubcheck
2871 copyup mvnsubcheck
2872
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]2873 templayer mvpsdarea DIFF,barediff
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2874 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2875 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2876 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2877 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2878 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2879 and-not mvpfetexpand
2880 copyup mvpsubcheck
2881
2882 layer mvpsd mvpsdarea
2883 labels DIFF
2884
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2885 layer mvpsd TAP,TAPTXT
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2886 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2887 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2888 labels TAP
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]2889 labels TAPTXT text
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2890
2891 templayer mvpsdexpand mvpsdarea
2892 grow 500
2893
2894 # Copy psub areas up for contact checks
2895 templayer xpsubcheck psubcheck
2896 copyup psubcheck
2897
2898 templayer mvxpsubcheck mvpsubcheck
2899 copyup mvpsubcheck
2900
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2901 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2902 and-not PSDM
2903 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2904 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2905 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2906 and-not pfetexpand
2907 and psdexpand
2908
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2909 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2910 and-not PSDM
2911 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2912 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2913 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2914 and nsdexpand
2915
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2916 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2917 and-not PSDM
2918 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2919 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2920 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2921 and-not mvpfetexpand
2922 and mvpsdexpand
2923
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2924 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2925 and-not PSDM
2926 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2927 and-not POLY
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2928 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2929 and mvnsdexpand
2930
2931 templayer hresarea POLY
2932 and RPM
2933 grow 3000
2934
2935 templayer uresarea POLY
2936 and URPM
2937 grow 3000
2938
2939 templayer diffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2940 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2941 grow 3000
2942
2943 templayer mvdiffresarea DIFFRES
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]2944 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2945 grow 3000
2946
2947 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2948
2949 layer pfet POLY
2950 and DIFF
2951 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2952 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2953 and-not STDCELL
2954
2955 layer scpfet POLY
2956 and DIFF
2957 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2958 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2959 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2960 and STDCELL
2961
2962 layer scpfethvt POLY
2963 and DIFF
2964 and diffresarea
2965 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2966 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2967 and STDCELL
2968
2969 templayer xpolyterm RPM,URPM
2970 and POLY
2971 and-not POLYRES
2972 # add back the 0.06um contact surround in the direction of the resistor
2973 grow 60
2974 and POLY
2975
2976 layer xpc xpolyterm
2977
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2978 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2979 and-not POLYRES
2980 and-not POLYSHORT
2981 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2982 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2983 and-not RPM
2984 and-not URPM
2985 copyup polycheck
2986
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2987 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2988 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2989 variants (vendor)
2990 labels POLYTXT port
2991 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2992 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2993 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2994 labels POLYPIN port
2995
2996 # Copy (non-resistor) poly areas up for contact checks
2997 templayer xpolycheck polycheck
2998 copyup polycheck
2999
3000 layer mrp1 POLY
3001 and POLYRES
3002 and-not RPM
3003 and-not URPM
3004 labels POLY
3005
3006 layer rmp POLY
3007 and POLYSHORT
3008 labels POLY
3009
3010 layer xhrpoly POLY
3011 and POLYRES
3012 and RPM
3013 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3014 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3015 and NPC
3016 and-not xpolyterm
3017 labels POLY
3018
3019 layer uhrpoly POLY
3020 and POLYRES
3021 and URPM
3022 and-not RPM
3023 and NPC
3024 and-not xpolyterm
3025 labels POLY
3026
3027 templayer ndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3028 or barecont
3029 and LI
3030 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3031 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3032 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3033 and-not NWELL,nwelcheck
3034 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3035
3036 layer ndc ndcbase
3037 grow 85
3038 shrink 85
3039 shrink 85
3040 grow 85
3041 or ndcbase
3042 labels CONT
3043
3044 templayer nscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3045 or barecont
3046 and LI
3047 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3048 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3049 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3050 and NWELL,nwelcheck
3051 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3052
3053 layer nsc nscbase
3054 grow 85
3055 shrink 85
3056 shrink 85
3057 grow 85
3058 or nscbase
3059 labels CONT
3060
3061 templayer pdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3062 or barecont
3063 and LI
3064 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3065 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3066 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3067 and NWELL,nwelcheck
3068 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3069
3070 layer pdc pdcbase
3071 grow 85
3072 shrink 85
3073 shrink 85
3074 grow 85
3075 or pdcbase
3076 labels CONT
3077
3078 templayer pdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3079 or barecont
3080 and LI
3081 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3082 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3083 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3084 and pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3085 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3086
3087 layer pdc pdcnowell
3088 grow 85
3089 shrink 85
3090 shrink 85
3091 grow 85
3092 or pdcnowell
3093 labels CONT
3094
3095 templayer pscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3096 or barecont
3097 and LI
3098 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3099 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3100 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3101 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3102 and-not pfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3103 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3104
3105 layer psc pscbase
3106 grow 85
3107 shrink 85
3108 shrink 85
3109 grow 85
3110 or pscbase
3111 labels CONT
3112
3113 templayer pcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3114 or barecont
3115 and LI
3116 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3117 and POLY
3118 and-not DIFF
3119 and-not RPM,URPM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3120
3121 layer pc pcbase
3122 grow 85
3123 shrink 85
3124 shrink 85
3125 grow 85
3126 or pcbase
3127 labels CONT
3128
3129 templayer ndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3130 or barecont
3131 and LI
3132 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3133 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3134 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3135 and DIODE
3136 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3137 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3138 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3139 and-not LVTN
3140
3141 layer ndic ndicbase
3142 grow 85
3143 shrink 85
3144 shrink 85
3145 grow 85
3146 or ndicbase
3147 labels CONT
3148
3149 templayer ndilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3150 or barecont
3151 and LI
3152 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3153 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3154 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3155 and DIODE
3156 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3157 and-not PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3158 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3159 and LVTN
3160
3161 layer ndilvtc ndilvtcbase
3162 grow 85
3163 shrink 85
3164 shrink 85
3165 grow 85
3166 or ndilvtcbase
3167 labels CONT
3168
3169 templayer pdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3170 or barecont
3171 and LI
3172 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3173 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3174 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3175 and DIODE
3176 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3177 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3178 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3179 and-not LVTN
3180 and-not HVTP
3181
3182 layer pdic pdicbase
3183 grow 85
3184 shrink 85
3185 shrink 85
3186 grow 85
3187 or pdicbase
3188 labels CONT
3189
3190 templayer pdilvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3191 or barecont
3192 and LI
3193 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3194 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3195 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3196 and DIODE
3197 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3198 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3199 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3200 and LVTN
3201 and-not HVTP
3202
3203 layer pdilvtc pdilvtcbase
3204 grow 85
3205 shrink 85
3206 shrink 85
3207 grow 85
3208 or pdilvtcbase
3209 labels CONT
3210
3211 templayer pdihvtcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3212 or barecont
3213 and LI
3214 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3215 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3216 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3217 and DIODE
3218 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3219 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3220 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3221 and-not LVTN
3222 and HVTP
3223
3224 layer pdihvtc pdihvtcbase
3225 grow 85
3226 shrink 85
3227 shrink 85
3228 grow 85
3229 or pdihvtcbase
3230 labels CONT
3231
3232 templayer mvndcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3233 or barecont
3234 and LI
3235 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3236 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3237 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3238 and-not NWELL,nwelcheck
3239 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3240
3241 layer mvndc mvndcbase
3242 grow 85
3243 shrink 85
3244 shrink 85
3245 grow 85
3246 or mvndcbase
3247 labels CONT
3248
3249 templayer mvnscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3250 or barecont
3251 and LI
3252 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3253 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3254 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3255 and NWELL,nwelcheck
3256 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3257
3258 layer mvnsc mvnscbase
3259 grow 85
3260 shrink 85
3261 shrink 85
3262 grow 85
3263 or mvnscbase
3264 labels CONT
3265
3266 templayer mvpdcbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3267 or barecont
3268 and LI
3269 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3270 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3271 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3272 and NWELL,nwelcheck
3273 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3274
3275 layer mvpdc mvpdcbase
3276 grow 85
3277 shrink 85
3278 shrink 85
3279 grow 85
3280 or mvpdcbase
3281 labels CONT
3282
3283 templayer mvpdcnowell CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3284 or barecont
3285 and LI
3286 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3287 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3288 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3289 and mvpfetexpand
3290 and MET1
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3291 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3292
3293 layer mvpdc mvpdcnowell
3294 grow 85
3295 shrink 85
3296 shrink 85
3297 grow 85
3298 or mvpdcnowell
3299 labels CONT
3300
3301 templayer mvpscbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3302 or barecont
3303 and LI
3304 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3305 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3306 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3307 and-not NWELL,nwelcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3308 and-not mvpfetexpand
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3309 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3310
3311 layer mvpsc mvpscbase
3312 grow 85
3313 shrink 85
3314 shrink 85
3315 grow 85
3316 or mvpscbase
3317 labels CONT
3318
3319 templayer mvndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3320 or barecont
3321 and LI
3322 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3323 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3324 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3325 and DIODE
3326 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3327 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3328 and-not LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3329 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3330
3331 layer mvndic mvndicbase
3332 grow 85
3333 shrink 85
3334 shrink 85
3335 grow 85
3336 or mvndicbase
3337 labels CONT
3338
3339 templayer nndicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3340 or barecont
3341 and LI
3342 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3343 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3344 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3345 and DIODE
3346 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3347 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3348 and LVTN
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3349 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3350
3351 layer nndic nndicbase
3352 grow 85
3353 shrink 85
3354 shrink 85
3355 grow 85
3356 or nndicbase
3357 labels CONT
3358
3359 templayer mvpdicbase CONT
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3360 or barecont
3361 and LI
3362 or licont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3363 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3364 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3365 and DIODE
3366 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3367 and-not NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3368 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3369
3370 layer mvpdic mvpdicbase
3371 grow 85
3372 shrink 85
3373 shrink 85
3374 grow 85
3375 or mvpdicbase
3376 labels CONT
3377
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3378 layer fomfill FOMFILL
3379 labels FOMFILL
3380
3381 layer polyfill POLYFILL
3382 labels POLYFILL
3383
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3384 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3385 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3386 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3387 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3388 variants (vendor)
3389 labels LITXT port
3390 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3391 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3392 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3393 labels LIPIN port
3394
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3395 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3396 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3397 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3398 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3399 variants (vendor)
3400 labels LITXT port
3401 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3402 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3403 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3404 labels LIPIN port
3405
3406 layer rli LI
3407 and LIRES,LISHORT
3408 labels LIRES,LISHORT
3409
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3410 layer lifill LIFILL
3411 labels LIFILL
3412
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3413 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3414 grow 95
3415 shrink 95
3416 shrink 85
3417 grow 85
3418 or MCON
3419 labels MCON
3420
3421 layer m1 MET1,MET1TXT,MET1PIN
3422 and-not MET1RES,MET1SHORT
3423 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3424 variants (vendor)
3425 labels MET1TXT port
3426 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3427 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3428 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3429 labels MET1PIN port
3430
3431 layer rm1 MET1
3432 and MET1RES,MET1SHORT
3433 labels MET1RES,MET1SHORT
3434
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3435 layer m1fill MET1FILL
3436 labels MET1FILL
3437
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3438#ifdef MIM
3439 layer mimcap MET3
3440 and CAPM
3441 labels CAPM
3442
3443 layer mimcc VIA3
3444 and CAPM
3445 grow 60
3446 grow 40
3447 shrink 40
3448 labels CAPM
3449
3450 layer mimcap2 MET4
3451 and CAPM2
3452 labels CAPM2
3453
3454 layer mim2cc VIA4
3455 and CAPM2
3456 grow 190
3457 grow 210
3458 shrink 210
3459 labels CAPM2
3460
3461#endif (MIM)
3462
3463 templayer m2cbase VIA1
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3464 and-not COREID
3465 grow 5
3466 or VIA1
3467 grow 50
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3468
3469 layer m2c m2cbase
3470 grow 30
3471 shrink 30
3472 shrink 130
3473 grow 130
3474 or m2cbase
3475
3476 layer m2 MET2,MET2TXT,MET2PIN
3477 and-not MET2RES,MET2SHORT
3478 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3479 variants (vendor)
3480 labels MET2TXT port
3481 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3482 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3483 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3484 labels MET2PIN port
3485
3486 layer rm2 MET2
3487 and MET2RES,MET2SHORT
3488 labels MET2RES,MET2SHORT
3489
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3490 layer m2fill MET2FILL
3491 labels MET2FILL
3492
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3493 templayer m3cbase VIA2
3494 grow 40
3495
3496 layer m3c m3cbase
3497 grow 60
3498 shrink 60
3499 shrink 140
3500 grow 140
3501 or m3cbase
3502
3503 layer m3 MET3,MET3TXT,MET3PIN
3504 and-not MET3RES,MET3SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3505 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3506 variants (vendor)
3507 labels MET3TXT port
3508 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3509 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3510 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3511 labels MET3PIN port
3512
3513 layer rm3 MET3
3514 and MET3RES,MET3SHORT
3515 labels MET3RES,MET3SHORT
3516
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3517 layer m3fill MET3FILL
3518 labels MET3FILL
3519
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3520#ifdef (METAL5)
3521
3522 templayer via3base VIA3
3523#ifdef MIM
3524 and-not CAPM
3525#endif (MIM)
3526 grow 60
3527
3528 layer via3 via3base
3529 grow 40
3530 shrink 40
3531 shrink 160
3532 grow 160
3533 or via3base
3534
3535 layer m4 MET4,MET4TXT,MET4PIN
3536 and-not MET4RES,MET4SHORT
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3537 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3538 variants (vendor)
3539 labels MET4TXT port
3540 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3541 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3542 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3543 labels MET4PIN port
3544
3545 layer rm4 MET4
3546 and MET4RES,MET4SHORT
3547 labels MET4RES,MET4SHORT
3548
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3549 layer m4fill MET4FILL
3550 labels MET4FILL
3551
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3552 layer m5 MET5,MET5TXT,MET5PIN
3553 and-not MET5RES,MET5SHORT
3554 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3555 variants (vendor)
3556 labels MET5TXT port
3557 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3558 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3559 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3560 labels MET5PIN port
3561
3562 layer rm5 MET5
3563 and MET5RES,MET5SHORT
3564 labels MET5RES,MET5SHORT
3565
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3566 layer m5fill MET5FILL
3567 labels MET5FILL
3568
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3569 templayer via4base VIA4
3570#ifdef MIM
3571 and-not CAPM2
3572#endif (MIM)
3573 grow 190
3574
3575 layer via4 via4base
3576 grow 210
3577 shrink 210
3578 shrink 590
3579 grow 590
3580 or via4base
3581#endif (METAL5)
3582
3583#ifdef REDISTRIBUTION
3584 layer metrdl RDL,RDLTXT,RDLPIN
3585 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3586 variants (vendor)
3587 labels RDLTXT port
3588 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3589 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3590 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3591 labels RDLPIN port
3592#endif
3593
3594 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3595 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3596 # the next layer up
3597
3598 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3599 and-not PSDM
3600 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3601 and POLY
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3602 copyup baretrans
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3603
3604 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3605 and-not PSDM
3606 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3607 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3608 and-not COREID
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3609 copyup barediff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3610
3611 # Handle contacts found by copyup
3612
3613 templayer ndiccopy CONT
3614 and LI
3615 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3616 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3617 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3618
3619 layer ndic ndiccopy
3620 grow 85
3621 shrink 85
3622 shrink 85
3623 grow 85
3624 or ndiccopy
3625 labels CONT
3626
3627 templayer mvndiccopy CONT
3628 and LI
3629 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3630 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3631 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3632
3633 layer mvndic mvndiccopy
3634 grow 85
3635 shrink 85
3636 shrink 85
3637 grow 85
3638 or mvndiccopy
3639 labels CONT
3640
3641 templayer pdiccopy CONT
3642 and LI
3643 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3644 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3645 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3646
3647 layer pdic pdiccopy
3648 grow 85
3649 shrink 85
3650 shrink 85
3651 grow 85
3652 or pdiccopy
3653 labels CONT
3654
3655 templayer mvpdiccopy CONT
3656 and LI
3657 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3658 and PSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3659 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3660
3661 layer mvpdic mvpdiccopy
3662 grow 85
3663 shrink 85
3664 shrink 85
3665 grow 85
3666 or mvpdiccopy
3667 labels CONT
3668
3669 templayer ndccopy CONT
3670 and ndifcheck
3671
3672 layer ndc ndccopy
3673 grow 85
3674 shrink 85
3675 shrink 85
3676 grow 85
3677 or ndccopy
3678 labels CONT
3679
3680 templayer mvndccopy CONT
3681 and mvndifcheck
3682
3683 layer mvndc mvndccopy
3684 grow 85
3685 shrink 85
3686 shrink 85
3687 grow 85
3688 or mvndccopy
3689 labels CONT
3690
3691 templayer pdccopy CONT
3692 and pdifcheck
3693
3694 layer pdc pdccopy
3695 grow 85
3696 shrink 85
3697 shrink 85
3698 grow 85
3699 or pdccopy
3700 labels CONT
3701
3702 templayer mvpdccopy CONT
3703 and mvpdifcheck
3704
3705 layer mvpdc mvpdccopy
3706 grow 85
3707 shrink 85
3708 shrink 85
3709 grow 85
3710 or mvpdccopy
3711 labels CONT
3712
3713 templayer pccopy CONT
3714 and polycheck
3715
3716 layer pc pccopy
3717 grow 85
3718 shrink 85
3719 shrink 85
3720 grow 85
3721 or pccopy
3722 labels CONT
3723
3724 templayer nsccopy CONT
3725 and nsubcheck
3726
3727 layer nsc nsccopy
3728 grow 85
3729 shrink 85
3730 shrink 85
3731 grow 85
3732 or nsccopy
3733 labels CONT
3734
3735 templayer mvnsccopy CONT
3736 and mvnsubcheck
3737
3738 layer mvnsc mvnsccopy
3739 grow 85
3740 shrink 85
3741 shrink 85
3742 grow 85
3743 or mvnsccopy
3744 labels CONT
3745
3746 templayer psccopy CONT
3747 and psubcheck
3748
3749 layer psc psccopy
3750 grow 85
3751 shrink 85
3752 shrink 85
3753 grow 85
3754 or psccopy
3755 labels CONT
3756
3757 templayer mvpsccopy CONT
3758 and mvpsubcheck
3759
3760 layer mvpsc mvpsccopy
3761 grow 85
3762 shrink 85
3763 shrink 85
3764 grow 85
3765 or mvpsccopy
3766 labels CONT
3767
3768 # Find contacts not covered in
3769 # metal and pull them into the
3770 # next layer up
3771
3772 templayer gencont CONT
3773 and LI
3774 and-not DIFF,TAP
3775 and-not POLY
3776 and-not DIODE
3777 and-not nsubcheck
3778 and-not psubcheck
3779 and-not mvnsubcheck
3780 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3781 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3782 copyup barelicont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3783
3784 templayer barecont CONT
3785 and-not LI
3786 and-not nsubcheck
3787 and-not psubcheck
3788 and-not mvnsubcheck
3789 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3790 and-not CORELI
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]3791 copyup barecont
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3792
3793 layer glass GLASS,PADTXT,PADPIN
3794 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3795 variants (vendor)
3796 labels PADTXT port
3797 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3798 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3799 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3800 labels PADPIN port
3801
3802 templayer boundary BOUND,STDCELL,PADCELL
3803 boundary
3804
3805 layer comment LVSTEXT
3806 labels LVSTEXT text
3807
3808 layer comment TTEXT
3809 labels TTEXT text
3810
3811 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3812 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3813
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3814 layer obsactive FILLOBSFOM
3815
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3816# MOS Varactor
3817
3818 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3819 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3820 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3821 and NWELL,nwelcheck
3822 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3823 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3824 # NOTE: Else forms a varactor that is not in the vendor netlist.
3825 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3826 labels POLY
3827
3828 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3829 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3830 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3831 and NWELL,nwelcheck
3832 and-not HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3833 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3834 labels POLY
3835
3836 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3837 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3838 and NSDM
Tim Edwardsb78b1f12021-03-31 21:32:10 -0400[diff] [blame]3839 and NWELL,nwelcheck
3840 and HVI,hvcheck
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3841 labels POLY
3842
3843 calma NWELL 64 20
3844 calma DIFF 65 20
3845 calma DNWELL 64 18
3846 calma PWRES 64 13
3847 calma TAP 65 44
3848 # LVTN
3849 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3850 # HVTR
3851 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3852 # HVTP
3853 calma HVTP 78 44
3854 # SONOS (TUNM)
3855 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3856 # NSDM (NPLUS)
3857 calma NSDM 93 44
3858 # PSDM (PPLUS)
3859 calma PSDM 94 20
3860 # HVI (THKOX)
3861 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3862 # NPC
3863 calma NPC 95 20
3864 # P+ POLY MASK
3865 calma RPM 86 20
3866 calma URPM 79 20
3867 calma LDNTM 11 44
3868 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3869 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3870 calma POLYRES 66 13
3871 # Diffusion resistor ID mark
3872 calma DIFFRES 65 13
3873 calma POLY 66 20
3874 calma POLYMOD 66 83
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]3875 # 3.3V native FET ID mark
3876 calma LVID 81 60
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3877 # Diode ID mark
3878 calma DIODE 81 23
3879 # Bipolar NPN mark
3880 calma NPNID 82 20
3881 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3882 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3883 # Capacitor ID
3884 calma CAPID 82 64
3885 # Core area ID mark
3886 calma COREID 81 2
3887 # Standard cell ID mark
3888 calma STDCELL 81 4
3889 # Padframe cell ID mark
3890 calma PADCELL 81 3
3891 # Seal ring ID mark
3892 calma SEALID 81 1
3893 # Low tap density ID mark
3894 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3895 # ESD area ID
3896 calma ESDID 81 19
Tim Edwardsb0b06752021-01-22 09:06:11 -0500[diff] [blame]3897 calma OUTLINE 236 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3898
3899 # LICON
3900 calma CONT 66 44
3901 calma LI 67 20
3902 calma MCON 67 44
3903
3904 calma MET1 68 20
3905 calma VIA1 68 44
3906 calma MET2 69 20
3907 calma VIA2 69 44
3908 calma MET3 70 20
3909#ifdef METAL5
3910 calma VIA3 70 44
3911 calma MET4 71 20
3912 calma VIA4 71 44
3913 calma MET5 72 20
3914#endif
3915#ifdef REDISTRIBUTION
3916 calma RDL 74 20
3917#endif
3918 calma GLASS 76 20
3919
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3920 calma SUBTXT 64 59
3921 calma PADTXT 76 5
3922 calma DIFFTXT 65 6
3923 calma TAPTXT 65 5
3924 calma WELLTXT 64 5
3925 calma LITXT 67 5
3926 calma POLYTXT 66 5
3927 calma MET1TXT 68 5
3928 calma MET2TXT 69 5
3929 calma MET3TXT 70 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3930#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3931 calma MET4TXT 71 5
3932 calma MET5TXT 72 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3933#endif
3934#ifdef REDISTRIBUTION
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3935 calma RDLTXT 74 5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3936#endif
3937
3938 calma LIRES 67 13
3939 calma MET1RES 68 13
3940 calma MET2RES 69 13
3941 calma MET3RES 70 13
3942#ifdef METAL5
3943 calma MET4RES 71 13
3944 calma MET5RES 72 13
3945#endif
3946
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3947 calma LIFILL 56 28
3948 calma MET1FILL 36 28
3949 calma MET2FILL 41 28
3950 calma MET3FILL 34 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3951#ifdef METAL5
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3952 calma MET4FILL 51 28
3953 calma MET5FILL 59 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3954#endif
3955
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3956 calma POLYSHORT 66 15
3957 calma LISHORT 67 15
3958 calma MET1SHORT 68 15
3959 calma MET2SHORT 69 15
3960 calma MET3SHORT 70 15
3961#ifdef METAL5
3962 calma MET4SHORT 71 15
3963 calma MET5SHORT 72 15
3964#endif
3965
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3966 calma SUBPIN 122 16
3967 calma PADPIN 76 16
3968 calma DIFFPIN 65 16
3969 calma POLYPIN 66 16
3970 calma WELLPIN 64 16
3971 calma LIPIN 67 16
3972 calma MET1PIN 68 16
3973 calma MET2PIN 69 16
3974 calma MET3PIN 70 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3975#ifdef METAL5
Tim Edwards0c742ad2021-03-02 17:33:13 -0500[diff] [blame]3976 calma MET4PIN 71 16
3977 calma MET5PIN 72 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3978#endif
3979#ifdef REDISTRIBUTION
3980 calma RDLPIN 74 16
3981#endif
3982
3983 calma BOUND 235 4
3984
3985 calma LVSTEXT 83 44
3986
3987#ifdef (MIM)
3988 calma CAPM 89 44
3989 calma CAPM2 97 44
3990#endif (MIM)
3991
3992 calma FILLOBSM1 62 24
3993 calma FILLOBSM2 105 52
3994 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3995 calma FILLOBSM4 112 4
3996 calma FILLOBSFOM 22 24
3997 calma FILLOBSPOLY 33 24
3998
Tim Edwardsacba4072021-01-06 21:43:28 -0500[diff] [blame]3999 calma FOMFILL 23 28
4000 calma POLYFILL 28 28
4001 calma LIFILL 56 28
4002 calma MET1FILL 36 28
4003 calma MET2FILL 41 28
4004 calma MET3FILL 34 28
4005 calma MET4FILL 51 28
4006 calma MET5FILL 59 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4007
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4008#-----------------------------------------------------------------------
4009
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4010style rdlimport
4011 # This style is for reading shapes generated with the RDL layers
4012
4013 scalefactor 10 nanometers
4014 gridlimit 5
4015
4016 options ignore-unknown-layer-labels no-reconnect-labels
4017
4018 layer mrdl RDL
4019 layer mrdlc RDLC
4020
4021 calma RDL 10 0
4022 calma RDLC 20 0
4023
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4024end
4025
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4026#-----------------------------------------------------
4027# Digital flow maze router cost parameters
4028#-----------------------------------------------------
4029
4030mzrouter
4031end
4032
4033#-----------------------------------------------------
4034# Vendor DRC rules
4035#-----------------------------------------------------
4036
4037drc
4038
4039 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4040 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4041 cifstyle drc
4042
4043 variants (fast),(full)
4044
4045#-----------------------------
4046# DNWELL
4047#-----------------------------
4048
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4049 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
4050 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4051 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4052 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4053
4054 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4055 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4056 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4057 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4058 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4059
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4060 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
4061 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4062 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4063
4064#-----------------------------
4065# NWELL
4066#-----------------------------
4067
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4068 width allnwell 840 "N-well width < %d (nwell.1)"
4069 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4070
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4071 variants (full)
4072 cifmaxwidth nwell_missing_tap 0 bend_illegal \
4073 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4074
4075 cifspacing mvnwell lvnwell 2000 touching_illegal \
4076 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
4077 cifspacing mvnwell mvnwell 2000 touching_ok \
4078 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4079 variants (fast),(full)
4080
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4081#-----------------------------
4082# DIFF
4083#-----------------------------
4084
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4085 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4086 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4087 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4088 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4089
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4090 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
4091 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
4092 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
4093 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
4094 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
4095 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4096 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4097 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4098 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4099 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4100 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4101 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4102 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4103 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4104 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4105 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4106 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4107 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4108 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4109 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4110 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4111 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4112 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4113 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4114 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4115 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4116 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4117 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4118 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4119 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4120 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4121 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4122 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4123 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4124 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4125 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]4126
4127variants (full)
4128 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
4129 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
4130variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4131
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4132 spacing allnfets allpactivenonfet 270 touching_illegal \
4133 "nFET cannot abut P-diffusion (diff/tap.3)"
4134 spacing allpfets allnactivenonfet 270 touching_illegal \
4135 "pFET cannot abut N-diffusion (diff/tap.3)"
4136
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4137 # Butting junction rules
4138 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4139 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4140 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4141 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4142 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4143 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4144 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4145 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4146
4147 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4148 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4149 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4150 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4151 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4152 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4153 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4154 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
4155
4156 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4157 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
4158 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
4159
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4160 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
4161 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
4162
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4163 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4164
4165 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]4166 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4167
4168 # Latchup rules
4169 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4170 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4171 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4172 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4173 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4174 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4175
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4176 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4177
4178#-----------------------------
4179# POLY
4180#-----------------------------
4181
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4182 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
4183 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4184
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4185 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]4186 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4187 75 corner_ok allfets \
4188 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4189 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4190 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4191 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4192 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4193 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4194 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4195 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4196 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
4197 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4198 rect_only allfets "No bends in transistors (poly.11)"
4199 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4200 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4201 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4202 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4203 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4204
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4205 variants (fast)
4206
4207 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4208 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
4209 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
4210 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
Tim Edwardsf788cea2021-04-20 12:43:52 -0400[diff] [blame]4211 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \
4212 "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)"
4213
4214 # Minimum width requirement means actual spacing from res to ndiff has to be
4215 # constructed from mask rules. These supercede the simpler checks.
4216
4217 variants (full)
4218
4219 cifmaxwidth rpm_nsd_check 0 bend_illegal \
4220 "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)"
4221 cifmaxwidth rpm_poly_check 0 bend_illegal \
4222 "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)"
4223 cifmaxwidth rpm_hvntm_check 0 bend_illegal \
4224 "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)"
4225
4226 variants (fast,full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4227
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4228 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4229
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4230#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4231# HVTP
4232#--------------------------------------------------------------------
4233
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4234 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4235 360 touching_illegal \
4236 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
4237
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4238 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4239 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
4240
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4241#--------------------------------------------------------------------
4242# LVTN
4243#--------------------------------------------------------------------
4244
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4245 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
4246 allfetsnolvt 360 touching_illegal \
4247 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4248
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4249 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4250 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4251 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4252
4253 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4254 edge4way allfetsnolvt allactivenonfet 415 \
4255 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4256 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4257
4258#--------------------------------------------------------------------
4259# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4260#--------------------------------------------------------------------
4261
4262# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4263
4264#--------------------------------------------------------------------
4265# CONT (LICON, contact between poly/diff and LI)
4266#--------------------------------------------------------------------
4267
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4268 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4269 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4270 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4271 width psc/li 170 "P-tap contact width < %d (licon.1)"
4272 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4273 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4274 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4275
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4276 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4277 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4278 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4279
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4280 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4281 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4282 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4283 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4284 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4285 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4286
4287 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4288 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4289 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4290 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4291 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4292 "Diffusion contact spacing < %d (licon.2)"
4293 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4294
4295 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4296 "poly contact spacing to diffusion < %d (licon.14)"
4297 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4298 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4299
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4300 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4301 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4302 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4303 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4304 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4305 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4306 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4307 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4308 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4309 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4310 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4311 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4312
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4313 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4314 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4315 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4316 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4317 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4318 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4319 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4320 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4321 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4322
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4323 spacing psc/a allnactivenontap 60 touching_illegal \
4324 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4325 spacing nsc/a allpactivenontap 60 touching_illegal \
4326 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4327
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4328 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4329 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4330 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4331 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4332 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4333 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4334 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4335 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4336 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4337
4338 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4339 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4340 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4341 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4342
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4343 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4344 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4345 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4346 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4347 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4348 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4349 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4350 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4351
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4352 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4353 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4354 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4355 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4356
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4357 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4358 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4359 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4360 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4361 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4362 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4363 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4364 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4365
4366 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4367 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4368 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4369 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4370
4371 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4372 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4373 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4374 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4375
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4376 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4377
4378#-------------------------------------------------------------
4379# LI - Local interconnect layer
4380#-------------------------------------------------------------
4381
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4382variants *
4383
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4384 width *li 170 "Local interconnect width < %d (li.1)"
4385 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4386
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4387 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4388 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4389
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4390 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4391 # no special layers for the contacts in core cells, so they must be included
4392 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4393 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4394 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4395
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4396 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4397 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4398
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4399 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4400 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4401
4402 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4403 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4404 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4405
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4406 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4407
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4408 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4409 angles coreli 45 \
4410 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4411
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4412#-------------------------------------------------------------
4413# MCON - Contact between local interconnect and metal1
4414#-------------------------------------------------------------
4415
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4416 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4417 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4418
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4419 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4420
4421#-------------------------------------------------------------
4422# METAL1 -
4423#-------------------------------------------------------------
4424
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4425 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4426 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4427 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4428
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4429 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4430 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4431 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4432 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4433
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4434 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4435
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4436variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4437 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4438 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4439 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4440 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4441
4442variants (full)
4443 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4444 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4445
4446 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4447 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4448variants *
4449
4450#--------------------------------------------------
4451# VIA1
4452#--------------------------------------------------
4453
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4454 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4455 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4456 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4457 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4458 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4459 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4460
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4461 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4462
4463#--------------------------------------------------
4464# METAL2 -
4465#--------------------------------------------------
4466
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4467 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4468 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4469 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4470
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4471 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4472
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4473variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4474 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4475 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4476 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4477 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4478
4479variants (full)
4480 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4481 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4482
4483 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4484 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4485variants *
4486
4487#--------------------------------------------------
4488# VIA2
4489#--------------------------------------------------
4490
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4491 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4492
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4493 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4494
4495 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4496 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4497 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4498
4499 exact_overlap v2/m2
4500
4501#--------------------------------------------------
4502# METAL3 -
4503#--------------------------------------------------
4504
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4505 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4506 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4507 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4508
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4509 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4510
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4511variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4512 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4513 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4514 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4515 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4516variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4517 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4518 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4519variants *
4520
4521
4522#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4523#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4524#--------------------------------------------------
4525# VIA3 - Requires METAL5 Module
4526#--------------------------------------------------
4527
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4528 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4529 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4530 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4531 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4532 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4533 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4534
4535 exact_overlap v3/m3
4536
4537#-----------------------------
4538# METAL4 - METAL4 Module
4539#-----------------------------
4540
4541variants *
4542
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4543 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4544 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4545 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4546
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4547 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4548
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4549variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4550 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4551 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4552 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4553 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4554variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4555 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4556 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4557variants *
4558
4559#--------------------------------------------------
4560# VIA4 - Requires METAL5 Module
4561#--------------------------------------------------
4562
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4563 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4564 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4565 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4566 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4567
4568 exact_overlap v4/m4
4569
4570#-----------------------------
4571# METAL5 - METAL5 Module
4572#-----------------------------
4573
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4574 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4575 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4576 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4577
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4578 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4579
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4580#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4581#endif (METAL5)
4582
4583#ifdef REDISTRIBUTION
4584
4585variants (full)
4586
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4587 width metrdl 10000 "RDL width < %d (rdl.1)"
4588 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4589 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4590 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4591
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4592variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4593
4594#endif (REDISTRIBUTION)
4595
4596#--------------------------------------------------
4597# NMOS, PMOS
4598#--------------------------------------------------
4599
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4600 edge4way *poly allfetsstd 420 allfets 0 0 \
4601 "Transistor width < %d (diff/tap.2)"
4602 edge4way *poly allfetsspecial 360 allfets 0 0 \
4603 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4604 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4605 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4606 edge4way *poly ppu 140 allfets 0 0 \
4607 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4608
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4609 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4610 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4611
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4612 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4613 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards826be502021-02-14 20:19:48 -0500[diff] [blame]4614 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
4615 "poly spacing to diffusion tap < %d (poly.5)"
4616 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
4617 "poly spacing to diffusion tap < %d (poly.5)"
4618 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4619 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4620
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4621 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4622 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4623 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4624 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]4625 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4626 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4627 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4628 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4629
4630 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4631 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4632 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4633
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4634 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4635 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4636
4637 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4638 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4639 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4640
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4641 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4642 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4643
4644 # Minimum length of MV FETs. Note that this is larger than the minimum
4645 # width (0.29um), so an edge rule is required
4646
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4647 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4648 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4649
4650 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4651 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4652
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4653 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4654 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4655
4656#--------------------------------------------------
4657# mrp1 (N+ poly resistor)
4658#--------------------------------------------------
4659
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4660 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4661
4662#--------------------------------------------------
4663# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4664# uhrpoly (P+ poly resistor, 2kOhm/sq)
4665#--------------------------------------------------
4666
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4667 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4668 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4669 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4670
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4671 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4672 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4673
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4674 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4675 "Poly resistor spacing to poly < %d (poly.9)"
4676
4677 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4678 "Poly resistor spacing to poly < %d (poly.9)"
4679
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4680 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4681 "Poly resistor spacing to poly < %d (poly.9)"
4682
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4683 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4684 "Poly resistor spacing to diffusion < %d (poly.9)"
4685
4686#------------------------------------
4687# nsonos
4688#------------------------------------
4689
4690variants (full)
4691 cifmaxwidth bbox_missing 0 bend_illegal \
4692 "SONOS transistor must be in cell with abutment box (tunm.8)"
4693variants (fast),(full)
4694
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4695#------------------------------------
4696# MOS Varactor device rules
4697#------------------------------------
4698
4699 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4700 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4701
4702 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4703 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4704
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4705 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4706 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4707
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4708variants (full)
4709 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4710 "N-well overlap of varactor poly < 0.15um (varac.5)"
4711
4712 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4713 "Varactor N-well must not contain P+ diffusion (varac.7)"
4714variants (fast),(full)
4715
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4716#ifdef MIM
4717#-----------------------------------------------------------
4718# MiM CAP (CAPM) -
4719#-----------------------------------------------------------
4720
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4721 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4722 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4723 spacing *mimcap via3/m3 80 touching_illegal \
4724 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4725 surround *mimcc *mimcap 80 absence_illegal \
4726 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4727 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4728
4729 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4730 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4731 spacing via2 *mimcap 100 touching_illegal \
4732 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4733 spacing *mimcap *metal3/m3 500 surround_ok \
4734 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4735
4736variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4737 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4738 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4739variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4740
4741 # MiM cap contact rules (VIA3)
4742
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4743 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4744 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4745 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4746 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4747 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4748
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4749 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4750 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4751 spacing *mimcap2 via4/m4 10 touching_illegal \
4752 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4753 surround *mim2cc *mimcap2 10 absence_illegal \
4754 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4755 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4756
4757 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4758 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4759 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4760 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4761 spacing *mimcap2 *metal4/m4 500 surround_ok \
4762 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4763
4764variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4765 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4766 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4767variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4768
4769 # MiM cap contact rules (VIA4)
4770
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4771 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4772 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4773 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4774 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4775 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4776 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4777
4778#endif (MIM)
4779
4780#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4781# HVNTM
4782#----------------------------
4783variants (full)
4784 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4785 "HVNTM spacing < %d (hvntm.2)"
4786variants (fast),(full)
4787
4788#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4789# End DRC style
4790#----------------------------
4791
4792end
4793
4794#----------------------------
4795# LEF format definitions
4796#----------------------------
4797
4798lef
4799
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4800 masterslice pwell pwell PWELL substrate
4801 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4802
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4803 routing li li1 LI1 LI li
4804
4805 routing m1 met1 MET1 m1
4806 routing m2 met2 MET2 m2
4807 routing m3 met3 MET3 m3
4808#ifdef METAL5
4809 routing m4 met4 MET4 m4
4810 routing m5 met5 MET5 m5
4811#endif (METAL5)
4812#ifdef REDISTRIBUTION
4813 routing mrdl met6 MET6 m6 MRDL METRDL
4814#endif
4815
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4816 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4817 cut m2c via via1 VIA VIA1 cont2 via12
4818 cut m3c via2 VIA2 cont3 via23
4819#ifdef METAL5
4820 cut via3 via3 VIA3 cont4 via34
4821 cut via4 via4 VIA4 cont5 via45
4822#endif (METAL5)
4823
4824 obs obsli li1
4825 obs obsm1 met1
4826 obs obsm2 met2
4827 obs obsm3 met3
4828
4829#ifdef METAL5
4830 obs obsm4 met4
4831 obs obsm5 met5
4832#endif (METAL5)
4833#ifdef REDISTRIBUTION
4834 obs obsmrdl met6
4835#endif
4836
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4837 # NOTE: obsmcon only used with li1, not obsli.
4838 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4839
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4840 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4841 obs obsm1 via
4842 obs obsm2 via2
4843#ifdef METAL5
4844 obs obsm3 via3
4845 obs obsm4 via4
4846#endif (METAL5)
4847
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4848end
4849
4850#-----------------------------------------------------
4851# Device and Parasitic extraction
4852#-----------------------------------------------------
4853
4854
4855extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4856 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4857 cscale 1
4858 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4859 # dimensions must be in units of microns in the extract file.
4860 # Use extract style "ngspice(si)" to override this and produce
4861 # a file with SI units for length/area.
4862
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4863 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4864 lambda 1E6
4865 variants (si)
4866 lambda 1.0
4867 variants *
4868
4869 units microns
4870 step 7
4871 sidehalo 2
4872
4873 # NOTE: MiM cap layers have been purposely put out of order,
4874 # may want to reconsider.
4875
4876 planeorder dwell 0
4877 planeorder well 1
4878 planeorder active 2
4879 planeorder locali 3
4880 planeorder metal1 4
4881 planeorder metal2 5
4882 planeorder metal3 6
4883#ifdef METAL5
4884 planeorder metal4 7
4885 planeorder metal5 8
4886#ifdef REDISTRIBUTION
4887 planeorder metali 9
4888 planeorder block 10
4889 planeorder comment 11
4890 planeorder cap1 12
4891 planeorder cap2 13
4892#else (!REDISTRIBUTION)
4893 planeorder block 9
4894 planeorder comment 10
4895 planeorder cap1 11
4896 planeorder cap2 12
4897#endif (!REDISTRIBUTION)
4898#else (!METAL5)
4899#ifdef REDISTRIBUTION
4900 planeorder metali 7
4901 planeorder block 8
4902 planeorder comment 9
4903 planeorder cap1 10
4904 planeorder cap2 11
4905#else (!REDISTRIBUTION)
4906 planeorder block 7
4907 planeorder comment 8
4908 planeorder cap1 9
4909 planeorder cap2 10
4910#endif (!REDISTRIBUTION)
4911#endif (!METAL5)
4912
4913 height dnwell -0.1 0.1
4914 height nwell,pwell 0.0 0.2062
4915 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4916 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4917 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4918 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4919 height alldiffcont 0.3262 0.61
4920 height pc 0.5062 0.43
4921 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4922 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4923 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4924 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4925 height v1 1.7361 0.27
4926 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4927 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4928 height v2 2.3661 0.42
4929 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4930 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4931#ifdef METAL5
4932 height v3 3.6311 0.39
4933 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4934 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4935 height v4 4.8661 0.505
4936 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4937 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4938 height mimcap 2.4661 0.2
4939 height mimcap2 3.7311 0.2
4940 height mimcc 2.6661 0.12
4941 height mim2cc 3.9311 0.09
4942#ifdef REDISTRIBUTION
Tim Edwardsd8c15952021-04-29 15:52:27 -0400[diff] [blame]4943 height mrdlc 6.6311 0.63
4944 height mrdl 7.2611 3.0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4945#endif (!REDISTRIBUTION)
4946#endif (!METAL5)
4947
4948 # Antenna check parameters
4949 # Note that checks w/diode diffusion are not modeled
4950 model partial
4951 antenna poly sidewall 50 none
4952 antenna allcont surface 3 none
4953 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4954 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4955 antenna m1,m2,m3 sidewall 400 2600 400
4956 antenna v1 surface 3 0 18
4957 antenna v2 surface 6 0 36
4958#ifdef METAL5
4959 antenna m4,m5 sidewall 400 2600 400
4960 antenna v3,v4 surface 6 0 36
4961#endif (METAL5)
4962
4963 tiedown alldiffnonfet
4964
Tim Edwardsbafbda72021-04-05 16:54:37 -0400[diff] [blame]4965 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4966
4967# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4968
4969# Resistances are in milliohms per square
4970# Optional 3rd argument is the corner adjustment fraction
4971# Device values come from trtc.cor (typical corner)
4972 resist (dnwell)/dwell 2200000
4973 resist (pwell)/well 3050000
4974 resist (nwell)/well 1700000
4975 resist (rpw)/well 3050000 0.5
4976 resist (*ndiff,nsd)/active 120000
4977 resist (*pdiff,*psd)/active 197000
4978 resist (*mvndiff,mvnsd)/active 114000
4979 resist (*mvpdiff,*mvpsd)/active 191000
4980
4981 resist ndiffres/active 120000 0.5
4982 resist pdiffres/active 197000 0.5
4983 resist mvndiffres/active 114000 0.5
4984 resist mvpdiffres/active 191000 0.5
4985 resist mrp1/active 48200 0.5
4986 resist xhrpoly/active 319800 0.5
4987 resist uhrpoly/active 2000000 0.5
4988
4989 resist (allpolynonres)/active 48200
4990 resist rmp/active 48200
4991
4992 resist (allli)/locali 12200
4993 resist (allm1)/metal1 125
4994 resist (allm2)/metal2 125
4995 resist (allm3)/metal3 47
4996#ifdef METAL5
4997 resist (allm4)/metal4 47
4998 resist (allm5)/metal5 29
4999#endif (METAL5)
5000#ifdef REDISTRIBUTION
5001 resist mrdl/metali 5
5002#endif (REDISTRIBUTION)
5003
5004 contact ndc,nsc 15000
5005 contact pdc,psc 15000
5006 contact mvndc,mvnsc 15000
5007 contact mvpdc,mvpsc 15000
5008 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5009 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5010 contact m2c 4500
5011 contact m3c 3410
5012#ifdef METAL5
5013#ifdef MIM
5014 contact mimcc 4500
5015 contact mim2cc 3410
5016#endif (MIM)
5017 contact via3 3410
5018 contact via4 380
5019#endif (METAL5)
5020#ifdef REDISTRIBUTION
5021 contact mrdlc 6
5022#endif (REDISTRIBUTION)
5023
5024#-------------------------------------------------------------------------
5025# Parasitic capacitance values: Use document (...)
5026#-------------------------------------------------------------------------
5027# This uses the new "default" definitions that determine the intervening
5028# planes from the planeorder stack, take care of the reflexive sideoverlap
5029# definitions, and generally clean up the section and make it more readable.
5030#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5031# Also uses "units microns" statement. All values are taken from the
5032# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
5033# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5034#-------------------------------------------------------------------------
5035# Remember that device capacitances to substrate are taken care of by the
5036# models. Thus, active and poly definitions ignore all "fet" types.
5037# fet types are excluded when computing parasitic capacitance to
5038# active from layers above them because poly is a shield; fet types are
5039# included for parasitics from layers above to poly. Resistor types
5040# should be removed from all parasitic capacitance calculations, or else
5041# they just create floating caps. Technically, the capacitance probably
5042# should be split between the two terminals. Unsure of the correct model.
5043#-------------------------------------------------------------------------
5044
5045#n-well
5046# NOTE: This value not found in PEX files
5047defaultareacap nwell well 120
5048
5049#n-active
5050# Rely on device models to capture *ndiff area cap
5051# Do not extract parasitics from resistors
5052# defaultareacap allnactivenonfet active 790
5053# defaultperimeter allnactivenonfet active 280
5054
5055#p-active
5056# Rely on device models to capture *pdiff area cap
5057# Do not extract parasitics from resistors
5058# defaultareacap allpactivenonfet active 810
5059# defaultperimeter allpactivenonfet active 300
5060
5061#poly
5062# Do not extract parasitics from resistors
5063# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5064# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5065# defaultperimeter allpolynonfet active 57
5066
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5067 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5068 defaultareacap *poly active nwell,obswell,pwell well 106
5069 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5070
5071#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5072 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5073 defaultareacap allli locali nwell,obswell,pwell well 37
5074 defaultperimeter allli locali nwell,obswell,pwell well 55
5075 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5076
5077#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5078 defaultoverlap allli locali allactivenonfet active 37
5079 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5080
5081#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5082 defaultoverlap allli locali allpolynonres active 94
5083 defaultsideoverlap allli locali allpolynonres active 52
5084 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5085
5086#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5087 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5088 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
5089 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5090 defaultoverlap allm1 metal1 nwell well 26
5091
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5092#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5093 defaultoverlap allm1 metal1 allactivenonfet active 26
5094 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5095
5096#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5097 defaultoverlap allm1 metal1 allpolynonres active 45
5098 defaultsideoverlap allm1 metal1 allpolynonres active 47
5099 defaultsideoverlap *poly active allm1 metal1 17
5100
5101#metal1->locali
5102 defaultoverlap allm1 metal1 allli locali 114
5103 defaultsideoverlap allm1 metal1 allli locali 59
5104 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5105
5106#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]5107 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5108 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
5109 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
5110 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5111
5112#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5113 defaultoverlap allm2 metal2 allactivenonfet active 17
5114 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5115
5116#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5117 defaultoverlap allm2 metal2 allpolynonres active 24
5118 defaultsideoverlap allm2 metal2 allpolynonres active 41
5119 defaultsideoverlap *poly active allm2 metal2 11
5120
5121#metal2->locali
5122 defaultoverlap allm2 metal2 allli locali 38
5123 defaultsideoverlap allm2 metal2 allli locali 46
5124 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5125
5126#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5127 defaultoverlap allm2 metal2 allm1 metal1 134
5128 defaultsideoverlap allm2 metal2 allm1 metal1 67
5129 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5130
5131#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5132 defaultsidewall allm3 metal3 63
5133 defaultoverlap allm3 metal3 nwell well 12
5134 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
5135 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5136
5137#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5138 defaultoverlap allm3 metal3 allactive active 12
5139 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5140
5141#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5142 defaultoverlap allm3 metal3 allpolynonres active 16
5143 defaultsideoverlap allm3 metal3 allpolynonres active 44
5144 defaultsideoverlap *poly active allm3 metal3 9
5145
5146#metal3->locali
5147 defaultoverlap allm3 metal3 allli locali 21
5148 defaultsideoverlap allm3 metal3 allli locali 47
5149 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5150
5151#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5152 defaultoverlap allm3 metal3 allm1 metal1 35
5153 defaultsideoverlap allm3 metal3 allm1 metal1 55
5154 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5155
5156#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5157 defaultoverlap allm3 metal3 allm2 metal2 86
5158 defaultsideoverlap allm3 metal3 allm2 metal2 70
5159 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5160
5161#ifdef METAL5
5162#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5163 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5164# defaultareacap alltopm metal4 well 6
5165 areacap allm4/m4 8
5166 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5167 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5168
5169#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5170 defaultoverlap allm4 metal4 allactivenonfet active 8
5171 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5172
5173#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5174 defaultoverlap allm4 metal4 allpolynonres active 10
5175 defaultsideoverlap allm4 metal4 allpolynonres active 38
5176 defaultsideoverlap *poly active allm4 metal4 6
5177
5178#metal4->locali
5179 defaultoverlap allm4 metal4 allli locali 12
5180 defaultsideoverlap allm4 metal4 allli locali 40
5181 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5182
5183#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5184 defaultoverlap allm4 metal4 allm1 metal1 15
5185 defaultsideoverlap allm4 metal4 allm1 metal1 43
5186 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5187
5188#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5189 defaultoverlap allm4 metal4 allm2 metal2 20
5190 defaultsideoverlap allm4 metal4 allm2 metal2 46
5191 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5192
5193#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5194 defaultoverlap allm4 metal4 allm3 metal3 84
5195 defaultsideoverlap allm4 metal4 allm3 metal3 71
5196 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5197
5198#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5199 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5200# defaultareacap allm5 metal5 well 6
5201 areacap allm5/m5 6
5202 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5203 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5204
5205#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5206 defaultoverlap allm5 metal5 allactivenonfet active 6
5207 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5208
5209#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5210 defaultoverlap allm5 metal5 allpolynonres active 7
5211 defaultsideoverlap allm5 metal5 allpolynonres active 40
5212 defaultsideoverlap *poly active allm5 metal5 6
5213
5214#metal5->locali
5215 defaultoverlap allm5 metal5 allli locali 8
5216 defaultsideoverlap allm5 metal5 allli locali 41
5217 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5218
5219#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5220 defaultoverlap allm5 metal5 allm1 metal1 9
5221 defaultsideoverlap allm5 metal5 allm1 metal1 43
5222 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5223
5224#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5225 defaultoverlap allm5 metal5 allm2 metal2 11
5226 defaultsideoverlap allm5 metal5 allm2 metal2 46
5227 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5228
5229#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5230 defaultoverlap allm5 metal5 allm3 metal3 20
5231 defaultsideoverlap allm5 metal5 allm3 metal3 54
5232 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5233
5234#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]5235 defaultoverlap allm5 metal5 allm4 metal4 68
5236 defaultsideoverlap allm5 metal5 allm4 metal4 83
5237 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5238#endif (METAL5)
5239
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]5240#ifdef REDISTRIBUTION
5241#endif (REDISTRIBUTION)
5242
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5243# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5244
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5245variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5246
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5247 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5248 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5249 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5250 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5251 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5252 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5253 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5254 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5255 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5256 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5257 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5258 a1=as p1=ps a2=ad p2=pd
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5259 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5260 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
5261 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5262
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5263 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5264 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5265 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5266 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5267 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5268 a1=as p1=ps a2=ad p2=pd
Tim Edwardse895c2a2021-02-26 16:05:31 -0500[diff] [blame]5269 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
5270 *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
5271 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5272 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5273 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5274 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5275 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5276 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5277 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5278 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5279 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
5280 a1=as p1=ps a2=ad p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5281 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5282 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5283 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5284 *nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5285 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5286 *mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5287
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5288 # Bipolars
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5289 device msubcircuit sky130_fd_pr__npn_05v0 npn *ndiff dnwell space/w error a2=area
5290 device msubcircuit sky130_fd_pr__pnp_05v0 pnp *pdiff pwell,space/w a2=area
5291 device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5292
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5293 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5294 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5295 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5296 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5297
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5298 # Extended drain devices (must appear before the regular devices)
5299 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5300 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5301 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5302 dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5303 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5304 pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5305
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5306 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5307 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5308 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5309 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5310 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5311 a1=as p1=ps a2=ad p2=pd
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5312 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5313 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5314 a1=as p1=ps a2=ad p2=pd
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5315 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
5316 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5317 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5318 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5319 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
5320 a1=as p1=ps a2=ad p2=pd
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5321 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
Tim Edwardsa7915ea2021-01-06 16:57:58 -0500[diff] [blame]5322 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
5323 a1=as p1=ps a2=ad p2=pd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5324
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5325 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5326 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5327 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5328 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5329#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5330 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5331 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5332#endif (METAL5)
5333
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5334 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5335 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5336 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5337 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5338 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5339 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5340 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5341 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5342 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5343 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5344 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5345 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5346 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5347 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5348 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5349 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5350 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5351 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5352 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5353 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5354 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5355 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5356 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5357 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5358
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5359 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5360 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5361 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5362 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5363 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5364 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5365 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5366 *mvndiff pwell,space/w error l=l w=w
5367 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5368 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5369
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5370 device resistor sky130_fd_pr__res_generic_po rmp *poly
5371 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5372
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5373 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5374 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5375 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
5376 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5377 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5378 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5379 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5380 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5381
5382 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
5383 pwell,space/w a=area
5384 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
5385 pwell,space/w a=area
5386 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
5387 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5388 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5389 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5390
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5391
5392#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5393 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5394 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5395#endif (MIM)
5396
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5397 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5398
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5399 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5400 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5401 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5402 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5403 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5404 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5405 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5406 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5407 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5408 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5409 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5410 pwell,space/w
5411
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5412 # Note that corenvar, corepvar are not considered devices, and extract as
5413 # parasitic capacitance instead (but cap values need to be added).
5414
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5415 # Extended drain devices (must appear before the regular devices)
5416 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5417 dnwell pwell,space/w error
5418 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5419 dnwell pwell,space/w error
5420 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5421 pwell,space/w nwell error
5422
5423 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5424 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5425 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5426 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5427 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwardsee445932021-03-31 12:32:04 -0400[diff] [blame]5428 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5429
5430 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5431 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5432 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5433 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5434
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5435 device resistor sky130_fd_pr__res_generic_po rmp *poly
5436 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5437 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5438 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5439 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5440#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5441 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5442 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5443#endif (METAL5)
5444
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5445 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5446 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5447 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5448 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5449 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5450 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5451 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5452 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5453 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5454 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5455 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5456 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5457 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5458 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5459 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5460 device resistor mrdn_hv mvndiffres *mvndiff
5461 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5462 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5463
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5464 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5465 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5466 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5467 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5468
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5469 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5470 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5471 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5472 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5473
Tim Edwards9642ef82021-04-27 22:12:52 -0400[diff] [blame]5474 device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a2=area
5475 device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a2=area
5476 device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5477
5478#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5479 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5480 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5481#endif (MIM)
5482
5483end
5484
5485#-----------------------------------------------------
5486# Wiring tool definitions
5487#-----------------------------------------------------
5488
5489wiring
5490 # All wiring values are in nanometers
5491 scalefactor 10
5492
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5493 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5494 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5495 contact v2 280 m2 0 45 m3 25 0
5496#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5497 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5498 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5499#endif (METAL5)
5500
5501 contact pc 170 poly 50 80 li 0 80
5502 contact pdc 170 pdiff 40 60 li 0 80
5503 contact ndc 170 ndiff 40 60 li 0 80
5504 contact psc 170 psd 40 60 li 0 80
5505 contact nsc 170 nsd 40 60 li 0 80
5506
5507end
5508
5509#-----------------------------------------------------
5510# Plain old router. . .
5511#-----------------------------------------------------
5512
5513router
5514end
5515
5516#------------------------------------------------------------
5517# Plowing (restored in magic 8.2, need to fill this section)
5518#------------------------------------------------------------
5519
5520plowing
5521end
5522
5523#-----------------------------------------------------------------
5524# No special plot layers defined (use default PNM color choices)
5525#-----------------------------------------------------------------
5526
5527plot
5528 style pnm
5529 default
5530 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5531 draw fillblock4 no_color_at_all
5532 draw fomfill no_color_at_all
5533 draw polyfill no_color_at_all
5534 draw m1fill no_color_at_all
5535 draw m2fill no_color_at_all
5536 draw m3fill no_color_at_all
5537 draw m4fill no_color_at_all
5538 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5539 draw nwell cwell
5540end
5541