commit	5330c799b8c72a8a2ee053fcf0200ff8cb517071	[log] [tgz]
author	Ali Imran <ali1120001@outlook.com>	Mon Aug 22 15:05:34 2022 +0500
committer	Ali Imran <ali1120001@outlook.com>	Mon Aug 22 15:05:34 2022 +0500
tree	f2bb8dc94b778e2a8799c3d26c47273fa341e7b2
parent	699c8bfee4668d8ef603e29822cd014138ace14c [diff]

Core hardened

caravel[Added - diff]
def/warpv_core.def[Added - diff]
gds/warpv_core.gds[Added - diff]
grep[Added - diff]
lef/warpv_core.lef[Added - diff]
mag/warpv_core.mag[Added - diff]
maglef/warpv_core.mag[Added - diff]
mgmt_core_wrapper[Added - diff]
openlane/warpv_core/config.tcl[Added - diff]
openlane/warpv_core/pin_order.cfg[Added - diff]
sdc/warpv_core.sdc[Added - diff]
sdf/warpv_core.sdf[Added - diff]
signoff/warpv_core/OPENLANE_VERSION[Added - diff]
signoff/warpv_core/PDK_SOURCES[Added - diff]
signoff/warpv_core/metrics.csv[Added - diff]
simlog.txt[Added - diff]
spef/warpv_core.spef[Added - diff]
spi/lvs/warpv_core.spice[Added - diff]
verilog/dv/wb_port/clk_gate.v[Added - diff]
verilog/dv/wb_port/sandpiper.vh[Added - diff]
verilog/dv/wb_port/sandpiper_gen.vh[Added - diff]
verilog/dv/wb_port/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/dv/wb_port/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
verilog/dv/wb_port/sp_verilog.vh[Added - diff]
verilog/dv/wb_port/warpv_core_gen.v[Added - diff]
verilog/dv/wb_port/wb_interface_gen.v[Added - diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/gl/warpv_core.v[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/a.out[Added - diff]
verilog/rtl/clk_gate.v[Added - diff]
verilog/rtl/includes/proj_default/clk_gate.sv[Added - diff]
verilog/rtl/includes/proj_default/sp_default.vh[Added - diff]
verilog/rtl/includes/proj_verilog/clk_gate.v[Added - diff]
verilog/rtl/includes/proj_verilog/sp_verilog.vh[Added - diff]
verilog/rtl/includes/pseudo_rand.tlv[Added - diff]
verilog/rtl/includes/rw_lib.vh[Added - diff]
verilog/rtl/includes/sandhost/README.txt[Added - diff]
verilog/rtl/includes/sandhost/sqrt32.v[Added - diff]
verilog/rtl/includes/sandhost/tb.sv[Added - diff]
verilog/rtl/includes/sandpiper.vh[Added - diff]
verilog/rtl/includes/sandpiper_gen.vh[Added - diff]
verilog/rtl/includes/simple_bypass_fifo.sv[Added - diff]
verilog/rtl/sandpiper.vh[Added - diff]
verilog/rtl/sandpiper_gen.vh[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v[diff]
verilog/rtl/sp_verilog.vh[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/warpv_core.v[Added - diff]
verilog/rtl/warpv_core_gen.v[Added - diff]
verilog/rtl/wb_interface.v[Added - diff]
verilog/rtl/wb_interface_gen.v[Added - diff]
verilog/tlv/warpv_core.tlv[Renamed from verilog/tlv/warpv.tlv - diff]
verilog/tlv/wb_interface.tlv[Added - diff]
verilog/tlv/wb_interface.tlv.bak[Added - diff]

56 files changed

tree: f2bb8dc94b778e2a8799c3d26c47273fa341e7b2

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.