| // Generated by SandPiper(TM) 1.12-2022/01/27-beta from Redwood EDA, LLC. |
| // Redwood EDA, LLC does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. |
| |
| |
| `include "sandpiper_gen.vh" |
| |
| |
| genvar instr_mem, pipe_ctrl_instr, pipe_ctrl_stage, regs, src; |
| |
| |
| // |
| // Signals declared top-level. |
| // |
| |
| // For |fetch/instr$BranchState. |
| wire [1:0] FETCH_Instr_BranchState_a1; |
| reg [1:0] FETCH_Instr_BranchState_a2; |
| reg [1:1] FETCH_Instr_BranchState_a3; |
| |
| // For |fetch/instr$Cnt. |
| wire [7:0] FETCH_Instr_Cnt_n2; |
| reg [7:0] FETCH_Instr_Cnt_n1; |
| |
| // For |fetch/instr$GoodPathMask. |
| wire [3+1:0] FETCH_Instr_GoodPathMask_n1; |
| reg [3+1:0] FETCH_Instr_GoodPathMask_a0, |
| FETCH_Instr_GoodPathMask_a1, |
| FETCH_Instr_GoodPathMask_a2, |
| FETCH_Instr_GoodPathMask_a3; |
| |
| // For |fetch/instr$NoFetch. |
| wire FETCH_Instr_NoFetch_n1; |
| reg FETCH_Instr_NoFetch_a0, |
| FETCH_Instr_NoFetch_a1, |
| FETCH_Instr_NoFetch_a2, |
| FETCH_Instr_NoFetch_a3; |
| |
| // For |fetch/instr$Pc. |
| wire [31:2] FETCH_Instr_Pc_n1; |
| reg [31:2] FETCH_Instr_Pc_a0, |
| FETCH_Instr_Pc_a1, |
| FETCH_Instr_Pc_a2, |
| FETCH_Instr_Pc_a3; |
| |
| // For |fetch/instr$RemainingCyclesWithinTimeUnit. |
| wire [30-1:0] FETCH_Instr_RemainingCyclesWithinTimeUnit_a1; |
| reg [30-1:0] FETCH_Instr_RemainingCyclesWithinTimeUnit_a2; |
| |
| // For |fetch/instr$abort. |
| wire FETCH_Instr_abort_a2; |
| |
| // For |fetch/instr$aborting_isa_trap. |
| wire FETCH_Instr_aborting_isa_trap_a2; |
| |
| // For |fetch/instr$aborting_trap. |
| wire FETCH_Instr_aborting_trap_a2; |
| reg FETCH_Instr_aborting_trap_a3; |
| |
| // For |fetch/instr$add_rslt. |
| wire [31:0] FETCH_Instr_add_rslt_a2; |
| |
| // For |fetch/instr$add_sub_rslt. |
| wire [31:0] FETCH_Instr_add_sub_rslt_a2; |
| |
| // For |fetch/instr$addi_rslt. |
| wire [31:0] FETCH_Instr_addi_rslt_a2; |
| |
| // For |fetch/instr$addr. |
| wire [31:0] FETCH_Instr_addr_a2; |
| reg [31:0] FETCH_Instr_addr_a3; |
| |
| // For |fetch/instr$and_rslt. |
| wire [31:0] FETCH_Instr_and_rslt_a2; |
| |
| // For |fetch/instr$andi_rslt. |
| wire [31:0] FETCH_Instr_andi_rslt_a2; |
| |
| // For |fetch/instr$auipc_rslt. |
| wire [31:0] FETCH_Instr_auipc_rslt_a2; |
| |
| // For |fetch/instr$branch. |
| wire FETCH_Instr_branch_a1; |
| reg FETCH_Instr_branch_a2; |
| |
| // For |fetch/instr$branch_or_reset. |
| wire FETCH_Instr_branch_or_reset_a2; |
| reg FETCH_Instr_branch_or_reset_a3; |
| |
| // For |fetch/instr$branch_redir_pc. |
| wire [31:2] FETCH_Instr_branch_redir_pc_a2; |
| |
| // For |fetch/instr$branch_target. |
| wire [31:2] FETCH_Instr_branch_target_a1; |
| reg [31:2] FETCH_Instr_branch_target_a2; |
| |
| // For |fetch/instr$bypass_avail1. |
| wire FETCH_Instr_bypass_avail1_a1; |
| reg FETCH_Instr_bypass_avail1_a2, |
| FETCH_Instr_bypass_avail1_a3; |
| |
| // For |fetch/instr$bypass_avail2. |
| wire FETCH_Instr_bypass_avail2_a1; |
| reg FETCH_Instr_bypass_avail2_a2, |
| FETCH_Instr_bypass_avail2_a3; |
| |
| // For |fetch/instr$commit. |
| wire FETCH_Instr_commit_a2; |
| reg FETCH_Instr_commit_a3; |
| |
| // For |fetch/instr$conditional_branch. |
| wire FETCH_Instr_conditional_branch_a1; |
| reg FETCH_Instr_conditional_branch_a2; |
| |
| // For |fetch/instr$csr_cycle. |
| wire [31:0] FETCH_Instr_csr_cycle_a1; |
| reg [31:0] FETCH_Instr_csr_cycle_a2, |
| FETCH_Instr_csr_cycle_a3; |
| |
| // For |fetch/instr$csr_cycle_hw_wr. |
| wire FETCH_Instr_csr_cycle_hw_wr_a2; |
| reg FETCH_Instr_csr_cycle_hw_wr_a3; |
| |
| // For |fetch/instr$csr_cycle_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_cycle_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_cycle_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_cycle_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_cycle_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_cycle_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_cycle_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_cycle_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_cycleh. |
| wire [31:0] FETCH_Instr_csr_cycleh_a1; |
| reg [31:0] FETCH_Instr_csr_cycleh_a2, |
| FETCH_Instr_csr_cycleh_a3; |
| |
| // For |fetch/instr$csr_cycleh_hw_wr. |
| wire FETCH_Instr_csr_cycleh_hw_wr_a2; |
| reg FETCH_Instr_csr_cycleh_hw_wr_a3; |
| |
| // For |fetch/instr$csr_cycleh_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_cycleh_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_cycleh_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_cycleh_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_cycleh_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_cycleh_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_cycleh_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_cycleh_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_instret. |
| wire [31:0] FETCH_Instr_csr_instret_a1; |
| reg [31:0] FETCH_Instr_csr_instret_a2, |
| FETCH_Instr_csr_instret_a3; |
| |
| // For |fetch/instr$csr_instret_hw_wr. |
| wire FETCH_Instr_csr_instret_hw_wr_a2; |
| reg FETCH_Instr_csr_instret_hw_wr_a3; |
| |
| // For |fetch/instr$csr_instret_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_instret_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_instret_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_instret_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_instret_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_instret_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_instret_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_instret_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_instreth. |
| wire [31:0] FETCH_Instr_csr_instreth_a1; |
| reg [31:0] FETCH_Instr_csr_instreth_a2, |
| FETCH_Instr_csr_instreth_a3; |
| |
| // For |fetch/instr$csr_instreth_hw_wr. |
| wire FETCH_Instr_csr_instreth_hw_wr_a2; |
| reg FETCH_Instr_csr_instreth_hw_wr_a3; |
| |
| // For |fetch/instr$csr_instreth_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_instreth_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_instreth_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_instreth_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_instreth_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_instreth_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_instreth_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_instreth_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_time. |
| wire [31:0] FETCH_Instr_csr_time_a1; |
| reg [31:0] FETCH_Instr_csr_time_a2, |
| FETCH_Instr_csr_time_a3; |
| |
| // For |fetch/instr$csr_time_hw_wr. |
| wire FETCH_Instr_csr_time_hw_wr_a2; |
| reg FETCH_Instr_csr_time_hw_wr_a3; |
| |
| // For |fetch/instr$csr_time_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_time_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_time_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_time_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_time_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_time_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_time_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_time_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_timeh. |
| wire [31:0] FETCH_Instr_csr_timeh_a1; |
| reg [31:0] FETCH_Instr_csr_timeh_a2, |
| FETCH_Instr_csr_timeh_a3; |
| |
| // For |fetch/instr$csr_timeh_hw_wr. |
| wire FETCH_Instr_csr_timeh_hw_wr_a2; |
| reg FETCH_Instr_csr_timeh_hw_wr_a3; |
| |
| // For |fetch/instr$csr_timeh_hw_wr_en_mask. |
| wire [31:0] FETCH_Instr_csr_timeh_hw_wr_en_mask_a2; |
| |
| // For |fetch/instr$csr_timeh_hw_wr_mask. |
| wire [31:0] FETCH_Instr_csr_timeh_hw_wr_mask_a2; |
| |
| // For |fetch/instr$csr_timeh_hw_wr_value. |
| wire [31:0] FETCH_Instr_csr_timeh_hw_wr_value_a2; |
| |
| // For |fetch/instr$csr_timeh_masked_wr_value. |
| wire [31:0] FETCH_Instr_csr_timeh_masked_wr_value_a2; |
| |
| // For |fetch/instr$csr_trap. |
| wire FETCH_Instr_csr_trap_a1; |
| reg FETCH_Instr_csr_trap_a2; |
| |
| // For |fetch/instr$csr_wr_value. |
| wire [31:0] FETCH_Instr_csr_wr_value_a2; |
| |
| // For |fetch/instr$csrrc_rslt. |
| wire [31:0] FETCH_Instr_csrrc_rslt_a2; |
| |
| // For |fetch/instr$csrrci_rslt. |
| wire [31:0] FETCH_Instr_csrrci_rslt_a2; |
| |
| // For |fetch/instr$csrrs_rslt. |
| wire [31:0] FETCH_Instr_csrrs_rslt_a2; |
| |
| // For |fetch/instr$csrrsi_rslt. |
| wire [31:0] FETCH_Instr_csrrsi_rslt_a2; |
| |
| // For |fetch/instr$csrrw_rslt. |
| wire [31:0] FETCH_Instr_csrrw_rslt_a2; |
| |
| // For |fetch/instr$csrrwi_rslt. |
| wire [31:0] FETCH_Instr_csrrwi_rslt_a2; |
| |
| // For |fetch/instr$dest_pending. |
| wire FETCH_Instr_dest_pending_a1; |
| |
| // For |fetch/instr$dest_reg. |
| wire [4:0] FETCH_Instr_dest_reg_a1; |
| reg [4:0] FETCH_Instr_dest_reg_a2, |
| FETCH_Instr_dest_reg_a3; |
| |
| // For |fetch/instr$dest_reg_valid. |
| wire FETCH_Instr_dest_reg_valid_a1; |
| reg FETCH_Instr_dest_reg_valid_a2, |
| FETCH_Instr_dest_reg_valid_a3; |
| |
| // For |fetch/instr$div_mul. |
| wire FETCH_Instr_div_mul_a1; |
| reg FETCH_Instr_div_mul_a2; |
| |
| // For |fetch/instr$equal. |
| wire FETCH_Instr_equal_a2; |
| |
| // For |fetch/instr$fetch. |
| wire FETCH_Instr_fetch_a0; |
| reg FETCH_Instr_fetch_a1; |
| |
| // For |fetch/instr$first_issue. |
| wire FETCH_Instr_first_issue_a3; |
| |
| // For |fetch/instr$full_csr_cycle_hw_wr_value. |
| wire [63:0] FETCH_Instr_full_csr_cycle_hw_wr_value_a2; |
| |
| // For |fetch/instr$full_csr_instret_hw_wr_value. |
| wire [63:0] FETCH_Instr_full_csr_instret_hw_wr_value_a2; |
| |
| // For |fetch/instr$full_csr_time_hw_wr_value. |
| wire [63:0] FETCH_Instr_full_csr_time_hw_wr_value_a2; |
| |
| // For |fetch/instr$good_path. |
| wire FETCH_Instr_good_path_a2; |
| |
| // For |fetch/instr$illegal. |
| wire FETCH_Instr_illegal_a1; |
| reg FETCH_Instr_illegal_a2; |
| |
| // For |fetch/instr$illegal_itype_with_funct7. |
| wire FETCH_Instr_illegal_itype_with_funct7_a1; |
| |
| // For |fetch/instr$imm_valid. |
| wire FETCH_Instr_imm_valid_a3; |
| |
| // For |fetch/instr$imm_value. |
| wire [31:0] FETCH_Instr_imm_value_a3; |
| |
| // For |fetch/instr$indirect_jump. |
| wire FETCH_Instr_indirect_jump_a1; |
| reg FETCH_Instr_indirect_jump_a2, |
| FETCH_Instr_indirect_jump_a3; |
| |
| // For |fetch/instr$indirect_jump_full_target. |
| wire [31:0] FETCH_Instr_indirect_jump_full_target_a2; |
| |
| // For |fetch/instr$indirect_jump_target. |
| wire [31:2] FETCH_Instr_indirect_jump_target_a2; |
| |
| // For |fetch/instr$is___type. |
| wire FETCH_Instr_is___type_a1; |
| |
| // For |fetch/instr$is_add_instr. |
| wire FETCH_Instr_is_add_instr_a1; |
| reg FETCH_Instr_is_add_instr_a2, |
| FETCH_Instr_is_add_instr_a3; |
| |
| // For |fetch/instr$is_addi_instr. |
| wire FETCH_Instr_is_addi_instr_a1; |
| reg FETCH_Instr_is_addi_instr_a2, |
| FETCH_Instr_is_addi_instr_a3; |
| |
| // For |fetch/instr$is_and_instr. |
| wire FETCH_Instr_is_and_instr_a1; |
| reg FETCH_Instr_is_and_instr_a2, |
| FETCH_Instr_is_and_instr_a3; |
| |
| // For |fetch/instr$is_andi_instr. |
| wire FETCH_Instr_is_andi_instr_a1; |
| reg FETCH_Instr_is_andi_instr_a2, |
| FETCH_Instr_is_andi_instr_a3; |
| |
| // For |fetch/instr$is_auipc_instr. |
| wire FETCH_Instr_is_auipc_instr_a1; |
| reg FETCH_Instr_is_auipc_instr_a2, |
| FETCH_Instr_is_auipc_instr_a3; |
| |
| // For |fetch/instr$is_b_type. |
| wire FETCH_Instr_is_b_type_a1; |
| reg FETCH_Instr_is_b_type_a2, |
| FETCH_Instr_is_b_type_a3; |
| |
| // For |fetch/instr$is_beq_instr. |
| wire FETCH_Instr_is_beq_instr_a1; |
| reg FETCH_Instr_is_beq_instr_a2, |
| FETCH_Instr_is_beq_instr_a3; |
| |
| // For |fetch/instr$is_bge_instr. |
| wire FETCH_Instr_is_bge_instr_a1; |
| reg FETCH_Instr_is_bge_instr_a2, |
| FETCH_Instr_is_bge_instr_a3; |
| |
| // For |fetch/instr$is_bgeu_instr. |
| wire FETCH_Instr_is_bgeu_instr_a1; |
| reg FETCH_Instr_is_bgeu_instr_a2, |
| FETCH_Instr_is_bgeu_instr_a3; |
| |
| // For |fetch/instr$is_blt_instr. |
| wire FETCH_Instr_is_blt_instr_a1; |
| reg FETCH_Instr_is_blt_instr_a2, |
| FETCH_Instr_is_blt_instr_a3; |
| |
| // For |fetch/instr$is_bltu_instr. |
| wire FETCH_Instr_is_bltu_instr_a1; |
| reg FETCH_Instr_is_bltu_instr_a2, |
| FETCH_Instr_is_bltu_instr_a3; |
| |
| // For |fetch/instr$is_bne_instr. |
| wire FETCH_Instr_is_bne_instr_a1; |
| reg FETCH_Instr_is_bne_instr_a2, |
| FETCH_Instr_is_bne_instr_a3; |
| |
| // For |fetch/instr$is_csr_clear. |
| wire FETCH_Instr_is_csr_clear_a1; |
| reg FETCH_Instr_is_csr_clear_a2; |
| |
| // For |fetch/instr$is_csr_cycle. |
| wire FETCH_Instr_is_csr_cycle_a1; |
| reg FETCH_Instr_is_csr_cycle_a2; |
| |
| // For |fetch/instr$is_csr_cycleh. |
| wire FETCH_Instr_is_csr_cycleh_a1; |
| reg FETCH_Instr_is_csr_cycleh_a2; |
| |
| // For |fetch/instr$is_csr_instr. |
| wire FETCH_Instr_is_csr_instr_a1; |
| |
| // For |fetch/instr$is_csr_instret. |
| wire FETCH_Instr_is_csr_instret_a1; |
| reg FETCH_Instr_is_csr_instret_a2; |
| |
| // For |fetch/instr$is_csr_instreth. |
| wire FETCH_Instr_is_csr_instreth_a1; |
| reg FETCH_Instr_is_csr_instreth_a2; |
| |
| // For |fetch/instr$is_csr_set. |
| wire FETCH_Instr_is_csr_set_a1; |
| reg FETCH_Instr_is_csr_set_a2; |
| |
| // For |fetch/instr$is_csr_time. |
| wire FETCH_Instr_is_csr_time_a1; |
| reg FETCH_Instr_is_csr_time_a2; |
| |
| // For |fetch/instr$is_csr_timeh. |
| wire FETCH_Instr_is_csr_timeh_a1; |
| reg FETCH_Instr_is_csr_timeh_a2; |
| |
| // For |fetch/instr$is_csr_write. |
| wire FETCH_Instr_is_csr_write_a1; |
| reg FETCH_Instr_is_csr_write_a2; |
| |
| // For |fetch/instr$is_csrrc_instr. |
| wire FETCH_Instr_is_csrrc_instr_a1; |
| reg FETCH_Instr_is_csrrc_instr_a2, |
| FETCH_Instr_is_csrrc_instr_a3; |
| |
| // For |fetch/instr$is_csrrci_instr. |
| wire FETCH_Instr_is_csrrci_instr_a1; |
| reg FETCH_Instr_is_csrrci_instr_a2, |
| FETCH_Instr_is_csrrci_instr_a3; |
| |
| // For |fetch/instr$is_csrrs_instr. |
| wire FETCH_Instr_is_csrrs_instr_a1; |
| reg FETCH_Instr_is_csrrs_instr_a2, |
| FETCH_Instr_is_csrrs_instr_a3; |
| |
| // For |fetch/instr$is_csrrsi_instr. |
| wire FETCH_Instr_is_csrrsi_instr_a1; |
| reg FETCH_Instr_is_csrrsi_instr_a2, |
| FETCH_Instr_is_csrrsi_instr_a3; |
| |
| // For |fetch/instr$is_csrrw_instr. |
| wire FETCH_Instr_is_csrrw_instr_a1; |
| reg FETCH_Instr_is_csrrw_instr_a2, |
| FETCH_Instr_is_csrrw_instr_a3; |
| |
| // For |fetch/instr$is_csrrwi_instr. |
| wire FETCH_Instr_is_csrrwi_instr_a1; |
| reg FETCH_Instr_is_csrrwi_instr_a2, |
| FETCH_Instr_is_csrrwi_instr_a3; |
| |
| // For |fetch/instr$is_dest_condition. |
| wire FETCH_Instr_is_dest_condition_a1; |
| |
| // For |fetch/instr$is_i_type. |
| wire FETCH_Instr_is_i_type_a1; |
| reg FETCH_Instr_is_i_type_a2, |
| FETCH_Instr_is_i_type_a3; |
| |
| // For |fetch/instr$is_j_type. |
| wire FETCH_Instr_is_j_type_a1; |
| reg FETCH_Instr_is_j_type_a2, |
| FETCH_Instr_is_j_type_a3; |
| |
| // For |fetch/instr$is_jal_instr. |
| wire FETCH_Instr_is_jal_instr_a1; |
| reg FETCH_Instr_is_jal_instr_a2, |
| FETCH_Instr_is_jal_instr_a3; |
| |
| // For |fetch/instr$is_jalr_instr. |
| wire FETCH_Instr_is_jalr_instr_a1; |
| reg FETCH_Instr_is_jalr_instr_a2, |
| FETCH_Instr_is_jalr_instr_a3; |
| |
| // For |fetch/instr$is_lb_instr. |
| wire FETCH_Instr_is_lb_instr_a1; |
| reg FETCH_Instr_is_lb_instr_a2, |
| FETCH_Instr_is_lb_instr_a3; |
| |
| // For |fetch/instr$is_lbu_instr. |
| wire FETCH_Instr_is_lbu_instr_a1; |
| reg FETCH_Instr_is_lbu_instr_a2, |
| FETCH_Instr_is_lbu_instr_a3; |
| |
| // For |fetch/instr$is_lh_instr. |
| wire FETCH_Instr_is_lh_instr_a1; |
| reg FETCH_Instr_is_lh_instr_a2, |
| FETCH_Instr_is_lh_instr_a3; |
| |
| // For |fetch/instr$is_lhu_instr. |
| wire FETCH_Instr_is_lhu_instr_a1; |
| reg FETCH_Instr_is_lhu_instr_a2, |
| FETCH_Instr_is_lhu_instr_a3; |
| |
| // For |fetch/instr$is_lui_instr. |
| wire FETCH_Instr_is_lui_instr_a1; |
| reg FETCH_Instr_is_lui_instr_a2, |
| FETCH_Instr_is_lui_instr_a3; |
| |
| // For |fetch/instr$is_lw_instr. |
| wire FETCH_Instr_is_lw_instr_a1; |
| reg FETCH_Instr_is_lw_instr_a2, |
| FETCH_Instr_is_lw_instr_a3; |
| |
| // For |fetch/instr$is_or_instr. |
| wire FETCH_Instr_is_or_instr_a1; |
| reg FETCH_Instr_is_or_instr_a2, |
| FETCH_Instr_is_or_instr_a3; |
| |
| // For |fetch/instr$is_ori_instr. |
| wire FETCH_Instr_is_ori_instr_a1; |
| reg FETCH_Instr_is_ori_instr_a2, |
| FETCH_Instr_is_ori_instr_a3; |
| |
| // For |fetch/instr$is_r2_type. |
| wire FETCH_Instr_is_r2_type_a1; |
| |
| // For |fetch/instr$is_r4_type. |
| wire FETCH_Instr_is_r4_type_a1; |
| |
| // For |fetch/instr$is_r_type. |
| wire FETCH_Instr_is_r_type_a1; |
| reg FETCH_Instr_is_r_type_a2, |
| FETCH_Instr_is_r_type_a3; |
| |
| // For |fetch/instr$is_s_type. |
| wire FETCH_Instr_is_s_type_a1; |
| reg FETCH_Instr_is_s_type_a2, |
| FETCH_Instr_is_s_type_a3; |
| |
| // For |fetch/instr$is_sb_instr. |
| wire FETCH_Instr_is_sb_instr_a1; |
| reg FETCH_Instr_is_sb_instr_a2, |
| FETCH_Instr_is_sb_instr_a3; |
| |
| // For |fetch/instr$is_sh_instr. |
| wire FETCH_Instr_is_sh_instr_a1; |
| reg FETCH_Instr_is_sh_instr_a2, |
| FETCH_Instr_is_sh_instr_a3; |
| |
| // For |fetch/instr$is_sll_instr. |
| wire FETCH_Instr_is_sll_instr_a1; |
| reg FETCH_Instr_is_sll_instr_a2, |
| FETCH_Instr_is_sll_instr_a3; |
| |
| // For |fetch/instr$is_slli_instr. |
| wire FETCH_Instr_is_slli_instr_a1; |
| reg FETCH_Instr_is_slli_instr_a2, |
| FETCH_Instr_is_slli_instr_a3; |
| |
| // For |fetch/instr$is_slt_instr. |
| wire FETCH_Instr_is_slt_instr_a1; |
| reg FETCH_Instr_is_slt_instr_a2, |
| FETCH_Instr_is_slt_instr_a3; |
| |
| // For |fetch/instr$is_slti_instr. |
| wire FETCH_Instr_is_slti_instr_a1; |
| reg FETCH_Instr_is_slti_instr_a2, |
| FETCH_Instr_is_slti_instr_a3; |
| |
| // For |fetch/instr$is_sltiu_instr. |
| wire FETCH_Instr_is_sltiu_instr_a1; |
| reg FETCH_Instr_is_sltiu_instr_a2, |
| FETCH_Instr_is_sltiu_instr_a3; |
| |
| // For |fetch/instr$is_sltu_instr. |
| wire FETCH_Instr_is_sltu_instr_a1; |
| reg FETCH_Instr_is_sltu_instr_a2, |
| FETCH_Instr_is_sltu_instr_a3; |
| |
| // For |fetch/instr$is_sra_instr. |
| wire FETCH_Instr_is_sra_instr_a1; |
| reg FETCH_Instr_is_sra_instr_a2, |
| FETCH_Instr_is_sra_instr_a3; |
| |
| // For |fetch/instr$is_srai_instr. |
| wire FETCH_Instr_is_srai_instr_a1; |
| reg FETCH_Instr_is_srai_instr_a2, |
| FETCH_Instr_is_srai_instr_a3; |
| |
| // For |fetch/instr$is_srl_instr. |
| wire FETCH_Instr_is_srl_instr_a1; |
| reg FETCH_Instr_is_srl_instr_a2, |
| FETCH_Instr_is_srl_instr_a3; |
| |
| // For |fetch/instr$is_srli_instr. |
| wire FETCH_Instr_is_srli_instr_a1; |
| reg FETCH_Instr_is_srli_instr_a2, |
| FETCH_Instr_is_srli_instr_a3; |
| |
| // For |fetch/instr$is_srli_srai_instr. |
| wire FETCH_Instr_is_srli_srai_instr_a1; |
| |
| // For |fetch/instr$is_sub_instr. |
| wire FETCH_Instr_is_sub_instr_a1; |
| reg FETCH_Instr_is_sub_instr_a2, |
| FETCH_Instr_is_sub_instr_a3; |
| |
| // For |fetch/instr$is_sw_instr. |
| wire FETCH_Instr_is_sw_instr_a1; |
| reg FETCH_Instr_is_sw_instr_a2, |
| FETCH_Instr_is_sw_instr_a3; |
| |
| // For |fetch/instr$is_u_type. |
| wire FETCH_Instr_is_u_type_a1; |
| reg FETCH_Instr_is_u_type_a2, |
| FETCH_Instr_is_u_type_a3; |
| |
| // For |fetch/instr$is_xor_instr. |
| wire FETCH_Instr_is_xor_instr_a1; |
| reg FETCH_Instr_is_xor_instr_a2, |
| FETCH_Instr_is_xor_instr_a3; |
| |
| // For |fetch/instr$is_xori_instr. |
| wire FETCH_Instr_is_xori_instr_a1; |
| reg FETCH_Instr_is_xori_instr_a2, |
| FETCH_Instr_is_xori_instr_a3; |
| |
| // For |fetch/instr$jal_rslt. |
| wire [31:0] FETCH_Instr_jal_rslt_a2; |
| |
| // For |fetch/instr$jalr_rslt. |
| wire [31:0] FETCH_Instr_jalr_rslt_a2; |
| |
| // For |fetch/instr$jump. |
| wire FETCH_Instr_jump_a1; |
| reg FETCH_Instr_jump_a2, |
| FETCH_Instr_jump_a3; |
| |
| // For |fetch/instr$jump_target. |
| wire [31:2] FETCH_Instr_jump_target_a1; |
| reg [31:2] FETCH_Instr_jump_target_a2; |
| |
| // For |fetch/instr$lb_rslt. |
| wire [31:0] FETCH_Instr_lb_rslt_a2; |
| |
| // For |fetch/instr$lbu_rslt. |
| wire [31:0] FETCH_Instr_lbu_rslt_a2; |
| |
| // For |fetch/instr$ld. |
| wire FETCH_Instr_ld_a1; |
| reg FETCH_Instr_ld_a2; |
| |
| // For |fetch/instr$ld_data. |
| wire [31:0] FETCH_Instr_ld_data_a4; |
| |
| // For |fetch/instr$ld_st. |
| wire FETCH_Instr_ld_st_a1; |
| reg FETCH_Instr_ld_st_a2; |
| |
| // For |fetch/instr$ld_st_cond. |
| wire FETCH_Instr_ld_st_cond_a2; |
| |
| // For |fetch/instr$ld_st_half. |
| wire FETCH_Instr_ld_st_half_a1; |
| reg FETCH_Instr_ld_st_half_a2, |
| FETCH_Instr_ld_st_half_a3; |
| |
| // For |fetch/instr$ld_st_word. |
| wire FETCH_Instr_ld_st_word_a1; |
| reg FETCH_Instr_ld_st_word_a2, |
| FETCH_Instr_ld_st_word_a3; |
| |
| // For |fetch/instr$lh_rslt. |
| wire [31:0] FETCH_Instr_lh_rslt_a2; |
| |
| // For |fetch/instr$lhu_rslt. |
| wire [31:0] FETCH_Instr_lhu_rslt_a2; |
| |
| // For |fetch/instr$lui_rslt. |
| wire [31:0] FETCH_Instr_lui_rslt_a2; |
| |
| // For |fetch/instr$lw_rslt. |
| wire [31:0] FETCH_Instr_lw_rslt_a2; |
| |
| // For |fetch/instr$misaligned_indirect_jump_target. |
| wire FETCH_Instr_misaligned_indirect_jump_target_a2; |
| |
| // For |fetch/instr$misaligned_jump_target. |
| wire FETCH_Instr_misaligned_jump_target_a1; |
| reg FETCH_Instr_misaligned_jump_target_a2; |
| |
| // For |fetch/instr$misaligned_pc. |
| wire FETCH_Instr_misaligned_pc_a1; |
| reg FETCH_Instr_misaligned_pc_a2; |
| |
| // For |fetch/instr$mispred_branch. |
| wire FETCH_Instr_mispred_branch_a2; |
| reg FETCH_Instr_mispred_branch_a3; |
| |
| // For |fetch/instr$mnemonic. |
| wire [10*8-1:0] FETCH_Instr_mnemonic_a3; |
| |
| // For |fetch/instr$multype_instr. |
| wire FETCH_Instr_multype_instr_a1; |
| |
| // For |fetch/instr$next_good_path_mask. |
| wire [3+1:0] FETCH_Instr_next_good_path_mask_a0; |
| |
| // For |fetch/instr$next_no_fetch. |
| wire FETCH_Instr_next_no_fetch_a0; |
| |
| // For |fetch/instr$next_pc. |
| wire [31:2] FETCH_Instr_next_pc_a0; |
| |
| // For |fetch/instr$non_aborting_isa_trap. |
| wire FETCH_Instr_non_aborting_isa_trap_a2; |
| |
| // For |fetch/instr$non_aborting_trap. |
| wire FETCH_Instr_non_aborting_trap_a2; |
| reg FETCH_Instr_non_aborting_trap_a3; |
| |
| // For |fetch/instr$non_pipelined. |
| wire FETCH_Instr_non_pipelined_a2; |
| reg FETCH_Instr_non_pipelined_a3; |
| |
| // For |fetch/instr$or_rslt. |
| wire [31:0] FETCH_Instr_or_rslt_a2; |
| |
| // For |fetch/instr$ori_rslt. |
| wire [31:0] FETCH_Instr_ori_rslt_a2; |
| |
| // For |fetch/instr$pc. |
| wire [31:2] FETCH_Instr_pc_a2; |
| reg [31:2] FETCH_Instr_pc_a3; |
| |
| // For |fetch/instr$pc_inc. |
| wire [31:2] FETCH_Instr_pc_inc_a0; |
| reg [31:2] FETCH_Instr_pc_inc_a1, |
| FETCH_Instr_pc_inc_a2, |
| FETCH_Instr_pc_inc_a3; |
| |
| // For |fetch/instr$pending_replay. |
| wire FETCH_Instr_pending_replay_a1; |
| |
| // For |fetch/instr$pred_taken. |
| wire FETCH_Instr_pred_taken_a1; |
| reg FETCH_Instr_pred_taken_a2; |
| |
| // For |fetch/instr$pred_taken_branch. |
| wire FETCH_Instr_pred_taken_branch_a1; |
| reg FETCH_Instr_pred_taken_branch_a2, |
| FETCH_Instr_pred_taken_branch_a3; |
| |
| // For |fetch/instr$raw. |
| wire [31:0] FETCH_Instr_raw_a1; |
| |
| // For |fetch/instr$raw_aq. |
| wire FETCH_Instr_raw_aq_a1; |
| |
| // For |fetch/instr$raw_b_imm. |
| wire [31:0] FETCH_Instr_raw_b_imm_a1; |
| reg [31:0] FETCH_Instr_raw_b_imm_a2, |
| FETCH_Instr_raw_b_imm_a3; |
| |
| // For |fetch/instr$raw_funct3. |
| wire [2:0] FETCH_Instr_raw_funct3_a1; |
| reg [2:2] FETCH_Instr_raw_funct3_a2, |
| FETCH_Instr_raw_funct3_a3; |
| |
| // For |fetch/instr$raw_funct7. |
| wire [6:0] FETCH_Instr_raw_funct7_a1; |
| reg [6:0] FETCH_Instr_raw_funct7_a2, |
| FETCH_Instr_raw_funct7_a3; |
| |
| // For |fetch/instr$raw_i_imm. |
| wire [31:0] FETCH_Instr_raw_i_imm_a1; |
| reg [31:0] FETCH_Instr_raw_i_imm_a2, |
| FETCH_Instr_raw_i_imm_a3; |
| |
| // For |fetch/instr$raw_j_imm. |
| wire [31:0] FETCH_Instr_raw_j_imm_a1; |
| reg [31:0] FETCH_Instr_raw_j_imm_a2, |
| FETCH_Instr_raw_j_imm_a3; |
| |
| // For |fetch/instr$raw_op2. |
| wire [1:0] FETCH_Instr_raw_op2_a1; |
| |
| // For |fetch/instr$raw_op5. |
| wire [4:0] FETCH_Instr_raw_op5_a1; |
| |
| // For |fetch/instr$raw_rd. |
| wire [4:0] FETCH_Instr_raw_rd_a1; |
| reg [4:0] FETCH_Instr_raw_rd_a2, |
| FETCH_Instr_raw_rd_a3; |
| |
| // For |fetch/instr$raw_rl. |
| wire FETCH_Instr_raw_rl_a1; |
| |
| // For |fetch/instr$raw_rm. |
| wire [2:0] FETCH_Instr_raw_rm_a1; |
| |
| // For |fetch/instr$raw_rs1. |
| wire [4:0] FETCH_Instr_raw_rs1_a1; |
| reg [4:0] FETCH_Instr_raw_rs1_a2, |
| FETCH_Instr_raw_rs1_a3; |
| |
| // For |fetch/instr$raw_rs2. |
| wire [4:0] FETCH_Instr_raw_rs2_a1; |
| reg [4:0] FETCH_Instr_raw_rs2_a2, |
| FETCH_Instr_raw_rs2_a3; |
| |
| // For |fetch/instr$raw_rs3. |
| wire [4:0] FETCH_Instr_raw_rs3_a1; |
| reg [4:0] FETCH_Instr_raw_rs3_a2, |
| FETCH_Instr_raw_rs3_a3; |
| |
| // For |fetch/instr$raw_s_imm. |
| wire [31:0] FETCH_Instr_raw_s_imm_a1; |
| reg [31:0] FETCH_Instr_raw_s_imm_a2, |
| FETCH_Instr_raw_s_imm_a3; |
| |
| // For |fetch/instr$raw_shamt. |
| wire [6:0] FETCH_Instr_raw_shamt_a1; |
| |
| // For |fetch/instr$raw_u_imm. |
| wire [31:0] FETCH_Instr_raw_u_imm_a1; |
| reg [31:0] FETCH_Instr_raw_u_imm_a2, |
| FETCH_Instr_raw_u_imm_a3; |
| |
| // For |fetch/instr$reg_wr_pending. |
| wire FETCH_Instr_reg_wr_pending_a1; |
| reg FETCH_Instr_reg_wr_pending_a2, |
| FETCH_Instr_reg_wr_pending_a3; |
| |
| // For |fetch/instr$replay. |
| wire FETCH_Instr_replay_a1; |
| reg FETCH_Instr_replay_a2, |
| FETCH_Instr_replay_a3; |
| |
| // For |fetch/instr$replay_trap. |
| wire FETCH_Instr_replay_trap_a2; |
| |
| // For |fetch/instr$reset. |
| wire FETCH_Instr_reset_n1; |
| reg FETCH_Instr_reset_a0, |
| FETCH_Instr_reset_a1, |
| FETCH_Instr_reset_a2, |
| FETCH_Instr_reset_a3; |
| |
| // For |fetch/instr$rslt. |
| wire [31:0] FETCH_Instr_rslt_a2; |
| reg [31:0] FETCH_Instr_rslt_a3; |
| |
| // For |fetch/instr$second_issue. |
| wire FETCH_Instr_second_issue_a0; |
| reg FETCH_Instr_second_issue_a1, |
| FETCH_Instr_second_issue_a2, |
| FETCH_Instr_second_issue_a3; |
| |
| // For |fetch/instr$second_issue_ld. |
| wire FETCH_Instr_second_issue_ld_a0; |
| reg FETCH_Instr_second_issue_ld_a1, |
| FETCH_Instr_second_issue_ld_a2; |
| |
| // For |fetch/instr$sll_rslt. |
| wire [31:0] FETCH_Instr_sll_rslt_a2; |
| |
| // For |fetch/instr$slli_rslt. |
| wire [31:0] FETCH_Instr_slli_rslt_a2; |
| |
| // For |fetch/instr$slt_rslt. |
| wire [31:0] FETCH_Instr_slt_rslt_a2; |
| |
| // For |fetch/instr$slti_rslt. |
| wire [31:0] FETCH_Instr_slti_rslt_a2; |
| |
| // For |fetch/instr$sltiu_rslt. |
| wire [31:0] FETCH_Instr_sltiu_rslt_a2; |
| |
| // For |fetch/instr$sltu_rslt. |
| wire [31:0] FETCH_Instr_sltu_rslt_a2; |
| |
| // For |fetch/instr$soft_reset. |
| wire FETCH_Instr_soft_reset_n1; |
| |
| // For |fetch/instr$spec_ld. |
| wire FETCH_Instr_spec_ld_a1; |
| reg FETCH_Instr_spec_ld_a2, |
| FETCH_Instr_spec_ld_a3; |
| |
| // For |fetch/instr$sra_rslt. |
| wire [31:0] FETCH_Instr_sra_rslt_a2; |
| |
| // For |fetch/instr$srai_intermediate_rslt. |
| wire [31:0] FETCH_Instr_srai_intermediate_rslt_a2; |
| |
| // For |fetch/instr$srai_rslt. |
| wire [31:0] FETCH_Instr_srai_rslt_a2; |
| |
| // For |fetch/instr$srl_rslt. |
| wire [31:0] FETCH_Instr_srl_rslt_a2; |
| |
| // For |fetch/instr$srli_intermediate_rslt. |
| wire [31:0] FETCH_Instr_srli_intermediate_rslt_a2; |
| |
| // For |fetch/instr$srli_rslt. |
| wire [31:0] FETCH_Instr_srli_rslt_a2; |
| |
| // For |fetch/instr$st. |
| wire FETCH_Instr_st_a1; |
| reg FETCH_Instr_st_a2, |
| FETCH_Instr_st_a3; |
| |
| // For |fetch/instr$st_cond. |
| wire FETCH_Instr_st_cond_a2; |
| |
| // For |fetch/instr$st_mask. |
| wire [3:0] FETCH_Instr_st_mask_a2; |
| reg [3:0] FETCH_Instr_st_mask_a3; |
| |
| // For |fetch/instr$st_reg_value. |
| wire [31:0] FETCH_Instr_st_reg_value_a2; |
| |
| // For |fetch/instr$st_value. |
| wire [31:0] FETCH_Instr_st_value_a2; |
| reg [31:0] FETCH_Instr_st_value_a3; |
| |
| // For |fetch/instr$sub_rslt. |
| wire [31:0] FETCH_Instr_sub_rslt_a2; |
| |
| // For |fetch/instr$taken. |
| wire FETCH_Instr_taken_a2; |
| |
| // For |fetch/instr$time_unit_expires. |
| wire FETCH_Instr_time_unit_expires_a2; |
| |
| // For |fetch/instr$trap_target. |
| wire [31:2] FETCH_Instr_trap_target_a2; |
| reg [31:2] FETCH_Instr_trap_target_a3; |
| |
| // For |fetch/instr$unnatural_addr_trap. |
| wire FETCH_Instr_unnatural_addr_trap_a2; |
| |
| // For |fetch/instr$upd_csr_cycle. |
| wire [31:0] FETCH_Instr_upd_csr_cycle_a2; |
| |
| // For |fetch/instr$upd_csr_cycleh. |
| wire [31:0] FETCH_Instr_upd_csr_cycleh_a2; |
| |
| // For |fetch/instr$upd_csr_instret. |
| wire [31:0] FETCH_Instr_upd_csr_instret_a2; |
| |
| // For |fetch/instr$upd_csr_instreth. |
| wire [31:0] FETCH_Instr_upd_csr_instreth_a2; |
| |
| // For |fetch/instr$upd_csr_time. |
| wire [31:0] FETCH_Instr_upd_csr_time_a2; |
| |
| // For |fetch/instr$upd_csr_timeh. |
| wire [31:0] FETCH_Instr_upd_csr_timeh_a2; |
| |
| // For |fetch/instr$valid_csr. |
| wire FETCH_Instr_valid_csr_a1; |
| |
| // For |fetch/instr$valid_decode. |
| wire FETCH_Instr_valid_decode_a1; |
| reg FETCH_Instr_valid_decode_a2, |
| FETCH_Instr_valid_decode_a3; |
| |
| // For |fetch/instr$valid_decode_branch. |
| wire FETCH_Instr_valid_decode_branch_a1; |
| reg FETCH_Instr_valid_decode_branch_a2; |
| |
| // For |fetch/instr$valid_dest_reg_valid. |
| wire FETCH_Instr_valid_dest_reg_valid_a2; |
| reg FETCH_Instr_valid_dest_reg_valid_a3; |
| |
| // For |fetch/instr$valid_exe. |
| wire FETCH_Instr_valid_exe_a2; |
| |
| // For |fetch/instr$valid_ld. |
| wire FETCH_Instr_valid_ld_a2; |
| reg FETCH_Instr_valid_ld_a3; |
| |
| // For |fetch/instr$valid_st. |
| wire FETCH_Instr_valid_st_a2; |
| reg FETCH_Instr_valid_st_a3; |
| |
| // For |fetch/instr$xor_rslt. |
| wire [31:0] FETCH_Instr_xor_rslt_a2; |
| |
| // For |fetch/instr$xori_rslt. |
| wire [31:0] FETCH_Instr_xori_rslt_a2; |
| |
| // For |fetch/instr/orig_inst$dest_reg. |
| wire [4:0] FETCH_Instr_OrigInst_dest_reg_a0; |
| reg [4:0] FETCH_Instr_OrigInst_dest_reg_a1; |
| |
| // For |fetch/instr/orig_inst$pc. |
| wire [31:2] FETCH_Instr_OrigInst_pc_a0; |
| reg [31:2] FETCH_Instr_OrigInst_pc_a1, |
| FETCH_Instr_OrigInst_pc_a2, |
| FETCH_Instr_OrigInst_pc_a3; |
| |
| // For |fetch/instr/orig_load_inst$addr. |
| wire [1:0] FETCH_Instr_OrigLoadInst_addr_a0; |
| reg [1:0] FETCH_Instr_OrigLoadInst_addr_a1, |
| FETCH_Instr_OrigLoadInst_addr_a2; |
| |
| // For |fetch/instr/orig_load_inst$dest_reg. |
| wire [4:0] FETCH_Instr_OrigLoadInst_dest_reg_a0; |
| |
| // For |fetch/instr/orig_load_inst$g0_spec_ld_cond. |
| wire FETCH_Instr_OrigLoadInst_g0_spec_ld_cond_a2; |
| |
| // For |fetch/instr/orig_load_inst$ld_mask. |
| wire [3:0] FETCH_Instr_OrigLoadInst_ld_mask_a2; |
| |
| // For |fetch/instr/orig_load_inst$ld_rslt. |
| wire [31:0] FETCH_Instr_OrigLoadInst_ld_rslt_a2; |
| |
| // For |fetch/instr/orig_load_inst$ld_st_half. |
| wire FETCH_Instr_OrigLoadInst_ld_st_half_a0; |
| reg FETCH_Instr_OrigLoadInst_ld_st_half_a1, |
| FETCH_Instr_OrigLoadInst_ld_st_half_a2; |
| |
| // For |fetch/instr/orig_load_inst$ld_st_word. |
| wire FETCH_Instr_OrigLoadInst_ld_st_word_a0; |
| reg FETCH_Instr_OrigLoadInst_ld_st_word_a1, |
| FETCH_Instr_OrigLoadInst_ld_st_word_a2; |
| |
| // For |fetch/instr/orig_load_inst$ld_value. |
| wire [31:0] FETCH_Instr_OrigLoadInst_ld_value_a0; |
| reg [31:0] FETCH_Instr_OrigLoadInst_ld_value_a1, |
| FETCH_Instr_OrigLoadInst_ld_value_a2; |
| |
| // For |fetch/instr/orig_load_inst$pc. |
| wire [31:2] FETCH_Instr_OrigLoadInst_pc_a0; |
| |
| // For |fetch/instr/orig_load_inst$raw_funct3. |
| wire [2:2] FETCH_Instr_OrigLoadInst_raw_funct3_a0; |
| reg [2:2] FETCH_Instr_OrigLoadInst_raw_funct3_a1, |
| FETCH_Instr_OrigLoadInst_raw_funct3_a2; |
| |
| // For |fetch/instr/orig_load_inst$sign_bit. |
| wire FETCH_Instr_OrigLoadInst_sign_bit_a2; |
| |
| // For |fetch/instr/orig_load_inst$spec_ld. |
| wire FETCH_Instr_OrigLoadInst_spec_ld_a0; |
| reg FETCH_Instr_OrigLoadInst_spec_ld_a1, |
| FETCH_Instr_OrigLoadInst_spec_ld_a2; |
| |
| // For |fetch/instr/orig_load_inst$spec_ld_cond. |
| wire FETCH_Instr_OrigLoadInst_spec_ld_cond_a2; |
| |
| // For |fetch/instr/regs$pending. |
| wire FETCH_Instr_Regs_pending_a2 [31:1]; |
| reg FETCH_Instr_Regs_pending_a3 [31:1]; |
| |
| // For |fetch/instr/regs$value. |
| reg [31:0] FETCH_Instr_Regs_value_a3 [31:1]; |
| |
| // For |fetch/instr/src$replay. |
| wire [2:1] FETCH_Instr_Src_replay_a1; |
| |
| // For |fetch/instr/src$unconditioned_is_reg. |
| wire FETCH_Instr_Src_unconditioned_is_reg_a3 [2:1]; |
| |
| // For |fetch/instr/src$unconditioned_reg. |
| wire [4:0] FETCH_Instr_Src_unconditioned_reg_a3 [2:1]; |
| |
| // For |fetch/instr/src$unconditioned_reg_value. |
| wire [31:0] FETCH_Instr_Src_unconditioned_reg_value_a3 [2:1]; |
| |
| // For |mem/data$addr. |
| wire [1:0] MEM_Data_addr_a3; |
| reg [1:0] MEM_Data_addr_a4; |
| |
| // For |mem/data$dest_reg. |
| wire [4:0] MEM_Data_dest_reg_a3; |
| reg [4:0] MEM_Data_dest_reg_a4; |
| |
| // For |mem/data$ld_st_half. |
| wire MEM_Data_ld_st_half_a3; |
| reg MEM_Data_ld_st_half_a4; |
| |
| // For |mem/data$ld_st_word. |
| wire MEM_Data_ld_st_word_a3; |
| reg MEM_Data_ld_st_word_a4; |
| |
| // For |mem/data$ld_value. |
| wire [31:0] MEM_Data_ld_value_a4; |
| |
| // For |mem/data$pc. |
| wire [31:2] MEM_Data_pc_a3; |
| reg [31:2] MEM_Data_pc_a4; |
| |
| // For |mem/data$raw_funct3. |
| wire [2:2] MEM_Data_raw_funct3_a3; |
| reg [2:2] MEM_Data_raw_funct3_a4; |
| |
| // For |mem/data$spec_ld. |
| wire MEM_Data_spec_ld_a3; |
| reg MEM_Data_spec_ld_a4; |
| |
| // For |mem/data$valid_ld. |
| wire MEM_Data_valid_ld_a3; |
| reg MEM_Data_valid_ld_a4; |
| |
| |
| // |
| // Scope: |fetch |
| // |
| |
| // |
| // Scope: |fetch/instr |
| // |
| |
| // Clock signals. |
| wire clkF_FETCH_Instr_branch_or_reset_a3 ; |
| wire clkF_FETCH_Instr_branch_or_reset_a4 ; |
| wire clkP_FETCH_Instr_branch_a2 ; |
| wire clkP_FETCH_Instr_jump_a2 ; |
| wire clkP_FETCH_Instr_ld_st_cond_a3 ; |
| wire clkP_FETCH_Instr_second_issue_a1 ; |
| wire clkP_FETCH_Instr_second_issue_a2 ; |
| wire clkP_FETCH_Instr_second_issue_a3 ; |
| wire clkP_FETCH_Instr_second_issue_ld_a1 ; |
| wire clkP_FETCH_Instr_second_issue_ld_a2 ; |
| wire clkP_FETCH_Instr_st_cond_a3 ; |
| wire clkP_FETCH_Instr_valid_decode_a2 ; |
| wire clkP_FETCH_Instr_valid_decode_a3 ; |
| wire clkP_FETCH_Instr_valid_decode_branch_a2 ; |
| |
| // |
| // Scope: |fetch/instr/src[2:1] |
| // |
| |
| // Clock signals. |
| wire clkP_FETCH_Instr_Src_is_reg_condition_a2 [2:1]; |
| wire clkP_FETCH_Instr_Src_is_reg_condition_a3 [2:1]; |
| |
| |
| generate |
| |
| |
| // |
| // Scope: |fetch |
| // |
| |
| |
| // |
| // Scope: /instr |
| // |
| |
| // For $BranchState. |
| always @(posedge clkF_FETCH_Instr_branch_or_reset_a3) FETCH_Instr_BranchState_a2[1:0] <= FETCH_Instr_BranchState_a1[1:0]; |
| always @(posedge clkF_FETCH_Instr_branch_or_reset_a4) FETCH_Instr_BranchState_a3[1] <= FETCH_Instr_BranchState_a2[1]; |
| |
| // For $Cnt. |
| always @(posedge clk) FETCH_Instr_Cnt_n1[7:0] <= FETCH_Instr_Cnt_n2[7:0]; |
| |
| // For $GoodPathMask. |
| always @(posedge clk) FETCH_Instr_GoodPathMask_a0[3+1:0] <= FETCH_Instr_GoodPathMask_n1[3+1:0]; |
| always @(posedge clk) FETCH_Instr_GoodPathMask_a1[3+1:0] <= FETCH_Instr_GoodPathMask_a0[3+1:0]; |
| always @(posedge clk) FETCH_Instr_GoodPathMask_a2[3+1:0] <= FETCH_Instr_GoodPathMask_a1[3+1:0]; |
| always @(posedge clk) FETCH_Instr_GoodPathMask_a3[3+1:0] <= FETCH_Instr_GoodPathMask_a2[3+1:0]; |
| |
| // For $NoFetch. |
| always @(posedge clk) FETCH_Instr_NoFetch_a0 <= FETCH_Instr_NoFetch_n1; |
| always @(posedge clk) FETCH_Instr_NoFetch_a1 <= FETCH_Instr_NoFetch_a0; |
| always @(posedge clk) FETCH_Instr_NoFetch_a2 <= FETCH_Instr_NoFetch_a1; |
| always @(posedge clk) FETCH_Instr_NoFetch_a3 <= FETCH_Instr_NoFetch_a2; |
| |
| // For $Pc. |
| always @(posedge clk) FETCH_Instr_Pc_a0[31:2] <= FETCH_Instr_Pc_n1[31:2]; |
| always @(posedge clk) FETCH_Instr_Pc_a1[31:2] <= FETCH_Instr_Pc_a0[31:2]; |
| always @(posedge clk) FETCH_Instr_Pc_a2[31:2] <= FETCH_Instr_Pc_a1[31:2]; |
| always @(posedge clk) FETCH_Instr_Pc_a3[31:2] <= FETCH_Instr_Pc_a2[31:2]; |
| |
| // For $RemainingCyclesWithinTimeUnit. |
| always @(posedge clk) FETCH_Instr_RemainingCyclesWithinTimeUnit_a2[30-1:0] <= FETCH_Instr_RemainingCyclesWithinTimeUnit_a1[30-1:0]; |
| |
| // For $aborting_trap. |
| always @(posedge clk) FETCH_Instr_aborting_trap_a3 <= FETCH_Instr_aborting_trap_a2; |
| |
| // For $addr. |
| always @(posedge clkP_FETCH_Instr_ld_st_cond_a3) FETCH_Instr_addr_a3[31:0] <= FETCH_Instr_addr_a2[31:0]; |
| |
| // For $branch. |
| always @(posedge clk) FETCH_Instr_branch_a2 <= FETCH_Instr_branch_a1; |
| |
| // For $branch_or_reset. |
| always @(posedge clk) FETCH_Instr_branch_or_reset_a3 <= FETCH_Instr_branch_or_reset_a2; |
| |
| // For $branch_target. |
| always @(posedge clkP_FETCH_Instr_valid_decode_branch_a2) FETCH_Instr_branch_target_a2[31:2] <= FETCH_Instr_branch_target_a1[31:2]; |
| |
| // For $bypass_avail1. |
| always @(posedge clk) FETCH_Instr_bypass_avail1_a2 <= FETCH_Instr_bypass_avail1_a1; |
| always @(posedge clk) FETCH_Instr_bypass_avail1_a3 <= FETCH_Instr_bypass_avail1_a2; |
| |
| // For $bypass_avail2. |
| always @(posedge clk) FETCH_Instr_bypass_avail2_a2 <= FETCH_Instr_bypass_avail2_a1; |
| always @(posedge clk) FETCH_Instr_bypass_avail2_a3 <= FETCH_Instr_bypass_avail2_a2; |
| |
| // For $commit. |
| always @(posedge clk) FETCH_Instr_commit_a3 <= FETCH_Instr_commit_a2; |
| |
| // For $conditional_branch. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_conditional_branch_a2 <= FETCH_Instr_conditional_branch_a1; |
| |
| // For $csr_cycle. |
| always @(posedge clk) FETCH_Instr_csr_cycle_a2[31:0] <= FETCH_Instr_csr_cycle_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_cycle_a3[31:0] <= FETCH_Instr_csr_cycle_a2[31:0]; |
| |
| // For $csr_cycle_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_cycle_hw_wr_a3 <= FETCH_Instr_csr_cycle_hw_wr_a2; |
| |
| // For $csr_cycleh. |
| always @(posedge clk) FETCH_Instr_csr_cycleh_a2[31:0] <= FETCH_Instr_csr_cycleh_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_cycleh_a3[31:0] <= FETCH_Instr_csr_cycleh_a2[31:0]; |
| |
| // For $csr_cycleh_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_cycleh_hw_wr_a3 <= FETCH_Instr_csr_cycleh_hw_wr_a2; |
| |
| // For $csr_instret. |
| always @(posedge clk) FETCH_Instr_csr_instret_a2[31:0] <= FETCH_Instr_csr_instret_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_instret_a3[31:0] <= FETCH_Instr_csr_instret_a2[31:0]; |
| |
| // For $csr_instret_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_instret_hw_wr_a3 <= FETCH_Instr_csr_instret_hw_wr_a2; |
| |
| // For $csr_instreth. |
| always @(posedge clk) FETCH_Instr_csr_instreth_a2[31:0] <= FETCH_Instr_csr_instreth_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_instreth_a3[31:0] <= FETCH_Instr_csr_instreth_a2[31:0]; |
| |
| // For $csr_instreth_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_instreth_hw_wr_a3 <= FETCH_Instr_csr_instreth_hw_wr_a2; |
| |
| // For $csr_time. |
| always @(posedge clk) FETCH_Instr_csr_time_a2[31:0] <= FETCH_Instr_csr_time_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_time_a3[31:0] <= FETCH_Instr_csr_time_a2[31:0]; |
| |
| // For $csr_time_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_time_hw_wr_a3 <= FETCH_Instr_csr_time_hw_wr_a2; |
| |
| // For $csr_timeh. |
| always @(posedge clk) FETCH_Instr_csr_timeh_a2[31:0] <= FETCH_Instr_csr_timeh_a1[31:0]; |
| always @(posedge clk) FETCH_Instr_csr_timeh_a3[31:0] <= FETCH_Instr_csr_timeh_a2[31:0]; |
| |
| // For $csr_timeh_hw_wr. |
| always @(posedge clk) FETCH_Instr_csr_timeh_hw_wr_a3 <= FETCH_Instr_csr_timeh_hw_wr_a2; |
| |
| // For $csr_trap. |
| always @(posedge clk) FETCH_Instr_csr_trap_a2 <= FETCH_Instr_csr_trap_a1; |
| |
| // For $dest_reg. |
| always @(posedge clk) FETCH_Instr_dest_reg_a2[4:0] <= FETCH_Instr_dest_reg_a1[4:0]; |
| always @(posedge clk) FETCH_Instr_dest_reg_a3[4:0] <= FETCH_Instr_dest_reg_a2[4:0]; |
| |
| // For $dest_reg_valid. |
| always @(posedge clk) FETCH_Instr_dest_reg_valid_a2 <= FETCH_Instr_dest_reg_valid_a1; |
| always @(posedge clk) FETCH_Instr_dest_reg_valid_a3 <= FETCH_Instr_dest_reg_valid_a2; |
| |
| // For $div_mul. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_div_mul_a2 <= FETCH_Instr_div_mul_a1; |
| |
| // For $fetch. |
| always @(posedge clk) FETCH_Instr_fetch_a1 <= FETCH_Instr_fetch_a0; |
| |
| // For $illegal. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_illegal_a2 <= FETCH_Instr_illegal_a1; |
| |
| // For $indirect_jump. |
| always @(posedge clk) FETCH_Instr_indirect_jump_a2 <= FETCH_Instr_indirect_jump_a1; |
| always @(posedge clk) FETCH_Instr_indirect_jump_a3 <= FETCH_Instr_indirect_jump_a2; |
| |
| // For $is_add_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_add_instr_a2 <= FETCH_Instr_is_add_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_add_instr_a3 <= FETCH_Instr_is_add_instr_a2; |
| |
| // For $is_addi_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_addi_instr_a2 <= FETCH_Instr_is_addi_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_addi_instr_a3 <= FETCH_Instr_is_addi_instr_a2; |
| |
| // For $is_and_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_and_instr_a2 <= FETCH_Instr_is_and_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_and_instr_a3 <= FETCH_Instr_is_and_instr_a2; |
| |
| // For $is_andi_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_andi_instr_a2 <= FETCH_Instr_is_andi_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_andi_instr_a3 <= FETCH_Instr_is_andi_instr_a2; |
| |
| // For $is_auipc_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_auipc_instr_a2 <= FETCH_Instr_is_auipc_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_auipc_instr_a3 <= FETCH_Instr_is_auipc_instr_a2; |
| |
| // For $is_b_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_b_type_a2 <= FETCH_Instr_is_b_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_b_type_a3 <= FETCH_Instr_is_b_type_a2; |
| |
| // For $is_beq_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_beq_instr_a2 <= FETCH_Instr_is_beq_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_beq_instr_a3 <= FETCH_Instr_is_beq_instr_a2; |
| |
| // For $is_bge_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_bge_instr_a2 <= FETCH_Instr_is_bge_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_bge_instr_a3 <= FETCH_Instr_is_bge_instr_a2; |
| |
| // For $is_bgeu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_bgeu_instr_a2 <= FETCH_Instr_is_bgeu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_bgeu_instr_a3 <= FETCH_Instr_is_bgeu_instr_a2; |
| |
| // For $is_blt_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_blt_instr_a2 <= FETCH_Instr_is_blt_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_blt_instr_a3 <= FETCH_Instr_is_blt_instr_a2; |
| |
| // For $is_bltu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_bltu_instr_a2 <= FETCH_Instr_is_bltu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_bltu_instr_a3 <= FETCH_Instr_is_bltu_instr_a2; |
| |
| // For $is_bne_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_bne_instr_a2 <= FETCH_Instr_is_bne_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_bne_instr_a3 <= FETCH_Instr_is_bne_instr_a2; |
| |
| // For $is_csr_clear. |
| always @(posedge clk) FETCH_Instr_is_csr_clear_a2 <= FETCH_Instr_is_csr_clear_a1; |
| |
| // For $is_csr_cycle. |
| always @(posedge clk) FETCH_Instr_is_csr_cycle_a2 <= FETCH_Instr_is_csr_cycle_a1; |
| |
| // For $is_csr_cycleh. |
| always @(posedge clk) FETCH_Instr_is_csr_cycleh_a2 <= FETCH_Instr_is_csr_cycleh_a1; |
| |
| // For $is_csr_instret. |
| always @(posedge clk) FETCH_Instr_is_csr_instret_a2 <= FETCH_Instr_is_csr_instret_a1; |
| |
| // For $is_csr_instreth. |
| always @(posedge clk) FETCH_Instr_is_csr_instreth_a2 <= FETCH_Instr_is_csr_instreth_a1; |
| |
| // For $is_csr_set. |
| always @(posedge clk) FETCH_Instr_is_csr_set_a2 <= FETCH_Instr_is_csr_set_a1; |
| |
| // For $is_csr_time. |
| always @(posedge clk) FETCH_Instr_is_csr_time_a2 <= FETCH_Instr_is_csr_time_a1; |
| |
| // For $is_csr_timeh. |
| always @(posedge clk) FETCH_Instr_is_csr_timeh_a2 <= FETCH_Instr_is_csr_timeh_a1; |
| |
| // For $is_csr_write. |
| always @(posedge clk) FETCH_Instr_is_csr_write_a2 <= FETCH_Instr_is_csr_write_a1; |
| |
| // For $is_csrrc_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrc_instr_a2 <= FETCH_Instr_is_csrrc_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrc_instr_a3 <= FETCH_Instr_is_csrrc_instr_a2; |
| |
| // For $is_csrrci_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrci_instr_a2 <= FETCH_Instr_is_csrrci_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrci_instr_a3 <= FETCH_Instr_is_csrrci_instr_a2; |
| |
| // For $is_csrrs_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrs_instr_a2 <= FETCH_Instr_is_csrrs_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrs_instr_a3 <= FETCH_Instr_is_csrrs_instr_a2; |
| |
| // For $is_csrrsi_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrsi_instr_a2 <= FETCH_Instr_is_csrrsi_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrsi_instr_a3 <= FETCH_Instr_is_csrrsi_instr_a2; |
| |
| // For $is_csrrw_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrw_instr_a2 <= FETCH_Instr_is_csrrw_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrw_instr_a3 <= FETCH_Instr_is_csrrw_instr_a2; |
| |
| // For $is_csrrwi_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_csrrwi_instr_a2 <= FETCH_Instr_is_csrrwi_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_csrrwi_instr_a3 <= FETCH_Instr_is_csrrwi_instr_a2; |
| |
| // For $is_i_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_i_type_a2 <= FETCH_Instr_is_i_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_i_type_a3 <= FETCH_Instr_is_i_type_a2; |
| |
| // For $is_j_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_j_type_a2 <= FETCH_Instr_is_j_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_j_type_a3 <= FETCH_Instr_is_j_type_a2; |
| |
| // For $is_jal_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_jal_instr_a2 <= FETCH_Instr_is_jal_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_jal_instr_a3 <= FETCH_Instr_is_jal_instr_a2; |
| |
| // For $is_jalr_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_jalr_instr_a2 <= FETCH_Instr_is_jalr_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_jalr_instr_a3 <= FETCH_Instr_is_jalr_instr_a2; |
| |
| // For $is_lb_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lb_instr_a2 <= FETCH_Instr_is_lb_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lb_instr_a3 <= FETCH_Instr_is_lb_instr_a2; |
| |
| // For $is_lbu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lbu_instr_a2 <= FETCH_Instr_is_lbu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lbu_instr_a3 <= FETCH_Instr_is_lbu_instr_a2; |
| |
| // For $is_lh_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lh_instr_a2 <= FETCH_Instr_is_lh_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lh_instr_a3 <= FETCH_Instr_is_lh_instr_a2; |
| |
| // For $is_lhu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lhu_instr_a2 <= FETCH_Instr_is_lhu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lhu_instr_a3 <= FETCH_Instr_is_lhu_instr_a2; |
| |
| // For $is_lui_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lui_instr_a2 <= FETCH_Instr_is_lui_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lui_instr_a3 <= FETCH_Instr_is_lui_instr_a2; |
| |
| // For $is_lw_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_lw_instr_a2 <= FETCH_Instr_is_lw_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_lw_instr_a3 <= FETCH_Instr_is_lw_instr_a2; |
| |
| // For $is_or_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_or_instr_a2 <= FETCH_Instr_is_or_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_or_instr_a3 <= FETCH_Instr_is_or_instr_a2; |
| |
| // For $is_ori_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_ori_instr_a2 <= FETCH_Instr_is_ori_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_ori_instr_a3 <= FETCH_Instr_is_ori_instr_a2; |
| |
| // For $is_r_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_r_type_a2 <= FETCH_Instr_is_r_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_r_type_a3 <= FETCH_Instr_is_r_type_a2; |
| |
| // For $is_s_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_s_type_a2 <= FETCH_Instr_is_s_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_s_type_a3 <= FETCH_Instr_is_s_type_a2; |
| |
| // For $is_sb_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sb_instr_a2 <= FETCH_Instr_is_sb_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sb_instr_a3 <= FETCH_Instr_is_sb_instr_a2; |
| |
| // For $is_sh_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sh_instr_a2 <= FETCH_Instr_is_sh_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sh_instr_a3 <= FETCH_Instr_is_sh_instr_a2; |
| |
| // For $is_sll_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sll_instr_a2 <= FETCH_Instr_is_sll_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sll_instr_a3 <= FETCH_Instr_is_sll_instr_a2; |
| |
| // For $is_slli_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_slli_instr_a2 <= FETCH_Instr_is_slli_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_slli_instr_a3 <= FETCH_Instr_is_slli_instr_a2; |
| |
| // For $is_slt_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_slt_instr_a2 <= FETCH_Instr_is_slt_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_slt_instr_a3 <= FETCH_Instr_is_slt_instr_a2; |
| |
| // For $is_slti_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_slti_instr_a2 <= FETCH_Instr_is_slti_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_slti_instr_a3 <= FETCH_Instr_is_slti_instr_a2; |
| |
| // For $is_sltiu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sltiu_instr_a2 <= FETCH_Instr_is_sltiu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sltiu_instr_a3 <= FETCH_Instr_is_sltiu_instr_a2; |
| |
| // For $is_sltu_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sltu_instr_a2 <= FETCH_Instr_is_sltu_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sltu_instr_a3 <= FETCH_Instr_is_sltu_instr_a2; |
| |
| // For $is_sra_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sra_instr_a2 <= FETCH_Instr_is_sra_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sra_instr_a3 <= FETCH_Instr_is_sra_instr_a2; |
| |
| // For $is_srai_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_srai_instr_a2 <= FETCH_Instr_is_srai_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_srai_instr_a3 <= FETCH_Instr_is_srai_instr_a2; |
| |
| // For $is_srl_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_srl_instr_a2 <= FETCH_Instr_is_srl_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_srl_instr_a3 <= FETCH_Instr_is_srl_instr_a2; |
| |
| // For $is_srli_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_srli_instr_a2 <= FETCH_Instr_is_srli_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_srli_instr_a3 <= FETCH_Instr_is_srli_instr_a2; |
| |
| // For $is_sub_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sub_instr_a2 <= FETCH_Instr_is_sub_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sub_instr_a3 <= FETCH_Instr_is_sub_instr_a2; |
| |
| // For $is_sw_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_sw_instr_a2 <= FETCH_Instr_is_sw_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_sw_instr_a3 <= FETCH_Instr_is_sw_instr_a2; |
| |
| // For $is_u_type. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_u_type_a2 <= FETCH_Instr_is_u_type_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_u_type_a3 <= FETCH_Instr_is_u_type_a2; |
| |
| // For $is_xor_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_xor_instr_a2 <= FETCH_Instr_is_xor_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_xor_instr_a3 <= FETCH_Instr_is_xor_instr_a2; |
| |
| // For $is_xori_instr. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_is_xori_instr_a2 <= FETCH_Instr_is_xori_instr_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_is_xori_instr_a3 <= FETCH_Instr_is_xori_instr_a2; |
| |
| // For $jump. |
| always @(posedge clk) FETCH_Instr_jump_a2 <= FETCH_Instr_jump_a1; |
| always @(posedge clk) FETCH_Instr_jump_a3 <= FETCH_Instr_jump_a2; |
| |
| // For $jump_target. |
| always @(posedge clkP_FETCH_Instr_jump_a2) FETCH_Instr_jump_target_a2[31:2] <= FETCH_Instr_jump_target_a1[31:2]; |
| |
| // For $ld. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_ld_a2 <= FETCH_Instr_ld_a1; |
| |
| // For $ld_st. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_ld_st_a2 <= FETCH_Instr_ld_st_a1; |
| |
| // For $ld_st_half. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_ld_st_half_a2 <= FETCH_Instr_ld_st_half_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_ld_st_half_a3 <= FETCH_Instr_ld_st_half_a2; |
| |
| // For $ld_st_word. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_ld_st_word_a2 <= FETCH_Instr_ld_st_word_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_ld_st_word_a3 <= FETCH_Instr_ld_st_word_a2; |
| |
| // For $misaligned_jump_target. |
| always @(posedge clkP_FETCH_Instr_jump_a2) FETCH_Instr_misaligned_jump_target_a2 <= FETCH_Instr_misaligned_jump_target_a1; |
| |
| // For $misaligned_pc. |
| always @(posedge clkP_FETCH_Instr_valid_decode_branch_a2) FETCH_Instr_misaligned_pc_a2 <= FETCH_Instr_misaligned_pc_a1; |
| |
| // For $mispred_branch. |
| always @(posedge clk) FETCH_Instr_mispred_branch_a3 <= FETCH_Instr_mispred_branch_a2; |
| |
| // For $non_aborting_trap. |
| always @(posedge clk) FETCH_Instr_non_aborting_trap_a3 <= FETCH_Instr_non_aborting_trap_a2; |
| |
| // For $non_pipelined. |
| always @(posedge clk) FETCH_Instr_non_pipelined_a3 <= FETCH_Instr_non_pipelined_a2; |
| |
| // For $pc. |
| always @(posedge clk) FETCH_Instr_pc_a3[31:2] <= FETCH_Instr_pc_a2[31:2]; |
| |
| // For $pc_inc. |
| always @(posedge clk) FETCH_Instr_pc_inc_a1[31:2] <= FETCH_Instr_pc_inc_a0[31:2]; |
| always @(posedge clk) FETCH_Instr_pc_inc_a2[31:2] <= FETCH_Instr_pc_inc_a1[31:2]; |
| always @(posedge clk) FETCH_Instr_pc_inc_a3[31:2] <= FETCH_Instr_pc_inc_a2[31:2]; |
| |
| // For $pred_taken. |
| always @(posedge clkP_FETCH_Instr_branch_a2) FETCH_Instr_pred_taken_a2 <= FETCH_Instr_pred_taken_a1; |
| |
| // For $pred_taken_branch. |
| always @(posedge clk) FETCH_Instr_pred_taken_branch_a2 <= FETCH_Instr_pred_taken_branch_a1; |
| always @(posedge clk) FETCH_Instr_pred_taken_branch_a3 <= FETCH_Instr_pred_taken_branch_a2; |
| |
| // For $raw_b_imm. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_b_imm_a2[31:0] <= FETCH_Instr_raw_b_imm_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_b_imm_a3[31:0] <= FETCH_Instr_raw_b_imm_a2[31:0]; |
| |
| // For $raw_funct3. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_funct3_a2[2] <= FETCH_Instr_raw_funct3_a1[2]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_funct3_a3[2] <= FETCH_Instr_raw_funct3_a2[2]; |
| |
| // For $raw_funct7. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_funct7_a2[6:0] <= FETCH_Instr_raw_funct7_a1[6:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_funct7_a3[6:0] <= FETCH_Instr_raw_funct7_a2[6:0]; |
| |
| // For $raw_i_imm. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_i_imm_a2[31:0] <= FETCH_Instr_raw_i_imm_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_i_imm_a3[31:0] <= FETCH_Instr_raw_i_imm_a2[31:0]; |
| |
| // For $raw_j_imm. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_j_imm_a2[31:0] <= FETCH_Instr_raw_j_imm_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_j_imm_a3[31:0] <= FETCH_Instr_raw_j_imm_a2[31:0]; |
| |
| // For $raw_rd. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_rd_a2[4:0] <= FETCH_Instr_raw_rd_a1[4:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_rd_a3[4:0] <= FETCH_Instr_raw_rd_a2[4:0]; |
| |
| // For $raw_rs1. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_rs1_a2[4:0] <= FETCH_Instr_raw_rs1_a1[4:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_rs1_a3[4:0] <= FETCH_Instr_raw_rs1_a2[4:0]; |
| |
| // For $raw_rs2. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_rs2_a2[4:0] <= FETCH_Instr_raw_rs2_a1[4:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_rs2_a3[4:0] <= FETCH_Instr_raw_rs2_a2[4:0]; |
| |
| // For $raw_rs3. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_rs3_a2[4:0] <= FETCH_Instr_raw_rs3_a1[4:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_rs3_a3[4:0] <= FETCH_Instr_raw_rs3_a2[4:0]; |
| |
| // For $raw_s_imm. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_s_imm_a2[31:0] <= FETCH_Instr_raw_s_imm_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_s_imm_a3[31:0] <= FETCH_Instr_raw_s_imm_a2[31:0]; |
| |
| // For $raw_u_imm. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_raw_u_imm_a2[31:0] <= FETCH_Instr_raw_u_imm_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_raw_u_imm_a3[31:0] <= FETCH_Instr_raw_u_imm_a2[31:0]; |
| |
| // For $reg_wr_pending. |
| always @(posedge clk) FETCH_Instr_reg_wr_pending_a2 <= FETCH_Instr_reg_wr_pending_a1; |
| always @(posedge clk) FETCH_Instr_reg_wr_pending_a3 <= FETCH_Instr_reg_wr_pending_a2; |
| |
| // For $replay. |
| always @(posedge clk) FETCH_Instr_replay_a2 <= FETCH_Instr_replay_a1; |
| always @(posedge clk) FETCH_Instr_replay_a3 <= FETCH_Instr_replay_a2; |
| |
| // For $reset. |
| always @(posedge clk) FETCH_Instr_reset_a0 <= FETCH_Instr_reset_n1; |
| always @(posedge clk) FETCH_Instr_reset_a1 <= FETCH_Instr_reset_a0; |
| always @(posedge clk) FETCH_Instr_reset_a2 <= FETCH_Instr_reset_a1; |
| always @(posedge clk) FETCH_Instr_reset_a3 <= FETCH_Instr_reset_a2; |
| |
| // For $rslt. |
| always @(posedge clk) FETCH_Instr_rslt_a3[31:0] <= FETCH_Instr_rslt_a2[31:0]; |
| |
| // For $second_issue. |
| always @(posedge clk) FETCH_Instr_second_issue_a1 <= FETCH_Instr_second_issue_a0; |
| always @(posedge clk) FETCH_Instr_second_issue_a2 <= FETCH_Instr_second_issue_a1; |
| always @(posedge clk) FETCH_Instr_second_issue_a3 <= FETCH_Instr_second_issue_a2; |
| |
| // For $second_issue_ld. |
| always @(posedge clk) FETCH_Instr_second_issue_ld_a1 <= FETCH_Instr_second_issue_ld_a0; |
| always @(posedge clk) FETCH_Instr_second_issue_ld_a2 <= FETCH_Instr_second_issue_ld_a1; |
| |
| // For $spec_ld. |
| always @(posedge clk) FETCH_Instr_spec_ld_a2 <= FETCH_Instr_spec_ld_a1; |
| always @(posedge clk) FETCH_Instr_spec_ld_a3 <= FETCH_Instr_spec_ld_a2; |
| |
| // For $st. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) FETCH_Instr_st_a2 <= FETCH_Instr_st_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) FETCH_Instr_st_a3 <= FETCH_Instr_st_a2; |
| |
| // For $st_mask. |
| always @(posedge clkP_FETCH_Instr_st_cond_a3) FETCH_Instr_st_mask_a3[3:0] <= FETCH_Instr_st_mask_a2[3:0]; |
| |
| // For $st_value. |
| always @(posedge clkP_FETCH_Instr_st_cond_a3) FETCH_Instr_st_value_a3[31:0] <= FETCH_Instr_st_value_a2[31:0]; |
| |
| // For $trap_target. |
| always @(posedge clk) FETCH_Instr_trap_target_a3[31:2] <= FETCH_Instr_trap_target_a2[31:2]; |
| |
| // For $valid_decode. |
| always @(posedge clk) FETCH_Instr_valid_decode_a2 <= FETCH_Instr_valid_decode_a1; |
| always @(posedge clk) FETCH_Instr_valid_decode_a3 <= FETCH_Instr_valid_decode_a2; |
| |
| // For $valid_decode_branch. |
| always @(posedge clk) FETCH_Instr_valid_decode_branch_a2 <= FETCH_Instr_valid_decode_branch_a1; |
| |
| // For $valid_dest_reg_valid. |
| always @(posedge clk) FETCH_Instr_valid_dest_reg_valid_a3 <= FETCH_Instr_valid_dest_reg_valid_a2; |
| |
| // For $valid_ld. |
| always @(posedge clk) FETCH_Instr_valid_ld_a3 <= FETCH_Instr_valid_ld_a2; |
| |
| // For $valid_st. |
| always @(posedge clk) FETCH_Instr_valid_st_a3 <= FETCH_Instr_valid_st_a2; |
| |
| |
| // |
| // Scope: /orig_inst |
| // |
| |
| // For $dest_reg. |
| always @(posedge clkP_FETCH_Instr_second_issue_a1) FETCH_Instr_OrigInst_dest_reg_a1[4:0] <= FETCH_Instr_OrigInst_dest_reg_a0[4:0]; |
| |
| // For $pc. |
| always @(posedge clkP_FETCH_Instr_second_issue_a1) FETCH_Instr_OrigInst_pc_a1[31:2] <= FETCH_Instr_OrigInst_pc_a0[31:2]; |
| always @(posedge clkP_FETCH_Instr_second_issue_a2) FETCH_Instr_OrigInst_pc_a2[31:2] <= FETCH_Instr_OrigInst_pc_a1[31:2]; |
| always @(posedge clkP_FETCH_Instr_second_issue_a3) FETCH_Instr_OrigInst_pc_a3[31:2] <= FETCH_Instr_OrigInst_pc_a2[31:2]; |
| |
| |
| // |
| // Scope: /src[2:1] |
| // |
| for (src = 1; src <= 2; src=src+1) begin : L1gen_FETCH_Instr_OrigInst_Src |
| // For $dummy. |
| always @(posedge clkP_FETCH_Instr_second_issue_a1) L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a1 <= L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a0; |
| always @(posedge clkP_FETCH_Instr_second_issue_a2) L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a2 <= L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a1; |
| always @(posedge clkP_FETCH_Instr_second_issue_a3) L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a3 <= L1_FETCH_Instr_OrigInst_Src[src].L1_dummy_a2; |
| |
| end |
| |
| |
| // |
| // Scope: /orig_load_inst |
| // |
| |
| // For $addr. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_addr_a1[1:0] <= FETCH_Instr_OrigLoadInst_addr_a0[1:0]; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_addr_a2[1:0] <= FETCH_Instr_OrigLoadInst_addr_a1[1:0]; |
| |
| // This is an unconditioned version of the condition signal. |
| assign FETCH_Instr_OrigLoadInst_g0_spec_ld_cond_a2 = FETCH_Instr_OrigLoadInst_spec_ld_cond_a2 && FETCH_Instr_second_issue_ld_a2; |
| |
| // For $ld_st_half. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_ld_st_half_a1 <= FETCH_Instr_OrigLoadInst_ld_st_half_a0; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_ld_st_half_a2 <= FETCH_Instr_OrigLoadInst_ld_st_half_a1; |
| |
| // For $ld_st_word. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_ld_st_word_a1 <= FETCH_Instr_OrigLoadInst_ld_st_word_a0; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_ld_st_word_a2 <= FETCH_Instr_OrigLoadInst_ld_st_word_a1; |
| |
| // For $ld_value. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_ld_value_a1[31:0] <= FETCH_Instr_OrigLoadInst_ld_value_a0[31:0]; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_ld_value_a2[31:0] <= FETCH_Instr_OrigLoadInst_ld_value_a1[31:0]; |
| |
| // For $raw_funct3. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_raw_funct3_a1[2] <= FETCH_Instr_OrigLoadInst_raw_funct3_a0[2]; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_raw_funct3_a2[2] <= FETCH_Instr_OrigLoadInst_raw_funct3_a1[2]; |
| |
| // For $spec_ld. |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a1) FETCH_Instr_OrigLoadInst_spec_ld_a1 <= FETCH_Instr_OrigLoadInst_spec_ld_a0; |
| always @(posedge clkP_FETCH_Instr_second_issue_ld_a2) FETCH_Instr_OrigLoadInst_spec_ld_a2 <= FETCH_Instr_OrigLoadInst_spec_ld_a1; |
| |
| |
| |
| // |
| // Scope: /regs[31:1] |
| // |
| for (regs = 1; regs <= 31; regs=regs+1) begin : L1gen_FETCH_Instr_Regs |
| // For $pending. |
| always @(posedge clk) FETCH_Instr_Regs_pending_a3[regs] <= FETCH_Instr_Regs_pending_a2[regs]; |
| |
| end |
| |
| // |
| // Scope: /src[2:1] |
| // |
| for (src = 1; src <= 2; src=src+1) begin : L1gen_FETCH_Instr_Src |
| // For $dummy. |
| always @(posedge clk) L1c_FETCH_Instr_Src[src].L1_dummy_a2 <= L1c_FETCH_Instr_Src[src].L1_dummy_a1; |
| always @(posedge clk) L1c_FETCH_Instr_Src[src].L1_dummy_a3 <= L1c_FETCH_Instr_Src[src].L1_dummy_a2; |
| |
| // For $is_reg. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) L1_FETCH_Instr_Src[src].L1_is_reg_a2 <= L1_FETCH_Instr_Src[src].L1_is_reg_a1; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) L1_FETCH_Instr_Src[src].L1_is_reg_a3 <= L1_FETCH_Instr_Src[src].L1_is_reg_a2; |
| |
| // For $is_reg_condition. |
| always @(posedge clk) L1b_FETCH_Instr_Src[src].L1_is_reg_condition_a2 <= L1b_FETCH_Instr_Src[src].L1_is_reg_condition_a1; |
| |
| // For $reg. |
| always @(posedge clkP_FETCH_Instr_valid_decode_a2) L1_FETCH_Instr_Src[src].L1_reg_a2[4:0] <= L1_FETCH_Instr_Src[src].L1_reg_a1[4:0]; |
| always @(posedge clkP_FETCH_Instr_valid_decode_a3) L1_FETCH_Instr_Src[src].L1_reg_a3[4:0] <= L1_FETCH_Instr_Src[src].L1_reg_a2[4:0]; |
| |
| // For $reg_value. |
| always @(posedge clkP_FETCH_Instr_Src_is_reg_condition_a2[src]) L1b_FETCH_Instr_Src[src].L1_reg_value_a2[31:0] <= L1b_FETCH_Instr_Src[src].L1_reg_value_a1[31:0]; |
| always @(posedge clkP_FETCH_Instr_Src_is_reg_condition_a3[src]) L1b_FETCH_Instr_Src[src].L1_reg_value_a3[31:0] <= L1b_FETCH_Instr_Src[src].L1_reg_value_a2[31:0]; |
| |
| end |
| |
| |
| |
| // |
| // Scope: |mem |
| // |
| |
| |
| // |
| // Scope: /data |
| // |
| |
| // For $addr. |
| always @(posedge clk) MEM_Data_addr_a4[1:0] <= MEM_Data_addr_a3[1:0]; |
| |
| // For $dest_reg. |
| always @(posedge clk) MEM_Data_dest_reg_a4[4:0] <= MEM_Data_dest_reg_a3[4:0]; |
| |
| // For $ld_st_half. |
| always @(posedge clk) MEM_Data_ld_st_half_a4 <= MEM_Data_ld_st_half_a3; |
| |
| // For $ld_st_word. |
| always @(posedge clk) MEM_Data_ld_st_word_a4 <= MEM_Data_ld_st_word_a3; |
| |
| // For $pc. |
| always @(posedge clk) MEM_Data_pc_a4[31:2] <= MEM_Data_pc_a3[31:2]; |
| |
| // For $raw_funct3. |
| always @(posedge clk) MEM_Data_raw_funct3_a4[2] <= MEM_Data_raw_funct3_a3[2]; |
| |
| // For $spec_ld. |
| always @(posedge clk) MEM_Data_spec_ld_a4 <= MEM_Data_spec_ld_a3; |
| |
| // For $valid_ld. |
| always @(posedge clk) MEM_Data_valid_ld_a4 <= MEM_Data_valid_ld_a3; |
| |
| |
| // |
| // Scope: /src[2:1] |
| // |
| for (src = 1; src <= 2; src=src+1) begin : L1gen_MEM_Data_Src |
| // For $dummy. |
| always @(posedge clk) L1_MEM_Data_Src[src].L1_dummy_a4 <= L1_MEM_Data_Src[src].L1_dummy_a3; |
| |
| end |
| |
| |
| |
| |
| endgenerate |
| |
| |
| |
| // |
| // Gated clocks. |
| // |
| |
| generate |
| |
| |
| |
| // |
| // Scope: |fetch |
| // |
| |
| |
| // |
| // Scope: /instr |
| // |
| |
| clk_gate gen_clkF_FETCH_Instr_branch_or_reset_a3(clkF_FETCH_Instr_branch_or_reset_a3, clk, FETCH_Instr_branch_or_reset_a2, 1'b1, 1'b0); |
| clk_gate gen_clkF_FETCH_Instr_branch_or_reset_a4(clkF_FETCH_Instr_branch_or_reset_a4, clk, FETCH_Instr_branch_or_reset_a3, 1'b1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_branch_a2(clkP_FETCH_Instr_branch_a2, clk, 1'b1, FETCH_Instr_branch_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_jump_a2(clkP_FETCH_Instr_jump_a2, clk, 1'b1, FETCH_Instr_jump_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_ld_st_cond_a3(clkP_FETCH_Instr_ld_st_cond_a3, clk, 1'b1, FETCH_Instr_ld_st_cond_a2, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_second_issue_a1(clkP_FETCH_Instr_second_issue_a1, clk, 1'b1, FETCH_Instr_second_issue_a0, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_second_issue_a2(clkP_FETCH_Instr_second_issue_a2, clk, 1'b1, FETCH_Instr_second_issue_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_second_issue_a3(clkP_FETCH_Instr_second_issue_a3, clk, 1'b1, FETCH_Instr_second_issue_a2, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_second_issue_ld_a1(clkP_FETCH_Instr_second_issue_ld_a1, clk, 1'b1, FETCH_Instr_second_issue_ld_a0, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_second_issue_ld_a2(clkP_FETCH_Instr_second_issue_ld_a2, clk, 1'b1, FETCH_Instr_second_issue_ld_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_st_cond_a3(clkP_FETCH_Instr_st_cond_a3, clk, 1'b1, FETCH_Instr_st_cond_a2, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_valid_decode_a2(clkP_FETCH_Instr_valid_decode_a2, clk, 1'b1, FETCH_Instr_valid_decode_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_valid_decode_a3(clkP_FETCH_Instr_valid_decode_a3, clk, 1'b1, FETCH_Instr_valid_decode_a2, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_valid_decode_branch_a2(clkP_FETCH_Instr_valid_decode_branch_a2, clk, 1'b1, FETCH_Instr_valid_decode_branch_a1, 1'b0); |
| |
| // |
| // Scope: /src[2:1] |
| // |
| for (src = 1; src <= 2; src=src+1) begin : L1clk_FETCH_Instr_Src |
| clk_gate gen_clkP_FETCH_Instr_Src_is_reg_condition_a2(clkP_FETCH_Instr_Src_is_reg_condition_a2[src], clk, 1'b1, L1b_FETCH_Instr_Src[src].L1_is_reg_condition_a1, 1'b0); |
| clk_gate gen_clkP_FETCH_Instr_Src_is_reg_condition_a3(clkP_FETCH_Instr_Src_is_reg_condition_a3[src], clk, 1'b1, L1b_FETCH_Instr_Src[src].L1_is_reg_condition_a2, 1'b0); |
| end |
| |
| |
| |
| |
| endgenerate |
| |
| |
| |
| generate // This is awkward, but we need to go into 'generate' context in the line that `includes the declarations file. |
