verilog/rtl/wb_interface.v

`line 2 "wb_interface.tlv" 0 //_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.12-2022/01/27-beta
`include "sp_verilog.vh" //_\SV

   // =========================================
   // Welcome!  Try the tutorials via the menu.
   // =========================================

   // Default Makerchip TL-Verilog Code Template

   // Macro providing required top-level module definition, random
   // stimulus support, and Verilator config.
	

   module wb_interface(input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output clk0,
    output csb0,
    output web0,
    output [3:0] wmask0,
    output [31:0] din0,
    output [8:0]  addr0,
    output wbs_ack_o,
    output processor_reset);
   
   wire clk;
   assign clk = wb_clk_i;
`include "wb_interface_gen.v" //_\TLV
   assign L0_valid_addr_a0 = wbs_adr_i[31:24] == 8'h30;
   assign processor_reset = (wbs_adr_i[31:24] == 8'h31) ? wbs_dat_i[0] : '0;
   assign L0_valid_a0 = wbs_cyc_i && wbs_stb_i;
   assign L0_ready_a0 = L0_valid_a0 && !L0_ready_a1;
   assign clk0 = wb_clk_i;
   assign csb0 = (L0_valid_addr_a0 && L0_valid_a0) ? '0 : '1;
   assign web0  = !wbs_we_i;
   assign wmask0 = wbs_sel_i & {4{wbs_we_i}};
   assign din0 = wbs_dat_i;
   assign addr0 = wbs_adr_i[10:2];
   assign wbs_ack_o = L0_ready_a0 || (wbs_adr_i[31:24] == 8'h31); endgenerate
//_\SV
   endmodule