1. b7e6a21 MPW5, little buffer + netlist by Jorge Marin · 3 years ago
  2. 435020e MPW5, little buffer by Jorge Marin · 3 years ago
  3. b8d4297 Full top cell connection to wrapper upload, DRC and netgen .spice by Jorge Marin · 3 years, 2 months ago
  4. e52d8c4 Full top cell connection to wrapper upload, DRC fixed by Jorge Marin · 3 years, 2 months ago
  5. 0903ce2 Full top cell connection to wrapper upload by Jorge Marin · 3 years, 2 months ago
  6. 9413811 First layout upload by Jorge Marin · 3 years, 2 months ago
  7. ea5ff7d Updated the layout to properly use the metal resistors in front of by Tim Edwards · 3 years, 2 months ago
  8. ab6ba9c Modified the user_analog_project_wrapper layouts (empty and example) by Tim Edwards · 3 years, 5 months ago
  9. 9422266 Modified the wrapper to extend the analog pins out 4um like the rest of by Tim Edwards · 3 years, 10 months ago
  10. 35111e9 Corrected ngspice testbenches for change in the name of the parameter by Tim Edwards · 3 years, 10 months ago
  11. a26abdd Redid the layout for the example analog project based on the updated by Tim Edwards · 3 years, 10 months ago
  12. 6bb2165 Added layout for the user_analog_project_wrapper example. by Tim Edwards · 3 years, 10 months ago
  13. dfc24ad Added xschem schematic of the POR and testbench simulations and results. by Tim Edwards · 3 years, 10 months ago
  14. fb13001 Simple layout, unwired (needs modifications to the project wrapper) by Tim Edwards · 3 years, 10 months ago
  15. a44a60b Preliminary work on the analog user project example. Added verilog RTL and by Tim Edwards · 3 years, 10 months ago