| commit | b8d4297fbfd0593101db3d0bd8fc2680b12cd2f3 | [log] [tgz] |
|---|---|---|
| author | Jorge Marin <jorge.marin.ndez@gmail.com> | Sat Jan 08 00:53:31 2022 -0300 |
| committer | Jorge Marin <jorge.marin.ndez@gmail.com> | Sat Jan 08 00:53:31 2022 -0300 |
| tree | d8d86eae46dd84a5e65bc6c91d2e3a0e4ad3eeeb | |
| parent | e52d8c46174d13248ac4c353e6f055ce6bc9bff8 [diff] |
Full top cell connection to wrapper upload, DRC and netgen .spice
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.