| commit | b7e6a21e24ee2c70e2a3d6c0e8ef43c1c6ad03b1 | [log] [tgz] |
|---|---|---|
| author | Jorge Marin <jorge.marin.ndez@gmail.com> | Tue Mar 22 02:12:23 2022 -0300 |
| committer | Jorge Marin <jorge.marin.ndez@gmail.com> | Tue Mar 22 02:12:23 2022 -0300 |
| tree | e313cfe119aaea631b0ab49d6c267ac1856e0884 | |
| parent | 435020ed9c5da8379b4ed6fc290e23ff24ade583 [diff] |
MPW5, little buffer + netlist
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.