Full top cell connection to wrapper upload, DRC fixed
22 files changed
tree: b630180896a85bf3aaeb4be1e1ece86e202bafad
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

Caravel Analog User

License CI Caravan Build

PLL-BASED CAPACITIVE SENSOR INTERFACE

This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:

image

The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:

image

The characteristic plot for an average window of 10us is seen below:

image

Refer to README for this sample project documentation.