1. 0f01622 Final run for precheck by mrg · 3 years, 8 months ago
  2. 9184a51 Update latest version by mrg · 3 years, 8 months ago
  3. e988856 Update SP SRAMs to have spare_wen0 by mrg · 3 years, 8 months ago
  4. 48dbc1e Update macros by mrg · 3 years, 9 months ago
  5. 45f14ab Add all dual port memories by mrg · 3 years, 9 months ago
  6. 8269657 Macro with two clock ports by AmoghLonkar · 3 years, 9 months ago
  7. a44330c Macros from new verilog control by AmoghLonkar · 3 years, 9 months ago
  8. 7503247 Adding macro files by AmoghLonkar · 3 years, 9 months ago
  9. 20d0669 remove extra files from repo; gbl routing to 0.2 by Jesse Cirimelli-Low · 3 years, 9 months ago
  10. 4fc0624 update lef power names by Jesse Cirimelli-Low · 3 years, 9 months ago
  11. 9bff904 Moved files to proper directories by AmoghLonkar · 3 years, 9 months ago
  12. 43506d4 Delete openram_testchip.lef by Amogh Lonkar · 3 years, 9 months ago
  13. 1a8f9b7 New lef file by AmoghLonkar · 3 years, 9 months ago
  14. 56cda99 New SRAM macro by AmoghLonkar · 3 years, 9 months ago
  15. f56156e Adding lef files by AmoghLonkar · 3 years, 9 months ago
  16. a2ff3b4 [DATA] Update views by manarabdelaty · 3 years, 10 months ago
  17. 609ec98 [DATA] Update views by manarabdelaty · 3 years, 10 months ago
  18. 3e3151b [DATA] update views to reflect rtl change by manarabdelaty · 3 years, 11 months ago
  19. 548e5a7 [DATA] Adjust user_proj_example/config.tcl by Ahmed Ghazy · 3 years, 11 months ago
  20. d4ec2f0 Example of a full run of user_project_wrapper by Ahmed Ghazy · 3 years, 11 months ago