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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-009/a44330c3d71af81a2af97ed289894a8f764cc38f
commit
a44330c3d71af81a2af97ed289894a8f764cc38f
[log] [tgz]
author
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:36:01 2021 -0700
committer
AmoghLonkar <alonkar@ucsc.edu>
Thu Jun 10 22:36:01 2021 -0700
tree
8969f0554ff56d1bf89445f87fa3189a13d425a6
parent
c16cb81976428dd4dae9580ce857985564ae3899 [diff]
Macros from new verilog control
2 files changed
tree: 8969f0554ff56d1bf89445f87fa3189a13d425a6
  1. .github/
  2. chisel/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. signoff/
  11. single_port/
  12. spi/
  13. verilog/
  14. caravel
  15. .gitignore
  16. .gitmodules
  17. info.yaml
  18. LICENSE
  19. Makefile
  20. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.