Macro with two clock ports
2 files changed
tree: d80b57532c08d2a7d264e2cdbbfdd4de3621715a
  1. .github/
  2. chisel/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. signoff/
  11. single_port/
  12. spi/
  13. verilog/
  14. .gitignore
  15. .gitmodules
  16. info.yaml
  17. LICENSE
  18. Makefile
  19. README.md
README.md

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