Add all dual port memories
12 files changed
tree: 8c28cc9c1b5c50ad03435b36f962d76c75b1c5b7
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. single_port/
  11. spi/
  12. verilog/
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

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