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agorararmard6c766a82020-12-10 18:13:12 +02001// SPDX-FileCopyrightText: 2020 Efabless Corporation
agorararmarde5780bf2020-12-09 21:27:56 +00002//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
agorararmardafa96ea2020-12-09 23:37:31 +020014// SPDX-License-Identifier: Apache-2.0
agorararmarde5780bf2020-12-09 21:27:56 +000015
Matt Venn08cd6eb2020-11-16 12:01:14 +010016`default_nettype none
Ahmed Ghazy22d29d62020-10-28 03:42:02 +020017module mem_wb (
Manar61dce922020-11-10 19:26:28 +020018`ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +020019 input VPWR,
20 input VGND,
21`endif
shalanfd13eb52020-08-21 16:48:07 +020022 input wb_clk_i,
23 input wb_rst_i,
24
25 input [31:0] wb_adr_i,
26 input [31:0] wb_dat_i,
27 input [3:0] wb_sel_i,
28 input wb_we_i,
29 input wb_cyc_i,
30 input wb_stb_i,
31
32 output wb_ack_o,
33 output [31:0] wb_dat_o
34
35);
Manar6bedda92020-11-02 20:29:07 +020036
37 localparam ADR_WIDTH = $clog2(`MEM_WORDS);
38
shalanfd13eb52020-08-21 16:48:07 +020039 wire valid;
40 wire ram_wen;
41 wire [3:0] wen; // write enable
42
43 assign valid = wb_cyc_i & wb_stb_i;
44 assign ram_wen = wb_we_i && valid;
45
46 assign wen = wb_sel_i & {4{ram_wen}} ;
47
shalanfd13eb52020-08-21 16:48:07 +020048 /*
49 Ack Generation
50 - write transaction: asserted upon receiving adr_i & dat_i
51 - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
52 */
53
shalan0d14e6e2020-08-31 16:50:48 +020054 reg wb_ack_read;
55 reg wb_ack_o;
shalanfd13eb52020-08-21 16:48:07 +020056
57 always @(posedge wb_clk_i) begin
58 if (wb_rst_i == 1'b 1) begin
shalan0d14e6e2020-08-31 16:50:48 +020059 wb_ack_read <= 1'b0;
60 wb_ack_o <= 1'b0;
shalanfd13eb52020-08-21 16:48:07 +020061 end else begin
shalan0d14e6e2020-08-31 16:50:48 +020062 // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]};
63 wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
64 wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
shalanfd13eb52020-08-21 16:48:07 +020065 end
66 end
67
Ahmed Ghazy22d29d62020-10-28 03:42:02 +020068 soc_mem
69`ifndef USE_OPENRAM
Manar6bedda92020-11-02 20:29:07 +020070 #(
71 .WORDS(`MEM_WORDS),
72 .ADR_WIDTH(ADR_WIDTH)
73 )
Ahmed Ghazy22d29d62020-10-28 03:42:02 +020074`endif
75 mem (
Manar61dce922020-11-10 19:26:28 +020076 `ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +020077 .VPWR(VPWR),
78 .VGND(VGND),
79 `endif
shalanfd13eb52020-08-21 16:48:07 +020080 .clk(wb_clk_i),
81 .ena(valid),
82 .wen(wen),
Manar6bedda92020-11-02 20:29:07 +020083 .addr(wb_adr_i[ADR_WIDTH+1:2]),
shalanfd13eb52020-08-21 16:48:07 +020084 .wdata(wb_dat_i),
85 .rdata(wb_dat_o)
86 );
87
88endmodule
89
90module soc_mem
91`ifndef USE_OPENRAM
92#(
Manar6bedda92020-11-02 20:29:07 +020093 parameter integer WORDS = 256,
94 parameter ADR_WIDTH = 8
shalanfd13eb52020-08-21 16:48:07 +020095)
96`endif
97 (
Manar61dce922020-11-10 19:26:28 +020098`ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +020099 input VPWR,
100 input VGND,
101`endif
shalanfd13eb52020-08-21 16:48:07 +0200102 input clk,
103 input ena,
104 input [3:0] wen,
Manar6bedda92020-11-02 20:29:07 +0200105 input [ADR_WIDTH-1:0] addr,
shalanfd13eb52020-08-21 16:48:07 +0200106 input [31:0] wdata,
107 output[31:0] rdata
108);
109
110`ifndef USE_OPENRAM
Manar8f131792020-11-11 16:38:32 +0200111 DFFRAM #(.COLS(`COLS)) SRAM (
Manar61dce922020-11-10 19:26:28 +0200112 `ifdef USE_POWER_PINS
Manar68e03632020-11-09 13:25:13 +0200113 .VPWR(VPWR),
114 .VGND(VGND),
115 `endif
Ahmed Ghazy5586f1b2020-11-06 21:34:43 +0200116 .CLK(clk),
117 .WE(wen),
118 .EN(ena),
119 .Di(wdata),
120 .Do(rdata),
121 // 8-bit address if using the default custom DFF RAM
122 .A(addr)
123 );
shalanfd13eb52020-08-21 16:48:07 +0200124`else
125
126 /* Using Port 0 Only - Size: 1KB, 256x32 bits */
127 //sram_1rw1r_32_256_8_scn4m_subm
Manar14d35ac2020-10-21 22:47:15 +0200128 sram_1rw1r_32_256_8_sky130 SRAM(
shalanfd13eb52020-08-21 16:48:07 +0200129 .clk0(clk),
130 .csb0(~ena),
131 .web0(~|wen),
132 .wmask0(wen),
Manar14d35ac2020-10-21 22:47:15 +0200133 .addr0(addr[7:0]),
shalanfd13eb52020-08-21 16:48:07 +0200134 .din0(wdata),
135 .dout0(rdata)
136 );
137
138`endif
139
Ahmed Ghazy5586f1b2020-11-06 21:34:43 +0200140endmodule
Tim Edwards581068f2020-11-19 12:45:25 -0500141`default_nettype wire