agorararmard | 6c766a8 | 2020-12-10 18:13:12 +0200 | [diff] [blame] | 1 | // SPDX-FileCopyrightText: 2020 Efabless Corporation |
agorararmard | e5780bf | 2020-12-09 21:27:56 +0000 | [diff] [blame] | 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
agorararmard | afa96ea | 2020-12-09 23:37:31 +0200 | [diff] [blame] | 14 | // SPDX-License-Identifier: Apache-2.0 |
agorararmard | e5780bf | 2020-12-09 21:27:56 +0000 | [diff] [blame] | 15 | |
Matt Venn | 08cd6eb | 2020-11-16 12:01:14 +0100 | [diff] [blame] | 16 | `default_nettype none |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 17 | module mem_wb ( |
Manar | 61dce92 | 2020-11-10 19:26:28 +0200 | [diff] [blame] | 18 | `ifdef USE_POWER_PINS |
Manar | 68e0363 | 2020-11-09 13:25:13 +0200 | [diff] [blame] | 19 | input VPWR, |
| 20 | input VGND, |
| 21 | `endif |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 22 | input wb_clk_i, |
| 23 | input wb_rst_i, |
| 24 | |
| 25 | input [31:0] wb_adr_i, |
| 26 | input [31:0] wb_dat_i, |
| 27 | input [3:0] wb_sel_i, |
| 28 | input wb_we_i, |
| 29 | input wb_cyc_i, |
| 30 | input wb_stb_i, |
| 31 | |
| 32 | output wb_ack_o, |
| 33 | output [31:0] wb_dat_o |
| 34 | |
| 35 | ); |
Manar | 6bedda9 | 2020-11-02 20:29:07 +0200 | [diff] [blame] | 36 | |
| 37 | localparam ADR_WIDTH = $clog2(`MEM_WORDS); |
| 38 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 39 | wire valid; |
| 40 | wire ram_wen; |
| 41 | wire [3:0] wen; // write enable |
| 42 | |
| 43 | assign valid = wb_cyc_i & wb_stb_i; |
| 44 | assign ram_wen = wb_we_i && valid; |
| 45 | |
| 46 | assign wen = wb_sel_i & {4{ram_wen}} ; |
| 47 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 48 | /* |
| 49 | Ack Generation |
| 50 | - write transaction: asserted upon receiving adr_i & dat_i |
| 51 | - read transaction : asserted one clock cycle after receiving the adr_i & dat_i |
| 52 | */ |
| 53 | |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 54 | reg wb_ack_read; |
| 55 | reg wb_ack_o; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 56 | |
| 57 | always @(posedge wb_clk_i) begin |
| 58 | if (wb_rst_i == 1'b 1) begin |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 59 | wb_ack_read <= 1'b0; |
| 60 | wb_ack_o <= 1'b0; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 61 | end else begin |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 62 | // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]}; |
| 63 | wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read; |
| 64 | wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 65 | end |
| 66 | end |
| 67 | |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 68 | soc_mem |
| 69 | `ifndef USE_OPENRAM |
Manar | 6bedda9 | 2020-11-02 20:29:07 +0200 | [diff] [blame] | 70 | #( |
| 71 | .WORDS(`MEM_WORDS), |
| 72 | .ADR_WIDTH(ADR_WIDTH) |
| 73 | ) |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 74 | `endif |
| 75 | mem ( |
Manar | 61dce92 | 2020-11-10 19:26:28 +0200 | [diff] [blame] | 76 | `ifdef USE_POWER_PINS |
Manar | 68e0363 | 2020-11-09 13:25:13 +0200 | [diff] [blame] | 77 | .VPWR(VPWR), |
| 78 | .VGND(VGND), |
| 79 | `endif |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 80 | .clk(wb_clk_i), |
| 81 | .ena(valid), |
| 82 | .wen(wen), |
Manar | 6bedda9 | 2020-11-02 20:29:07 +0200 | [diff] [blame] | 83 | .addr(wb_adr_i[ADR_WIDTH+1:2]), |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 84 | .wdata(wb_dat_i), |
| 85 | .rdata(wb_dat_o) |
| 86 | ); |
| 87 | |
| 88 | endmodule |
| 89 | |
| 90 | module soc_mem |
| 91 | `ifndef USE_OPENRAM |
| 92 | #( |
Manar | 6bedda9 | 2020-11-02 20:29:07 +0200 | [diff] [blame] | 93 | parameter integer WORDS = 256, |
| 94 | parameter ADR_WIDTH = 8 |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 95 | ) |
| 96 | `endif |
| 97 | ( |
Manar | 61dce92 | 2020-11-10 19:26:28 +0200 | [diff] [blame] | 98 | `ifdef USE_POWER_PINS |
Manar | 68e0363 | 2020-11-09 13:25:13 +0200 | [diff] [blame] | 99 | input VPWR, |
| 100 | input VGND, |
| 101 | `endif |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 102 | input clk, |
| 103 | input ena, |
| 104 | input [3:0] wen, |
Manar | 6bedda9 | 2020-11-02 20:29:07 +0200 | [diff] [blame] | 105 | input [ADR_WIDTH-1:0] addr, |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 106 | input [31:0] wdata, |
| 107 | output[31:0] rdata |
| 108 | ); |
| 109 | |
| 110 | `ifndef USE_OPENRAM |
Manar | 8f13179 | 2020-11-11 16:38:32 +0200 | [diff] [blame] | 111 | DFFRAM #(.COLS(`COLS)) SRAM ( |
Manar | 61dce92 | 2020-11-10 19:26:28 +0200 | [diff] [blame] | 112 | `ifdef USE_POWER_PINS |
Manar | 68e0363 | 2020-11-09 13:25:13 +0200 | [diff] [blame] | 113 | .VPWR(VPWR), |
| 114 | .VGND(VGND), |
| 115 | `endif |
Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 116 | .CLK(clk), |
| 117 | .WE(wen), |
| 118 | .EN(ena), |
| 119 | .Di(wdata), |
| 120 | .Do(rdata), |
| 121 | // 8-bit address if using the default custom DFF RAM |
| 122 | .A(addr) |
| 123 | ); |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 124 | `else |
| 125 | |
| 126 | /* Using Port 0 Only - Size: 1KB, 256x32 bits */ |
| 127 | //sram_1rw1r_32_256_8_scn4m_subm |
Manar | 14d35ac | 2020-10-21 22:47:15 +0200 | [diff] [blame] | 128 | sram_1rw1r_32_256_8_sky130 SRAM( |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 129 | .clk0(clk), |
| 130 | .csb0(~ena), |
| 131 | .web0(~|wen), |
| 132 | .wmask0(wen), |
Manar | 14d35ac | 2020-10-21 22:47:15 +0200 | [diff] [blame] | 133 | .addr0(addr[7:0]), |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 134 | .din0(wdata), |
| 135 | .dout0(rdata) |
| 136 | ); |
| 137 | |
| 138 | `endif |
| 139 | |
Ahmed Ghazy | 5586f1b | 2020-11-06 21:34:43 +0200 | [diff] [blame] | 140 | endmodule |
Tim Edwards | 581068f | 2020-11-19 12:45:25 -0500 | [diff] [blame] | 141 | `default_nettype wire |