Add a global defines.v and rely less on parameters
- This is mainly to avoid "accidents" with default parameter values
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 882f1c7..f9cfd62 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,6 +1,4 @@
-module mem_wb # (
- parameter integer MEM_WORDS = 256
-) (
+module mem_wb (
input wb_clk_i,
input wb_rst_i,
@@ -50,7 +48,11 @@
`endif
- soc_mem mem(
+ soc_mem
+`ifndef USE_OPENRAM
+ #(.WORDS(`MEM_WORDS))
+`endif
+ mem (
.clk(wb_clk_i),
.ena(valid),
.wen(wen),
