commit	0d14e6eb07affadbc58815c657f701914bb37a2a	[log] [tgz]
author	shalan	Mon Aug 31 16:50:48 2020 +0200
committer	shalan	Mon Aug 31 16:50:48 2020 +0200
tree	279aab06f9ab27ba838682595e28214f9d58acc9
parent	fd13eb528fb15e206e969380e4b4fb529931790d [diff]

harness phase1 initial commit

README.md[diff]
doc/README.md[diff]
doc/ciic_harness.png[Added - diff]
doc/counter_32.png[Added - diff]
doc/mgmt_soc_memory_map.png[Added - diff]
verilog/README.md[Deleted - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/harness/defs.h[Renamed from verilog/dv/harness/mgmt_soc/defs.h - diff]
verilog/dv/harness/mgmt_soc/Makefile[diff]
verilog/dv/harness/mgmt_soc/gpio/Makefile[diff]
verilog/dv/harness/mgmt_soc/gpio/gpio.c[diff]
verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v[diff]
verilog/dv/harness/mgmt_soc/hkspi/Makefile[diff]
verilog/dv/harness/mgmt_soc/hkspi/hkspi.c[diff]
verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v[diff]
verilog/dv/harness/mgmt_soc/mem/Makefile[diff]
verilog/dv/harness/mgmt_soc/mem/mem.c[diff]
verilog/dv/harness/mgmt_soc/mem/mem_tb.v[diff]
verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile[Added - diff]
verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c[Added - diff]
verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v[Renamed from verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v - diff]
verilog/dv/harness/mgmt_soc/perf/Makefile[diff]
verilog/dv/harness/mgmt_soc/perf/perf.c[diff]
verilog/dv/harness/mgmt_soc/perf/perf_tb.v[diff]
verilog/dv/harness/mgmt_soc/sysctrl/Makefile[diff]
verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c[diff]
verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v[diff]
verilog/dv/harness/mgmt_soc/uart/Makefile[diff]
verilog/dv/harness/mgmt_soc/uart/uart.c[diff]
verilog/dv/harness/mgmt_soc/uart/uart_tb.v[diff]
verilog/dv/harness/mgmt_soc/xbar/Makefile[Deleted - diff]
verilog/dv/harness/mgmt_soc/xbar/xbar.c[Deleted - diff]
verilog/dv/harness/mprj_counter/Makefile[Renamed from verilog/dv/wb/Makefile - diff]
verilog/dv/harness/mprj_counter/README.md[Added - diff]
verilog/dv/harness/mprj_counter/io_ports/Makefile[Added - diff]
verilog/dv/harness/mprj_counter/io_ports/io_ports.c[Added - diff]
verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/harness/mprj_counter/la_test1/Makefile[Added - diff]
verilog/dv/harness/mprj_counter/la_test1/la_test1.c[Added - diff]
verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/harness/mprj_counter/la_test2/Makefile[Added - diff]
verilog/dv/harness/mprj_counter/la_test2/la_test2.c[Added - diff]
verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/harness/sections.lds[Renamed from verilog/dv/harness/mgmt_soc/sections.lds - diff]
verilog/dv/harness/spiflash.v[Renamed from verilog/dv/harness/mgmt_soc/spiflash.v - diff]
verilog/dv/harness/start.s[Renamed from verilog/dv/harness/mgmt_soc/start.s - diff]
verilog/dv/harness/stub.c[Added - diff]
verilog/dv/harness/tbuart.v[Renamed from verilog/dv/harness/mgmt_soc/tbuart.v - diff]
verilog/dv/harness/verify.log[Renamed from verilog/dv/harness/mgmt_soc/verify.log - diff]
verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v[Deleted - diff]
verilog/dv/wb/crossbar_wb/Makefile[Deleted - diff]
verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v[Deleted - diff]
verilog/dv/wb/distributor/Makefile[Deleted - diff]
verilog/dv/wb/distributor/distributor_tb.v[Deleted - diff]
verilog/dv/wb/distributor/distributor_tb.vcd[Deleted - diff]
verilog/dv/wb/la_wb/la_wb_tb.vcd[Deleted - diff]
verilog/dv/wb/la_wb/ldo_wb_tb.vcd[Deleted - diff]
verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd[Deleted - diff]
verilog/dv/wb_utests/Makefile[Copied from verilog/dv/wb/Makefile - diff]
verilog/dv/wb_utests/gpio_wb/Makefile[Renamed from verilog/dv/wb/gpio_wb/Makefile - diff]
verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v[Renamed from verilog/dv/wb/gpio_wb/gpio_wb_tb.v - diff]
verilog/dv/wb_utests/intercon_wb/Makefile[Renamed from verilog/dv/wb/intercon_wb/Makefile - diff]
verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v[Renamed from verilog/dv/wb/intercon_wb/intercon_wb_tb.v - diff]
verilog/dv/wb_utests/la_wb/Makefile[Renamed from verilog/dv/wb/la_wb/Makefile - diff]
verilog/dv/wb_utests/la_wb/la_wb_tb.v[Renamed from verilog/dv/wb/la_wb/la_wb_tb.v - diff]
verilog/dv/wb_utests/mem_wb/Makefile[Renamed from verilog/dv/wb/mem_wb/Makefile - diff]
verilog/dv/wb_utests/mem_wb/mem_wb_tb.v[Renamed from verilog/dv/wb/mem_wb/mem_wb_tb.v - diff]
verilog/dv/wb_utests/mprj_ctrl/Makefile[Renamed from verilog/dv/wb/arbiter_wb/Makefile - diff]
verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v[Added - diff]
verilog/dv/wb_utests/spi_sysctrl_wb/Makefile[Renamed from verilog/dv/wb/spi_sysctrl_wb/Makefile - diff]
verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v[Renamed from verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v - diff]
verilog/dv/wb_utests/spimemio_wb/Makefile[Renamed from verilog/dv/wb/spimemio_wb/Makefile - diff]
verilog/dv/wb_utests/spimemio_wb/flash.hex[Renamed from verilog/dv/wb/spimemio_wb/flash.hex - diff]
verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v[Renamed from verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v - diff]
verilog/dv/wb_utests/sysctrl_wb/Makefile[Renamed from verilog/dv/wb/sysctrl_wb/Makefile - diff]
verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v[Renamed from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v - diff]
verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd[Renamed from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd - diff]
verilog/dv/wb_utests/uart_wb/Makefile[Renamed from verilog/dv/wb/uart_wb/Makefile - diff]
verilog/dv/wb_utests/uart_wb/uart_wb_tb.v[Renamed from verilog/dv/wb/uart_wb/uart_wb_tb.v - diff]
verilog/ip/arbiter.v[Deleted - diff]
verilog/ip/crossbar.v[Deleted - diff]
verilog/ip/distributor.v[Deleted - diff]
verilog/rtl/chip_io.v[Added - diff]
verilog/rtl/harness.v[Deleted - diff]
verilog/rtl/harness_chip.v[Added - diff]
verilog/rtl/la_wb.v[diff]
verilog/rtl/mem_wb.v[diff]
verilog/rtl/mgmt_core.v[Added - diff]
verilog/rtl/mgmt_soc.v[diff]
verilog/rtl/mprj_counter.v[Added - diff]
verilog/rtl/mprj_ctrl.v[Added - diff]
verilog/rtl/mprj_io.v[Added - diff]
verilog/rtl/pads.v[Added - diff]
verilog/rtl/sram_1rw1r_32_8192_8_sky130.v[Renamed from verilog/rtl/sram_1rw1r_32_256_8_sky130.v - diff]

94 files changed

tree: 279aab06f9ab27ba838682595e28214f9d58acc9

README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

Configure Mega Project I/O pads
Observe and control Mega Project signals (through on-chip logic analyzer probes)
Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.